2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "vc4_context.h"
29 #include "util/ralloc.h"
32 vc4_dump_program(struct vc4_compile
*c
)
34 fprintf(stderr
, "%s prog %d/%d QPU:\n",
35 qir_get_stage_name(c
->stage
),
36 c
->program_id
, c
->variant_id
);
38 for (int i
= 0; i
< c
->qpu_inst_count
; i
++) {
39 fprintf(stderr
, "0x%016"PRIx64
" ", c
->qpu_insts
[i
]);
40 vc4_qpu_disasm(&c
->qpu_insts
[i
], 1);
41 fprintf(stderr
, "\n");
46 queue(struct vc4_compile
*c
, uint64_t inst
)
48 struct queued_qpu_inst
*q
= rzalloc(c
, struct queued_qpu_inst
);
50 insert_at_tail(&c
->qpu_inst_list
, &q
->link
);
54 last_inst(struct vc4_compile
*c
)
56 struct queued_qpu_inst
*q
=
57 (struct queued_qpu_inst
*)last_elem(&c
->qpu_inst_list
);
62 set_last_cond_add(struct vc4_compile
*c
, uint32_t cond
)
64 *last_inst(c
) = qpu_set_cond_add(*last_inst(c
), cond
);
68 * Some special registers can be read from either file, which lets us resolve
69 * raddr conflicts without extra MOVs.
72 swap_file(struct qpu_reg
*src
)
77 if (src
->mux
== QPU_MUX_SMALL_IMM
) {
80 if (src
->mux
== QPU_MUX_A
)
93 * This is used to resolve the fact that we might register-allocate two
94 * different operands of an instruction to the same physical register file
95 * even though instructions have only one field for the register file source
98 * In that case, we need to move one to a temporary that can be used in the
99 * instruction, instead.
102 fixup_raddr_conflict(struct vc4_compile
*c
,
104 struct qpu_reg
*src0
, struct qpu_reg
*src1
,
107 uint32_t mux0
= src0
->mux
== QPU_MUX_SMALL_IMM
? QPU_MUX_B
: src0
->mux
;
108 uint32_t mux1
= src1
->mux
== QPU_MUX_SMALL_IMM
? QPU_MUX_B
: src1
->mux
;
110 if (mux0
<= QPU_MUX_R5
||
112 (src0
->addr
== src1
->addr
&&
113 src0
->mux
== src1
->mux
)) {
117 if (swap_file(src0
) || swap_file(src1
))
120 if (mux0
== QPU_MUX_A
) {
121 /* If we're conflicting over the A regfile, then we can just
122 * use the reserved rb31.
124 queue(c
, qpu_a_MOV(qpu_rb(31), *src1
));
128 /* Otherwise, we need a non-B regfile. So, we spill r3 out to
129 * rb31, then store our desired value in r3, and tell the
130 * caller to put rb31 back into r3 when we're done.
133 queue(c
, qpu_a_MOV(qpu_rb(31), qpu_r3()));
134 queue(c
, qpu_a_MOV(qpu_r3(), *src1
));
138 return r3_live
&& dst
.mux
!= QPU_MUX_R3
;
143 vc4_generate_code(struct vc4_context
*vc4
, struct vc4_compile
*c
)
145 struct qpu_reg
*temp_registers
= vc4_register_allocate(vc4
, c
);
146 bool discard
= false;
147 uint32_t inputs_remaining
= c
->num_inputs
;
148 uint32_t vpm_read_fifo_count
= 0;
149 uint32_t vpm_read_offset
= 0;
150 int last_vpm_read_index
= -1;
151 bool written_r3
= false;
153 /* Map from the QIR ops enum order to QPU unpack bits. */
154 static const uint32_t unpack_map
[] = {
159 QPU_UNPACK_16A_TO_F32
,
160 QPU_UNPACK_16B_TO_F32
,
163 make_empty_list(&c
->qpu_inst_list
);
168 /* There's a 4-entry FIFO for VPMVCD reads, each of which can
169 * load up to 16 dwords (4 vec4s) per vertex.
171 while (inputs_remaining
) {
172 uint32_t num_entries
= MIN2(inputs_remaining
, 16);
173 queue(c
, qpu_load_imm_ui(qpu_vrsetup(),
176 ((num_entries
& 0xf) << 20)));
177 inputs_remaining
-= num_entries
;
178 vpm_read_offset
+= num_entries
;
179 vpm_read_fifo_count
++;
181 assert(vpm_read_fifo_count
<= 4);
183 queue(c
, qpu_load_imm_ui(qpu_vwsetup(), 0x00001a00));
189 struct simple_node
*node
;
190 foreach(node
, &c
->instructions
) {
191 struct qinst
*qinst
= (struct qinst
*)node
;
194 fprintf(stderr
, "translating qinst to qpu: ");
195 qir_dump_inst(qinst
);
196 fprintf(stderr
, "\n");
199 static const struct {
203 #define A(name) [QOP_##name] = {QPU_A_##name, false}
204 #define M(name) [QOP_##name] = {QPU_M_##name, true}
229 struct qpu_reg src
[4];
230 for (int i
= 0; i
< qir_get_op_nsrc(qinst
->op
); i
++) {
231 int index
= qinst
->src
[i
].index
;
232 switch (qinst
->src
[i
].file
) {
237 src
[i
] = temp_registers
[index
];
245 case QFILE_SMALL_IMM
:
246 src
[i
].mux
= QPU_MUX_SMALL_IMM
;
247 src
[i
].addr
= qpu_encode_small_immediate(qinst
->src
[i
].index
);
248 /* This should only have returned a valid
249 * small immediate field, not ~0 for failure.
251 assert(src
[i
].addr
<= 47);
254 assert((int)qinst
->src
[i
].index
>=
255 last_vpm_read_index
);
256 last_vpm_read_index
= qinst
->src
[i
].index
;
257 src
[i
] = qpu_ra(QPU_R_VPM
);
263 switch (qinst
->dst
.file
) {
265 dst
= qpu_ra(QPU_W_NOP
);
268 dst
= temp_registers
[qinst
->dst
.index
];
271 dst
= qpu_ra(QPU_W_VPM
);
275 case QFILE_SMALL_IMM
:
276 assert(!"not reached");
282 /* Skip emitting the MOV if it's a no-op. */
283 if (dst
.mux
== QPU_MUX_A
|| dst
.mux
== QPU_MUX_B
||
284 dst
.mux
!= src
[0].mux
|| dst
.addr
!= src
[0].addr
) {
285 queue(c
, qpu_a_MOV(dst
, src
[0]));
290 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_NOP
), src
[0]));
291 *last_inst(c
) |= QPU_SF
;
298 queue(c
, qpu_a_MOV(dst
, src
[0]));
299 set_last_cond_add(c
, qinst
->op
- QOP_SEL_X_0_ZS
+
302 queue(c
, qpu_a_XOR(dst
, qpu_r0(), qpu_r0()));
303 set_last_cond_add(c
, ((qinst
->op
- QOP_SEL_X_0_ZS
) ^
311 queue(c
, qpu_a_MOV(dst
, src
[0]));
312 set_last_cond_add(c
, qinst
->op
- QOP_SEL_X_Y_ZS
+
315 queue(c
, qpu_a_MOV(dst
, src
[1]));
316 set_last_cond_add(c
, ((qinst
->op
- QOP_SEL_X_Y_ZS
) ^
327 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIP
),
331 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_RECIPSQRT
),
335 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_EXP
),
339 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_SFU_LOG
),
346 queue(c
, qpu_a_MOV(dst
, qpu_r4()));
350 case QOP_PACK_8888_F
:
351 queue(c
, qpu_m_MOV(dst
, src
[0]));
352 *last_inst(c
) |= QPU_PM
;
353 *last_inst(c
) |= QPU_SET_FIELD(QPU_PACK_MUL_8888
,
361 /* If dst doesn't happen to already contain src[0],
362 * then we have to move it in.
364 if (qinst
->src
[0].file
!= QFILE_NULL
&&
365 (src
[0].mux
!= dst
.mux
|| src
[0].addr
!= dst
.addr
)) {
366 /* Don't overwrite src1 while setting up
369 if (dst
.mux
== src
[1].mux
&&
370 dst
.addr
== src
[1].addr
) {
371 queue(c
, qpu_m_MOV(qpu_rb(31), src
[1]));
375 queue(c
, qpu_m_MOV(dst
, src
[0]));
378 queue(c
, qpu_m_MOV(dst
, src
[1]));
379 *last_inst(c
) |= QPU_PM
;
380 *last_inst(c
) |= QPU_SET_FIELD(QPU_PACK_MUL_8A
+
381 qinst
->op
- QOP_PACK_8A_F
,
386 queue(c
, qpu_a_ITOF(dst
,
387 qpu_ra(QPU_R_XY_PIXEL_COORD
)));
391 queue(c
, qpu_a_ITOF(dst
,
392 qpu_rb(QPU_R_XY_PIXEL_COORD
)));
395 case QOP_FRAG_REV_FLAG
:
396 queue(c
, qpu_a_ITOF(dst
,
397 qpu_rb(QPU_R_MS_REV_FLAGS
)));
402 /* QOP_FRAG_Z/W don't emit instructions, just allocate
403 * the register to the Z/W payload.
407 case QOP_TLB_DISCARD_SETUP
:
409 queue(c
, qpu_a_MOV(src
[0], src
[0]));
410 *last_inst(c
) |= QPU_SF
;
413 case QOP_TLB_STENCIL_SETUP
:
414 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_TLB_STENCIL_SETUP
), src
[0]));
417 case QOP_TLB_Z_WRITE
:
418 queue(c
, qpu_a_MOV(qpu_ra(QPU_W_TLB_Z
), src
[0]));
420 set_last_cond_add(c
, QPU_COND_ZS
);
424 case QOP_TLB_COLOR_READ
:
426 *last_inst(c
) = qpu_set_sig(*last_inst(c
),
431 case QOP_TLB_COLOR_WRITE
:
432 queue(c
, qpu_a_MOV(qpu_tlbc(), src
[0]));
434 set_last_cond_add(c
, QPU_COND_ZS
);
439 queue(c
, qpu_a_FADD(dst
, src
[0], qpu_r5()));
442 case QOP_PACK_SCALED
: {
443 uint64_t a
= (qpu_a_MOV(dst
, src
[0]) |
444 QPU_SET_FIELD(QPU_PACK_A_16A
,
446 uint64_t b
= (qpu_a_MOV(dst
, src
[1]) |
447 QPU_SET_FIELD(QPU_PACK_A_16B
,
450 if (dst
.mux
== src
[1].mux
&& dst
.addr
== src
[1].addr
) {
464 queue(c
, qpu_a_MOV(qpu_rb(QPU_W_TMU0_S
+
465 (qinst
->op
- QOP_TEX_S
)),
470 needs_restore
= fixup_raddr_conflict(c
, dst
,
473 queue(c
, qpu_a_ADD(qpu_rb(QPU_W_TMU0_S
), src
[0], src
[1]));
475 queue(c
, qpu_a_MOV(qpu_r3(), qpu_rb(31)));
480 *last_inst(c
) = qpu_set_sig(*last_inst(c
),
485 case QOP_R4_UNPACK_A
:
486 case QOP_R4_UNPACK_B
:
487 case QOP_R4_UNPACK_C
:
488 case QOP_R4_UNPACK_D
:
489 assert(src
[0].mux
== QPU_MUX_R4
);
490 queue(c
, qpu_a_MOV(dst
, src
[0]));
491 *last_inst(c
) |= QPU_PM
;
492 *last_inst(c
) |= QPU_SET_FIELD(QPU_UNPACK_8A
+
499 case QOP_UNPACK_8A_F
:
500 case QOP_UNPACK_8B_F
:
501 case QOP_UNPACK_8C_F
:
502 case QOP_UNPACK_8D_F
:
503 case QOP_UNPACK_16A_F
:
504 case QOP_UNPACK_16B_F
: {
505 assert(src
[0].mux
== QPU_MUX_A
);
507 /* Since we're setting the pack bits, if the
508 * destination is in A it would get re-packed.
510 queue(c
, qpu_a_FMAX((dst
.mux
== QPU_MUX_A
?
513 *last_inst(c
) |= QPU_SET_FIELD(unpack_map
[qinst
->op
-
517 if (dst
.mux
== QPU_MUX_A
) {
518 queue(c
, qpu_a_MOV(dst
, qpu_rb(31)));
523 case QOP_UNPACK_8A_I
:
524 case QOP_UNPACK_8B_I
:
525 case QOP_UNPACK_8C_I
:
526 case QOP_UNPACK_8D_I
:
527 case QOP_UNPACK_16A_I
:
528 case QOP_UNPACK_16B_I
: {
529 assert(src
[0].mux
== QPU_MUX_A
);
531 /* Since we're setting the pack bits, if the
532 * destination is in A it would get re-packed.
534 queue(c
, qpu_a_MOV((dst
.mux
== QPU_MUX_A
?
535 qpu_rb(31) : dst
), src
[0]));
536 *last_inst(c
) |= QPU_SET_FIELD(unpack_map
[qinst
->op
-
540 if (dst
.mux
== QPU_MUX_A
) {
541 queue(c
, qpu_a_MOV(dst
, qpu_rb(31)));
547 assert(qinst
->op
< ARRAY_SIZE(translate
));
548 assert(translate
[qinst
->op
].op
!= 0); /* NOPs */
550 /* If we have only one source, put it in the second
551 * argument slot as well so that we don't take up
552 * another raddr just to get unused data.
554 if (qir_get_op_nsrc(qinst
->op
) == 1)
557 needs_restore
= fixup_raddr_conflict(c
, dst
,
561 if (translate
[qinst
->op
].is_mul
) {
562 queue(c
, qpu_m_alu2(translate
[qinst
->op
].op
,
566 queue(c
, qpu_a_alu2(translate
[qinst
->op
].op
,
571 queue(c
, qpu_a_MOV(qpu_r3(), qpu_rb(31)));
576 if (dst
.mux
== QPU_MUX_R3
)
580 qpu_schedule_instructions(c
);
582 /* thread end can't have VPM write or read */
583 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
584 QPU_WADDR_ADD
) == QPU_W_VPM
||
585 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
586 QPU_WADDR_MUL
) == QPU_W_VPM
||
587 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
588 QPU_RADDR_A
) == QPU_R_VPM
||
589 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
590 QPU_RADDR_B
) == QPU_R_VPM
) {
591 qpu_serialize_one_inst(c
, qpu_NOP());
594 /* thread end can't have uniform read */
595 if (QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
596 QPU_RADDR_A
) == QPU_R_UNIF
||
597 QPU_GET_FIELD(c
->qpu_insts
[c
->qpu_inst_count
- 1],
598 QPU_RADDR_B
) == QPU_R_UNIF
) {
599 qpu_serialize_one_inst(c
, qpu_NOP());
602 /* thread end can't have TLB operations */
603 if (qpu_inst_is_tlb(c
->qpu_insts
[c
->qpu_inst_count
- 1]))
604 qpu_serialize_one_inst(c
, qpu_NOP());
606 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
607 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
609 qpu_serialize_one_inst(c
, qpu_NOP());
610 qpu_serialize_one_inst(c
, qpu_NOP());
617 c
->qpu_insts
[c
->qpu_inst_count
- 1] =
618 qpu_set_sig(c
->qpu_insts
[c
->qpu_inst_count
- 1],
619 QPU_SIG_SCOREBOARD_UNLOCK
);
623 if (vc4_debug
& VC4_DEBUG_QPU
)
626 vc4_qpu_validate(c
->qpu_insts
, c
->qpu_inst_count
);
628 free(temp_registers
);