src/gallium/drivers/vc4/vc4_qpu_schedule.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * @file vc4_qpu_schedule.c
  27  *
  28  * The basic model of the list scheduler is to take a basic block, compute a
  29  * DAG of the dependencies, and make a list of the DAG heads.  Heuristically
  30  * pick a DAG head, then put all the children that are now DAG heads into the
  31  * list of things to schedule.
  32  *
  33  * The goal of scheduling here is to pack pairs of operations together in a
  34  * single QPU instruction.
  35  */
  36
  37 #include "vc4_qir.h"
  38 #include "vc4_qpu.h"
  39 #include "util/ralloc.h"
  40
  41 static bool debug;
  42
  43 struct schedule_node_child;
  44
  45 struct schedule_node {
  46         struct simple_node link;
  47         struct queued_qpu_inst *inst;
  48         struct schedule_node_child *children;
  49         uint32_t child_count;
  50         uint32_t child_array_size;
  51         uint32_t parent_count;
  52
  53         /**
  54          * Minimum number of cycles from scheduling this instruction until the
  55          * end of the program, based on the slowest dependency chain through
  56          * the children.
  57          */
  58         uint32_t delay;
  59
  60         /**
  61          * cycles between this instruction being scheduled and when its result
  62          * can be consumed.
  63          */
  64         uint32_t latency;
  65
  66         /**
  67          * Which uniform from uniform_data[] this instruction read, or -1 if
  68          * not reading a uniform.
  69          */
  70         int uniform;
  71 };
  72
  73 struct schedule_node_child {
  74         struct schedule_node *node;
  75         bool write_after_read;
  76 };
  77
  78 /* When walking the instructions in reverse, we need to swap before/after in
  79  * add_dep().
  80  */
  81 enum direction { F, R };
  82
  83 struct schedule_state {
  84         struct schedule_node *last_r[6];
  85         struct schedule_node *last_ra[32];
  86         struct schedule_node *last_rb[32];
  87         struct schedule_node *last_sf;
  88         struct schedule_node *last_vpm_read;
  89         struct schedule_node *last_tmu_write;
  90         struct schedule_node *last_tlb;
  91         struct schedule_node *last_vpm;
  92         enum direction dir;
  93 };
  94
  95 static void
  96 add_dep(struct schedule_state *state,
  97         struct schedule_node *before,
  98         struct schedule_node *after,
  99         bool write)
 100 {
 101         bool write_after_read = !write && state->dir == R;
 102
 103         if (!before || !after)
 104                 return;
 105
 106         assert(before != after);
 107
 108         if (state->dir == R) {
 109                 struct schedule_node *t = before;
 110                 before = after;
 111                 after = t;
 112         }
 113
 114         for (int i = 0; i < before->child_count; i++) {
 115                 if (before->children[i].node == after &&
 116                     (before->children[i].write_after_read == write_after_read)) {
 117                         return;
 118                 }
 119         }
 120
 121         if (before->child_array_size <= before->child_count) {
 122                 before->child_array_size = MAX2(before->child_array_size * 2, 16);
 123                 before->children = reralloc(before, before->children,
 124                                             struct schedule_node_child,
 125                                             before->child_array_size);
 126         }
 127
 128         before->children[before->child_count].node = after;
 129         before->children[before->child_count].write_after_read =
 130                 write_after_read;
 131         before->child_count++;
 132         after->parent_count++;
 133 }
 134
 135 static void
 136 add_read_dep(struct schedule_state *state,
 137               struct schedule_node *before,
 138               struct schedule_node *after)
 139 {
 140         add_dep(state, before, after, false);
 141 }
 142
 143 static void
 144 add_write_dep(struct schedule_state *state,
 145               struct schedule_node **before,
 146               struct schedule_node *after)
 147 {
 148         add_dep(state, *before, after, true);
 149         *before = after;
 150 }
 151
 152 static bool
 153 qpu_writes_r4(uint64_t inst)
 154 {
 155         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 156
 157         switch(sig) {
 158         case QPU_SIG_COLOR_LOAD:
 159         case QPU_SIG_LOAD_TMU0:
 160         case QPU_SIG_LOAD_TMU1:
 161         case QPU_SIG_ALPHA_MASK_LOAD:
 162                 return true;
 163         default:
 164                 return false;
 165         }
 166 }
 167
 168 static void
 169 process_raddr_deps(struct schedule_state *state, struct schedule_node *n,
 170                    uint32_t raddr, bool is_a)
 171 {
 172         switch (raddr) {
 173         case QPU_R_VARY:
 174                 add_write_dep(state, &state->last_r[5], n);
 175                 break;
 176
 177         case QPU_R_VPM:
 178                 add_write_dep(state, &state->last_vpm_read, n);
 179                 break;
 180
 181         case QPU_R_UNIF:
 182         case QPU_R_NOP:
 183         case QPU_R_ELEM_QPU:
 184         case QPU_R_XY_PIXEL_COORD:
 185         case QPU_R_MS_REV_FLAGS:
 186                 break;
 187
 188         default:
 189                 if (raddr < 32) {
 190                         if (is_a)
 191                                 add_read_dep(state, state->last_ra[raddr], n);
 192                         else
 193                                 add_read_dep(state, state->last_rb[raddr], n);
 194                 } else {
 195                         fprintf(stderr, "unknown raddr %d\n", raddr);
 196                         abort();
 197                 }
 198                 break;
 199         }
 200 }
 201
 202 static bool
 203 is_tmu_write(uint32_t waddr)
 204 {
 205         switch (waddr) {
 206         case QPU_W_TMU0_S:
 207         case QPU_W_TMU0_T:
 208         case QPU_W_TMU0_R:
 209         case QPU_W_TMU0_B:
 210         case QPU_W_TMU1_S:
 211         case QPU_W_TMU1_T:
 212         case QPU_W_TMU1_R:
 213         case QPU_W_TMU1_B:
 214                 return true;
 215         default:
 216                 return false;
 217         }
 218 }
 219
 220 static bool
 221 reads_uniform(uint64_t inst)
 222 {
 223         if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
 224                 return false;
 225
 226         return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
 227                 QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF ||
 228                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
 229                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
 230 }
 231
 232 static void
 233 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
 234                  uint32_t mux)
 235 {
 236         if (mux != QPU_MUX_A && mux != QPU_MUX_B)
 237                 add_read_dep(state, state->last_r[mux], n);
 238 }
 239
 240
 241 static void
 242 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
 243                    uint32_t waddr, bool is_add)
 244 {
 245         uint64_t inst = n->inst->inst;
 246         bool is_a = is_add ^ ((inst & QPU_WS) != 0);
 247
 248         if (waddr < 32) {
 249                 if (is_a) {
 250                         add_write_dep(state, &state->last_ra[waddr], n);
 251                 } else {
 252                         add_write_dep(state, &state->last_rb[waddr], n);
 253                 }
 254         } else if (is_tmu_write(waddr)) {
 255                 add_write_dep(state, &state->last_tmu_write, n);
 256         } else if (qpu_waddr_is_tlb(waddr)) {
 257                 add_write_dep(state, &state->last_tlb, n);
 258         } else {
 259                 switch (waddr) {
 260                 case QPU_W_ACC0:
 261                 case QPU_W_ACC1:
 262                 case QPU_W_ACC2:
 263                 case QPU_W_ACC3:
 264                 case QPU_W_ACC5:
 265                         add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
 266                                       n);
 267                         break;
 268
 269                 case QPU_W_VPM:
 270                         add_write_dep(state, &state->last_vpm, n);
 271                         break;
 272
 273                 case QPU_W_VPMVCD_SETUP:
 274                         if (is_a)
 275                                 add_write_dep(state, &state->last_vpm_read, n);
 276                         else
 277                                 add_write_dep(state, &state->last_vpm, n);
 278                         break;
 279
 280                 case QPU_W_SFU_RECIP:
 281                 case QPU_W_SFU_RECIPSQRT:
 282                 case QPU_W_SFU_EXP:
 283                 case QPU_W_SFU_LOG:
 284                         add_write_dep(state, &state->last_r[4], n);
 285                         break;
 286
 287                 case QPU_W_TLB_STENCIL_SETUP:
 288                         /* This isn't a TLB operation that does things like
 289                          * implicitly lock the scoreboard, but it does have to
 290                          * appear before TLB_Z, and each of the TLB_STENCILs
 291                          * have to schedule in the same order relative to each
 292                          * other.
 293                          */
 294                         add_write_dep(state, &state->last_tlb, n);
 295                         break;
 296
 297                 case QPU_W_NOP:
 298                         break;
 299
 300                 default:
 301                         fprintf(stderr, "Unknown waddr %d\n", waddr);
 302                         abort();
 303                 }
 304         }
 305 }
 306
 307 static void
 308 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
 309                   uint32_t cond)
 310 {
 311         switch (cond) {
 312         case QPU_COND_NEVER:
 313         case QPU_COND_ALWAYS:
 314                 break;
 315         default:
 316                 add_read_dep(state, state->last_sf, n);
 317                 break;
 318         }
 319 }
 320
 321 /**
 322  * Common code for dependencies that need to be tracked both forward and
 323  * backward.
 324  *
 325  * This is for things like "all reads of r4 have to happen between the r4
 326  * writes that surround them".
 327  */
 328 static void
 329 calculate_deps(struct schedule_state *state, struct schedule_node *n)
 330 {
 331         uint64_t inst = n->inst->inst;
 332         uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
 333         uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
 334         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 335         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 336         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 337         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 338         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
 339         uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 340         uint32_t mul_a = QPU_GET_FIELD(inst, QPU_MUL_A);
 341         uint32_t mul_b = QPU_GET_FIELD(inst, QPU_MUL_B);
 342         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 343
 344         if (sig != QPU_SIG_LOAD_IMM) {
 345                 process_raddr_deps(state, n, raddr_a, true);
 346                 process_raddr_deps(state, n, raddr_b, false);
 347         }
 348
 349         if (add_op != QPU_A_NOP) {
 350                 process_mux_deps(state, n, add_a);
 351                 process_mux_deps(state, n, add_b);
 352         }
 353         if (mul_op != QPU_M_NOP) {
 354                 process_mux_deps(state, n, mul_a);
 355                 process_mux_deps(state, n, mul_b);
 356         }
 357
 358         process_waddr_deps(state, n, waddr_add, true);
 359         process_waddr_deps(state, n, waddr_mul, false);
 360         if (qpu_writes_r4(inst))
 361                 add_write_dep(state, &state->last_r[4], n);
 362
 363         switch (sig) {
 364         case QPU_SIG_SW_BREAKPOINT:
 365         case QPU_SIG_NONE:
 366         case QPU_SIG_THREAD_SWITCH:
 367         case QPU_SIG_LAST_THREAD_SWITCH:
 368         case QPU_SIG_SMALL_IMM:
 369         case QPU_SIG_LOAD_IMM:
 370                 break;
 371
 372         case QPU_SIG_LOAD_TMU0:
 373         case QPU_SIG_LOAD_TMU1:
 374                 /* TMU loads are coming from a FIFO, so ordering is important.
 375                  */
 376                 add_write_dep(state, &state->last_tmu_write, n);
 377                 break;
 378
 379         case QPU_SIG_COLOR_LOAD:
 380                 add_read_dep(state, state->last_tlb, n);
 381                 break;
 382
 383         case QPU_SIG_PROG_END:
 384         case QPU_SIG_WAIT_FOR_SCOREBOARD:
 385         case QPU_SIG_SCOREBOARD_UNLOCK:
 386         case QPU_SIG_COVERAGE_LOAD:
 387         case QPU_SIG_COLOR_LOAD_END:
 388         case QPU_SIG_ALPHA_MASK_LOAD:
 389         case QPU_SIG_BRANCH:
 390                 fprintf(stderr, "Unhandled signal bits %d\n", sig);
 391                 abort();
 392         }
 393
 394         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
 395         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
 396         if (inst & QPU_SF)
 397                 add_write_dep(state, &state->last_sf, n);
 398 }
 399
 400 static void
 401 calculate_forward_deps(struct vc4_compile *c, struct simple_node *schedule_list)
 402 {
 403         struct simple_node *node;
 404         struct schedule_state state;
 405
 406         memset(&state, 0, sizeof(state));
 407         state.dir = F;
 408
 409         foreach(node, schedule_list)
 410                 calculate_deps(&state, (struct schedule_node *)node);
 411 }
 412
 413 static void
 414 calculate_reverse_deps(struct vc4_compile *c, struct simple_node *schedule_list)
 415 {
 416         struct simple_node *node;
 417         struct schedule_state state;
 418
 419         memset(&state, 0, sizeof(state));
 420         state.dir = R;
 421
 422         for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
 423                 calculate_deps(&state, (struct schedule_node *)node);
 424         }
 425 }
 426
 427 struct choose_scoreboard {
 428         int tick;
 429         int last_sfu_write_tick;
 430         uint32_t last_waddr_a, last_waddr_b;
 431 };
 432
 433 static bool
 434 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst)
 435 {
 436         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 437         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 438         uint32_t src_muxes[] = {
 439                 QPU_GET_FIELD(inst, QPU_ADD_A),
 440                 QPU_GET_FIELD(inst, QPU_ADD_B),
 441                 QPU_GET_FIELD(inst, QPU_MUL_A),
 442                 QPU_GET_FIELD(inst, QPU_MUL_B),
 443         };
 444         for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
 445                 if ((src_muxes[i] == QPU_MUX_A &&
 446                      raddr_a < 32 &&
 447                      scoreboard->last_waddr_a == raddr_a) ||
 448                     (src_muxes[i] == QPU_MUX_B &&
 449                      raddr_b < 32 &&
 450                      scoreboard->last_waddr_b == raddr_b)) {
 451                         return true;
 452                 }
 453
 454                 if (src_muxes[i] == QPU_MUX_R4) {
 455                         if (scoreboard->tick -
 456                             scoreboard->last_sfu_write_tick <= 2) {
 457                                 return true;
 458                         }
 459                 }
 460         }
 461
 462         return false;
 463 }
 464
 465 static bool
 466 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst)
 467 {
 468         return (scoreboard->tick < 2 && qpu_inst_is_tlb(inst));
 469 }
 470
 471 static int
 472 get_instruction_priority(uint64_t inst)
 473 {
 474         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 475         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 476         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 477         uint32_t baseline_score;
 478         uint32_t next_score = 0;
 479
 480         /* Schedule TLB operations as late as possible, to get more
 481          * parallelism between shaders.
 482          */
 483         if (qpu_inst_is_tlb(inst))
 484                 return next_score;
 485         next_score++;
 486
 487         /* Schedule texture read results collection late to hide latency. */
 488         if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
 489                 return next_score;
 490         next_score++;
 491
 492         /* Default score for things that aren't otherwise special. */
 493         baseline_score = next_score;
 494         next_score++;
 495
 496         /* Schedule texture read setup early to hide their latency better. */
 497         if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
 498                 return next_score;
 499         next_score++;
 500
 501         return baseline_score;
 502 }
 503
 504 static struct schedule_node *
 505 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard,
 506                                struct simple_node *schedule_list,
 507                                struct schedule_node *prev_inst)
 508 {
 509         struct schedule_node *chosen = NULL;
 510         struct simple_node *node;
 511         int chosen_prio = 0;
 512
 513         foreach(node, schedule_list) {
 514                 struct schedule_node *n = (struct schedule_node *)node;
 515                 uint64_t inst = n->inst->inst;
 516
 517                 /* "An instruction must not read from a location in physical
 518                  *  regfile A or B that was written to by the previous
 519                  *  instruction."
 520                  */
 521                 if (reads_too_soon_after_write(scoreboard, inst))
 522                         continue;
 523
 524                 /* "A scoreboard wait must not occur in the first two
 525                  *  instructions of a fragment shader. This is either the
 526                  *  explicit Wait for Scoreboard signal or an implicit wait
 527                  *  with the first tile-buffer read or write instruction."
 528                  */
 529                 if (pixel_scoreboard_too_soon(scoreboard, inst))
 530                         continue;
 531
 532                 /* If we're trying to pair with another instruction, check
 533                  * that they're compatible.
 534                  */
 535                 if (prev_inst) {
 536                         if (prev_inst->uniform != -1 && n->uniform != -1)
 537                                 continue;
 538
 539                         inst = qpu_merge_inst(prev_inst->inst->inst, inst);
 540                         if (!inst)
 541                                 continue;
 542                 }
 543
 544                 int prio = get_instruction_priority(inst);
 545
 546                 /* Found a valid instruction.  If nothing better comes along,
 547                  * this one works.
 548                  */
 549                 if (!chosen) {
 550                         chosen = n;
 551                         chosen_prio = prio;
 552                         continue;
 553                 }
 554
 555                 if (prio > chosen_prio) {
 556                         chosen = n;
 557                         chosen_prio = prio;
 558                 } else if (prio < chosen_prio) {
 559                         continue;
 560                 }
 561
 562                 if (n->delay > chosen->delay) {
 563                         chosen = n;
 564                         chosen_prio = prio;
 565                 } else if (n->delay < chosen->delay) {
 566                         continue;
 567                 }
 568         }
 569
 570         return chosen;
 571 }
 572
 573 static void
 574 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
 575                              uint64_t inst)
 576 {
 577         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 578         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 579
 580         if (!(inst & QPU_WS)) {
 581                 scoreboard->last_waddr_a = waddr_add;
 582                 scoreboard->last_waddr_b = waddr_mul;
 583         } else {
 584                 scoreboard->last_waddr_b = waddr_add;
 585                 scoreboard->last_waddr_a = waddr_mul;
 586         }
 587
 588         if ((waddr_add >= QPU_W_SFU_RECIP && waddr_add <= QPU_W_SFU_LOG) ||
 589             (waddr_mul >= QPU_W_SFU_RECIP && waddr_mul <= QPU_W_SFU_LOG)) {
 590                 scoreboard->last_sfu_write_tick = scoreboard->tick;
 591         }
 592 }
 593
 594 static void
 595 dump_state(struct simple_node *schedule_list)
 596 {
 597         struct simple_node *node;
 598
 599         uint32_t i = 0;
 600         foreach(node, schedule_list) {
 601                 struct schedule_node *n = (struct schedule_node *)node;
 602
 603                 fprintf(stderr, "%3d: ", i++);
 604                 vc4_qpu_disasm(&n->inst->inst, 1);
 605                 fprintf(stderr, "\n");
 606
 607                 for (int i = 0; i < n->child_count; i++) {
 608                         struct schedule_node *child = n->children[i].node;
 609                         if (!child)
 610                                 continue;
 611
 612                         fprintf(stderr, "   - ");
 613                         vc4_qpu_disasm(&child->inst->inst, 1);
 614                         fprintf(stderr, " (%d parents, %c)\n",
 615                                 child->parent_count,
 616                                 n->children[i].write_after_read ? 'w' : 'r');
 617                 }
 618         }
 619 }
 620
 621 /** Recursive computation of the delay member of a node. */
 622 static void
 623 compute_delay(struct schedule_node *n)
 624 {
 625         if (!n->child_count) {
 626                 n->delay = 1;
 627         } else {
 628                 for (int i = 0; i < n->child_count; i++) {
 629                         if (!n->children[i].node->delay)
 630                                 compute_delay(n->children[i].node);
 631                         n->delay = MAX2(n->delay,
 632                                         n->children[i].node->delay + n->latency);
 633                 }
 634         }
 635 }
 636
 637 static void
 638 mark_instruction_scheduled(struct simple_node *schedule_list,
 639                            struct schedule_node *node,
 640                            bool war_only)
 641 {
 642         if (!node)
 643                 return;
 644
 645         for (int i = node->child_count - 1; i >= 0; i--) {
 646                 struct schedule_node *child =
 647                         node->children[i].node;
 648
 649                 if (!child)
 650                         continue;
 651
 652                 if (war_only && !node->children[i].write_after_read)
 653                         continue;
 654
 655                 child->parent_count--;
 656                 if (child->parent_count == 0)
 657                         insert_at_head(schedule_list, &child->link);
 658
 659                 node->children[i].node = NULL;
 660         }
 661 }
 662
 663 static void
 664 schedule_instructions(struct vc4_compile *c, struct simple_node *schedule_list)
 665 {
 666         struct simple_node *node, *t;
 667         struct choose_scoreboard scoreboard;
 668
 669         /* We reorder the uniforms as we schedule instructions, so save the
 670          * old data off and replace it.
 671          */
 672         uint32_t *uniform_data = c->uniform_data;
 673         enum quniform_contents *uniform_contents = c->uniform_contents;
 674         c->uniform_contents = ralloc_array(c, enum quniform_contents,
 675                                            c->num_uniforms);
 676         c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
 677         c->uniform_array_size = c->num_uniforms;
 678         uint32_t next_uniform = 0;
 679
 680         memset(&scoreboard, 0, sizeof(scoreboard));
 681         scoreboard.last_waddr_a = ~0;
 682         scoreboard.last_waddr_b = ~0;
 683         scoreboard.last_sfu_write_tick = -10;
 684
 685         if (debug) {
 686                 fprintf(stderr, "initial deps:\n");
 687                 dump_state(schedule_list);
 688                 fprintf(stderr, "\n");
 689         }
 690
 691         /* Remove non-DAG heads from the list. */
 692         foreach_s(node, t, schedule_list) {
 693                 struct schedule_node *n = (struct schedule_node *)node;
 694
 695                 if (n->parent_count != 0)
 696                         remove_from_list(&n->link);
 697         }
 698
 699         while (!is_empty_list(schedule_list)) {
 700                 struct schedule_node *chosen =
 701                         choose_instruction_to_schedule(&scoreboard,
 702                                                        schedule_list,
 703                                                        NULL);
 704                 struct schedule_node *merge = NULL;
 705
 706                 /* If there are no valid instructions to schedule, drop a NOP
 707                  * in.
 708                  */
 709                 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
 710
 711                 if (debug) {
 712                         fprintf(stderr, "current list:\n");
 713                         dump_state(schedule_list);
 714                         fprintf(stderr, "chose: ");
 715                         vc4_qpu_disasm(&inst, 1);
 716                         fprintf(stderr, "\n");
 717                 }
 718
 719                 /* Schedule this instruction onto the QPU list. Also try to
 720                  * find an instruction to pair with it.
 721                  */
 722                 if (chosen) {
 723                         remove_from_list(&chosen->link);
 724                         mark_instruction_scheduled(schedule_list, chosen, true);
 725                         if (chosen->uniform != -1) {
 726                                 c->uniform_data[next_uniform] =
 727                                         uniform_data[chosen->uniform];
 728                                 c->uniform_contents[next_uniform] =
 729                                         uniform_contents[chosen->uniform];
 730                                 next_uniform++;
 731                         }
 732
 733                         merge = choose_instruction_to_schedule(&scoreboard,
 734                                                                schedule_list,
 735                                                                chosen);
 736                         if (merge) {
 737                                 remove_from_list(&merge->link);
 738                                 inst = qpu_merge_inst(inst, merge->inst->inst);
 739                                 assert(inst != 0);
 740                                 if (merge->uniform != -1) {
 741                                         c->uniform_data[next_uniform] =
 742                                                 uniform_data[merge->uniform];
 743                                         c->uniform_contents[next_uniform] =
 744                                                 uniform_contents[merge->uniform];
 745                                         next_uniform++;
 746                                 }
 747
 748                                 if (debug) {
 749                                         fprintf(stderr, "merging: ");
 750                                         vc4_qpu_disasm(&merge->inst->inst, 1);
 751                                         fprintf(stderr, "\n");
 752                                         fprintf(stderr, "resulting in: ");
 753                                         vc4_qpu_disasm(&inst, 1);
 754                                         fprintf(stderr, "\n");
 755                                 }
 756                         }
 757                 }
 758
 759                 if (debug) {
 760                         fprintf(stderr, "\n");
 761                 }
 762
 763                 qpu_serialize_one_inst(c, inst);
 764
 765                 update_scoreboard_for_chosen(&scoreboard, inst);
 766
 767                 /* Now that we've scheduled a new instruction, some of its
 768                  * children can be promoted to the list of instructions ready to
 769                  * be scheduled.  Update the children's unblocked time for this
 770                  * DAG edge as we do so.
 771                  */
 772                 mark_instruction_scheduled(schedule_list, chosen, false);
 773                 mark_instruction_scheduled(schedule_list, merge, false);
 774
 775                 scoreboard.tick++;
 776         }
 777
 778         assert(next_uniform == c->num_uniforms);
 779 }
 780
 781 static uint32_t waddr_latency(uint32_t waddr)
 782 {
 783         if (waddr < 32)
 784                 return 2;
 785
 786         /* Some huge number, really. */
 787         if (waddr >= QPU_W_TMU0_S && waddr <= QPU_W_TMU1_B)
 788                 return 10;
 789
 790         switch(waddr) {
 791         case QPU_W_SFU_RECIP:
 792         case QPU_W_SFU_RECIPSQRT:
 793         case QPU_W_SFU_EXP:
 794         case QPU_W_SFU_LOG:
 795                 return 3;
 796         default:
 797                 return 1;
 798         }
 799 }
 800
 801 static uint32_t
 802 instruction_latency(uint64_t inst)
 803 {
 804         return MAX2(waddr_latency(QPU_GET_FIELD(inst, QPU_WADDR_ADD)),
 805                     waddr_latency(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
 806 }
 807
 808 void
 809 qpu_schedule_instructions(struct vc4_compile *c)
 810 {
 811         void *mem_ctx = ralloc_context(NULL);
 812         struct simple_node schedule_list;
 813         struct simple_node *node;
 814
 815         make_empty_list(&schedule_list);
 816
 817         if (debug) {
 818                 fprintf(stderr, "Pre-schedule instructions\n");
 819                 foreach(node, &c->qpu_inst_list) {
 820                         struct queued_qpu_inst *q =
 821                                 (struct queued_qpu_inst *)node;
 822                         vc4_qpu_disasm(&q->inst, 1);
 823                         fprintf(stderr, "\n");
 824                 }
 825                 fprintf(stderr, "\n");
 826         }
 827
 828         /* Wrap each instruction in a scheduler structure. */
 829         uint32_t next_uniform = 0;
 830         while (!is_empty_list(&c->qpu_inst_list)) {
 831                 struct queued_qpu_inst *inst =
 832                         (struct queued_qpu_inst *)c->qpu_inst_list.next;
 833                 struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
 834
 835                 n->inst = inst;
 836                 n->latency = instruction_latency(inst->inst);
 837
 838                 if (reads_uniform(inst->inst)) {
 839                         n->uniform = next_uniform++;
 840                 } else {
 841                         n->uniform = -1;
 842                 }
 843                 remove_from_list(&inst->link);
 844                 insert_at_tail(&schedule_list, &n->link);
 845         }
 846         assert(next_uniform == c->num_uniforms);
 847
 848         calculate_forward_deps(c, &schedule_list);
 849         calculate_reverse_deps(c, &schedule_list);
 850
 851         foreach(node, &schedule_list) {
 852                 struct schedule_node *n = (struct schedule_node *)node;
 853                 compute_delay(n);
 854         }
 855
 856         schedule_instructions(c, &schedule_list);
 857
 858         if (debug) {
 859                 fprintf(stderr, "Post-schedule instructions\n");
 860                 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
 861                 fprintf(stderr, "\n");
 862         }
 863
 864         ralloc_free(mem_ctx);
 865 }