src/gallium/drivers/vc4/vc4_qpu_schedule.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * @file vc4_qpu_schedule.c
  27  *
  28  * The basic model of the list scheduler is to take a basic block, compute a
  29  * DAG of the dependencies, and make a list of the DAG heads.  Heuristically
  30  * pick a DAG head, then put all the children that are now DAG heads into the
  31  * list of things to schedule.
  32  *
  33  * The goal of scheduling here is to pack pairs of operations together in a
  34  * single QPU instruction.
  35  */
  36
  37 #include "vc4_qir.h"
  38 #include "vc4_qpu.h"
  39 #include "util/ralloc.h"
  40
  41 static bool debug;
  42
  43 struct schedule_node_child;
  44
  45 struct schedule_node {
  46         struct list_head link;
  47         struct queued_qpu_inst *inst;
  48         struct schedule_node_child *children;
  49         uint32_t child_count;
  50         uint32_t child_array_size;
  51         uint32_t parent_count;
  52
  53         /* Longest cycles + instruction_latency() of any parent of this node. */
  54         uint32_t unblocked_time;
  55
  56         /**
  57          * Minimum number of cycles from scheduling this instruction until the
  58          * end of the program, based on the slowest dependency chain through
  59          * the children.
  60          */
  61         uint32_t delay;
  62
  63         /**
  64          * cycles between this instruction being scheduled and when its result
  65          * can be consumed.
  66          */
  67         uint32_t latency;
  68
  69         /**
  70          * Which uniform from uniform_data[] this instruction read, or -1 if
  71          * not reading a uniform.
  72          */
  73         int uniform;
  74 };
  75
  76 struct schedule_node_child {
  77         struct schedule_node *node;
  78         bool write_after_read;
  79 };
  80
  81 /* When walking the instructions in reverse, we need to swap before/after in
  82  * add_dep().
  83  */
  84 enum direction { F, R };
  85
  86 struct schedule_state {
  87         struct schedule_node *last_r[6];
  88         struct schedule_node *last_ra[32];
  89         struct schedule_node *last_rb[32];
  90         struct schedule_node *last_sf;
  91         struct schedule_node *last_vpm_read;
  92         struct schedule_node *last_tmu_write;
  93         struct schedule_node *last_tlb;
  94         struct schedule_node *last_vpm;
  95         struct schedule_node *last_uniforms_reset;
  96         enum direction dir;
  97         /* Estimated cycle when the current instruction would start. */
  98         uint32_t time;
  99 };
 100
 101 static void
 102 add_dep(struct schedule_state *state,
 103         struct schedule_node *before,
 104         struct schedule_node *after,
 105         bool write)
 106 {
 107         bool write_after_read = !write && state->dir == R;
 108
 109         if (!before || !after)
 110                 return;
 111
 112         assert(before != after);
 113
 114         if (state->dir == R) {
 115                 struct schedule_node *t = before;
 116                 before = after;
 117                 after = t;
 118         }
 119
 120         for (int i = 0; i < before->child_count; i++) {
 121                 if (before->children[i].node == after &&
 122                     (before->children[i].write_after_read == write_after_read)) {
 123                         return;
 124                 }
 125         }
 126
 127         if (before->child_array_size <= before->child_count) {
 128                 before->child_array_size = MAX2(before->child_array_size * 2, 16);
 129                 before->children = reralloc(before, before->children,
 130                                             struct schedule_node_child,
 131                                             before->child_array_size);
 132         }
 133
 134         before->children[before->child_count].node = after;
 135         before->children[before->child_count].write_after_read =
 136                 write_after_read;
 137         before->child_count++;
 138         after->parent_count++;
 139 }
 140
 141 static void
 142 add_read_dep(struct schedule_state *state,
 143               struct schedule_node *before,
 144               struct schedule_node *after)
 145 {
 146         add_dep(state, before, after, false);
 147 }
 148
 149 static void
 150 add_write_dep(struct schedule_state *state,
 151               struct schedule_node **before,
 152               struct schedule_node *after)
 153 {
 154         add_dep(state, *before, after, true);
 155         *before = after;
 156 }
 157
 158 static bool
 159 qpu_writes_r4(uint64_t inst)
 160 {
 161         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 162
 163         switch(sig) {
 164         case QPU_SIG_COLOR_LOAD:
 165         case QPU_SIG_LOAD_TMU0:
 166         case QPU_SIG_LOAD_TMU1:
 167         case QPU_SIG_ALPHA_MASK_LOAD:
 168                 return true;
 169         default:
 170                 return false;
 171         }
 172 }
 173
 174 static void
 175 process_raddr_deps(struct schedule_state *state, struct schedule_node *n,
 176                    uint32_t raddr, bool is_a)
 177 {
 178         switch (raddr) {
 179         case QPU_R_VARY:
 180                 add_write_dep(state, &state->last_r[5], n);
 181                 break;
 182
 183         case QPU_R_VPM:
 184                 add_write_dep(state, &state->last_vpm_read, n);
 185                 break;
 186
 187         case QPU_R_UNIF:
 188                 add_read_dep(state, state->last_uniforms_reset, n);
 189                 break;
 190
 191         case QPU_R_NOP:
 192         case QPU_R_ELEM_QPU:
 193         case QPU_R_XY_PIXEL_COORD:
 194         case QPU_R_MS_REV_FLAGS:
 195                 break;
 196
 197         default:
 198                 if (raddr < 32) {
 199                         if (is_a)
 200                                 add_read_dep(state, state->last_ra[raddr], n);
 201                         else
 202                                 add_read_dep(state, state->last_rb[raddr], n);
 203                 } else {
 204                         fprintf(stderr, "unknown raddr %d\n", raddr);
 205                         abort();
 206                 }
 207                 break;
 208         }
 209 }
 210
 211 static bool
 212 is_tmu_write(uint32_t waddr)
 213 {
 214         switch (waddr) {
 215         case QPU_W_TMU0_S:
 216         case QPU_W_TMU0_T:
 217         case QPU_W_TMU0_R:
 218         case QPU_W_TMU0_B:
 219         case QPU_W_TMU1_S:
 220         case QPU_W_TMU1_T:
 221         case QPU_W_TMU1_R:
 222         case QPU_W_TMU1_B:
 223                 return true;
 224         default:
 225                 return false;
 226         }
 227 }
 228
 229 static bool
 230 reads_uniform(uint64_t inst)
 231 {
 232         if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
 233                 return false;
 234
 235         return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
 236                 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
 237                  QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
 238                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
 239                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
 240 }
 241
 242 static void
 243 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
 244                  uint32_t mux)
 245 {
 246         if (mux != QPU_MUX_A && mux != QPU_MUX_B)
 247                 add_read_dep(state, state->last_r[mux], n);
 248 }
 249
 250
 251 static void
 252 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
 253                    uint32_t waddr, bool is_add)
 254 {
 255         uint64_t inst = n->inst->inst;
 256         bool is_a = is_add ^ ((inst & QPU_WS) != 0);
 257
 258         if (waddr < 32) {
 259                 if (is_a) {
 260                         add_write_dep(state, &state->last_ra[waddr], n);
 261                 } else {
 262                         add_write_dep(state, &state->last_rb[waddr], n);
 263                 }
 264         } else if (is_tmu_write(waddr)) {
 265                 add_write_dep(state, &state->last_tmu_write, n);
 266                 add_read_dep(state, state->last_uniforms_reset, n);
 267         } else if (qpu_waddr_is_tlb(waddr) ||
 268                    waddr == QPU_W_MS_FLAGS) {
 269                 add_write_dep(state, &state->last_tlb, n);
 270         } else {
 271                 switch (waddr) {
 272                 case QPU_W_ACC0:
 273                 case QPU_W_ACC1:
 274                 case QPU_W_ACC2:
 275                 case QPU_W_ACC3:
 276                 case QPU_W_ACC5:
 277                         add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
 278                                       n);
 279                         break;
 280
 281                 case QPU_W_VPM:
 282                         add_write_dep(state, &state->last_vpm, n);
 283                         break;
 284
 285                 case QPU_W_VPMVCD_SETUP:
 286                         if (is_a)
 287                                 add_write_dep(state, &state->last_vpm_read, n);
 288                         else
 289                                 add_write_dep(state, &state->last_vpm, n);
 290                         break;
 291
 292                 case QPU_W_SFU_RECIP:
 293                 case QPU_W_SFU_RECIPSQRT:
 294                 case QPU_W_SFU_EXP:
 295                 case QPU_W_SFU_LOG:
 296                         add_write_dep(state, &state->last_r[4], n);
 297                         break;
 298
 299                 case QPU_W_TLB_STENCIL_SETUP:
 300                         /* This isn't a TLB operation that does things like
 301                          * implicitly lock the scoreboard, but it does have to
 302                          * appear before TLB_Z, and each of the TLB_STENCILs
 303                          * have to schedule in the same order relative to each
 304                          * other.
 305                          */
 306                         add_write_dep(state, &state->last_tlb, n);
 307                         break;
 308
 309                 case QPU_W_MS_FLAGS:
 310                         add_write_dep(state, &state->last_tlb, n);
 311                         break;
 312
 313                 case QPU_W_UNIFORMS_ADDRESS:
 314                         add_write_dep(state, &state->last_uniforms_reset, n);
 315                         break;
 316
 317                 case QPU_W_NOP:
 318                         break;
 319
 320                 default:
 321                         fprintf(stderr, "Unknown waddr %d\n", waddr);
 322                         abort();
 323                 }
 324         }
 325 }
 326
 327 static void
 328 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
 329                   uint32_t cond)
 330 {
 331         switch (cond) {
 332         case QPU_COND_NEVER:
 333         case QPU_COND_ALWAYS:
 334                 break;
 335         default:
 336                 add_read_dep(state, state->last_sf, n);
 337                 break;
 338         }
 339 }
 340
 341 /**
 342  * Common code for dependencies that need to be tracked both forward and
 343  * backward.
 344  *
 345  * This is for things like "all reads of r4 have to happen between the r4
 346  * writes that surround them".
 347  */
 348 static void
 349 calculate_deps(struct schedule_state *state, struct schedule_node *n)
 350 {
 351         uint64_t inst = n->inst->inst;
 352         uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
 353         uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
 354         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 355         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 356         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 357         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 358         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
 359         uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 360         uint32_t mul_a = QPU_GET_FIELD(inst, QPU_MUL_A);
 361         uint32_t mul_b = QPU_GET_FIELD(inst, QPU_MUL_B);
 362         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 363
 364         if (sig != QPU_SIG_LOAD_IMM) {
 365                 process_raddr_deps(state, n, raddr_a, true);
 366                 if (sig != QPU_SIG_SMALL_IMM &&
 367                     sig != QPU_SIG_BRANCH)
 368                         process_raddr_deps(state, n, raddr_b, false);
 369         }
 370
 371         if (add_op != QPU_A_NOP) {
 372                 process_mux_deps(state, n, add_a);
 373                 process_mux_deps(state, n, add_b);
 374         }
 375         if (mul_op != QPU_M_NOP) {
 376                 process_mux_deps(state, n, mul_a);
 377                 process_mux_deps(state, n, mul_b);
 378         }
 379
 380         process_waddr_deps(state, n, waddr_add, true);
 381         process_waddr_deps(state, n, waddr_mul, false);
 382         if (qpu_writes_r4(inst))
 383                 add_write_dep(state, &state->last_r[4], n);
 384
 385         switch (sig) {
 386         case QPU_SIG_SW_BREAKPOINT:
 387         case QPU_SIG_NONE:
 388         case QPU_SIG_THREAD_SWITCH:
 389         case QPU_SIG_LAST_THREAD_SWITCH:
 390         case QPU_SIG_SMALL_IMM:
 391         case QPU_SIG_LOAD_IMM:
 392                 break;
 393
 394         case QPU_SIG_LOAD_TMU0:
 395         case QPU_SIG_LOAD_TMU1:
 396                 /* TMU loads are coming from a FIFO, so ordering is important.
 397                  */
 398                 add_write_dep(state, &state->last_tmu_write, n);
 399                 break;
 400
 401         case QPU_SIG_COLOR_LOAD:
 402                 add_read_dep(state, state->last_tlb, n);
 403                 break;
 404
 405         case QPU_SIG_BRANCH:
 406                 add_read_dep(state, state->last_sf, n);
 407                 break;
 408
 409         case QPU_SIG_PROG_END:
 410         case QPU_SIG_WAIT_FOR_SCOREBOARD:
 411         case QPU_SIG_SCOREBOARD_UNLOCK:
 412         case QPU_SIG_COVERAGE_LOAD:
 413         case QPU_SIG_COLOR_LOAD_END:
 414         case QPU_SIG_ALPHA_MASK_LOAD:
 415                 fprintf(stderr, "Unhandled signal bits %d\n", sig);
 416                 abort();
 417         }
 418
 419         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
 420         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_MUL));
 421         if ((inst & QPU_SF) && sig != QPU_SIG_BRANCH)
 422                 add_write_dep(state, &state->last_sf, n);
 423 }
 424
 425 static void
 426 calculate_forward_deps(struct vc4_compile *c, struct list_head *schedule_list)
 427 {
 428         struct schedule_state state;
 429
 430         memset(&state, 0, sizeof(state));
 431         state.dir = F;
 432
 433         list_for_each_entry(struct schedule_node, node, schedule_list, link)
 434                 calculate_deps(&state, node);
 435 }
 436
 437 static void
 438 calculate_reverse_deps(struct vc4_compile *c, struct list_head *schedule_list)
 439 {
 440         struct list_head *node;
 441         struct schedule_state state;
 442
 443         memset(&state, 0, sizeof(state));
 444         state.dir = R;
 445
 446         for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
 447                 calculate_deps(&state, (struct schedule_node *)node);
 448         }
 449 }
 450
 451 struct choose_scoreboard {
 452         int tick;
 453         int last_sfu_write_tick;
 454         int last_uniforms_reset_tick;
 455         uint32_t last_waddr_a, last_waddr_b;
 456 };
 457
 458 static bool
 459 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst)
 460 {
 461         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 462         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 463         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 464         uint32_t src_muxes[] = {
 465                 QPU_GET_FIELD(inst, QPU_ADD_A),
 466                 QPU_GET_FIELD(inst, QPU_ADD_B),
 467                 QPU_GET_FIELD(inst, QPU_MUL_A),
 468                 QPU_GET_FIELD(inst, QPU_MUL_B),
 469         };
 470         for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
 471                 if ((src_muxes[i] == QPU_MUX_A &&
 472                      raddr_a < 32 &&
 473                      scoreboard->last_waddr_a == raddr_a) ||
 474                     (src_muxes[i] == QPU_MUX_B &&
 475                      sig != QPU_SIG_SMALL_IMM &&
 476                      raddr_b < 32 &&
 477                      scoreboard->last_waddr_b == raddr_b)) {
 478                         return true;
 479                 }
 480
 481                 if (src_muxes[i] == QPU_MUX_R4) {
 482                         if (scoreboard->tick -
 483                             scoreboard->last_sfu_write_tick <= 2) {
 484                                 return true;
 485                         }
 486                 }
 487         }
 488
 489         if (sig == QPU_SIG_SMALL_IMM &&
 490             QPU_GET_FIELD(inst, QPU_SMALL_IMM) >= QPU_SMALL_IMM_MUL_ROT) {
 491                 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A);
 492                 uint32_t mux_b = QPU_GET_FIELD(inst, QPU_MUL_B);
 493
 494                 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
 495                     scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 ||
 496                     scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
 497                     scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) {
 498                         return true;
 499                 }
 500         }
 501
 502         if (reads_uniform(inst) &&
 503             scoreboard->tick - scoreboard->last_uniforms_reset_tick <= 2) {
 504                 return true;
 505         }
 506
 507         return false;
 508 }
 509
 510 static bool
 511 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst)
 512 {
 513         return (scoreboard->tick < 2 && qpu_inst_is_tlb(inst));
 514 }
 515
 516 static int
 517 get_instruction_priority(uint64_t inst)
 518 {
 519         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 520         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 521         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 522         uint32_t baseline_score;
 523         uint32_t next_score = 0;
 524
 525         /* Schedule TLB operations as late as possible, to get more
 526          * parallelism between shaders.
 527          */
 528         if (qpu_inst_is_tlb(inst))
 529                 return next_score;
 530         next_score++;
 531
 532         /* Schedule texture read results collection late to hide latency. */
 533         if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
 534                 return next_score;
 535         next_score++;
 536
 537         /* Default score for things that aren't otherwise special. */
 538         baseline_score = next_score;
 539         next_score++;
 540
 541         /* Schedule texture read setup early to hide their latency better. */
 542         if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
 543                 return next_score;
 544         next_score++;
 545
 546         return baseline_score;
 547 }
 548
 549 static struct schedule_node *
 550 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard,
 551                                struct list_head *schedule_list,
 552                                struct schedule_node *prev_inst)
 553 {
 554         struct schedule_node *chosen = NULL;
 555         int chosen_prio = 0;
 556
 557         list_for_each_entry(struct schedule_node, n, schedule_list, link) {
 558                 uint64_t inst = n->inst->inst;
 559
 560                 /* Don't choose the branch instruction until it's the last one
 561                  * left.  XXX: We could potentially choose it before it's the
 562                  * last one, if the remaining instructions fit in the delay
 563                  * slots.
 564                  */
 565                 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH &&
 566                     !list_is_singular(schedule_list)) {
 567                         continue;
 568                 }
 569
 570                 /* "An instruction must not read from a location in physical
 571                  *  regfile A or B that was written to by the previous
 572                  *  instruction."
 573                  */
 574                 if (reads_too_soon_after_write(scoreboard, inst))
 575                         continue;
 576
 577                 /* "A scoreboard wait must not occur in the first two
 578                  *  instructions of a fragment shader. This is either the
 579                  *  explicit Wait for Scoreboard signal or an implicit wait
 580                  *  with the first tile-buffer read or write instruction."
 581                  */
 582                 if (pixel_scoreboard_too_soon(scoreboard, inst))
 583                         continue;
 584
 585                 /* If we're trying to pair with another instruction, check
 586                  * that they're compatible.
 587                  */
 588                 if (prev_inst) {
 589                         if (prev_inst->uniform != -1 && n->uniform != -1)
 590                                 continue;
 591
 592                         inst = qpu_merge_inst(prev_inst->inst->inst, inst);
 593                         if (!inst)
 594                                 continue;
 595                 }
 596
 597                 int prio = get_instruction_priority(inst);
 598
 599                 /* Found a valid instruction.  If nothing better comes along,
 600                  * this one works.
 601                  */
 602                 if (!chosen) {
 603                         chosen = n;
 604                         chosen_prio = prio;
 605                         continue;
 606                 }
 607
 608                 if (prio > chosen_prio) {
 609                         chosen = n;
 610                         chosen_prio = prio;
 611                 } else if (prio < chosen_prio) {
 612                         continue;
 613                 }
 614
 615                 if (n->delay > chosen->delay) {
 616                         chosen = n;
 617                         chosen_prio = prio;
 618                 } else if (n->delay < chosen->delay) {
 619                         continue;
 620                 }
 621         }
 622
 623         return chosen;
 624 }
 625
 626 static void
 627 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
 628                              uint64_t inst)
 629 {
 630         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 631         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 632
 633         if (!(inst & QPU_WS)) {
 634                 scoreboard->last_waddr_a = waddr_add;
 635                 scoreboard->last_waddr_b = waddr_mul;
 636         } else {
 637                 scoreboard->last_waddr_b = waddr_add;
 638                 scoreboard->last_waddr_a = waddr_mul;
 639         }
 640
 641         if ((waddr_add >= QPU_W_SFU_RECIP && waddr_add <= QPU_W_SFU_LOG) ||
 642             (waddr_mul >= QPU_W_SFU_RECIP && waddr_mul <= QPU_W_SFU_LOG)) {
 643                 scoreboard->last_sfu_write_tick = scoreboard->tick;
 644         }
 645
 646         if (waddr_add == QPU_W_UNIFORMS_ADDRESS ||
 647             waddr_mul == QPU_W_UNIFORMS_ADDRESS) {
 648                 scoreboard->last_uniforms_reset_tick = scoreboard->tick;
 649         }
 650 }
 651
 652 static void
 653 dump_state(struct list_head *schedule_list)
 654 {
 655         list_for_each_entry(struct schedule_node, n, schedule_list, link) {
 656                 fprintf(stderr, "         t=%4d: ", n->unblocked_time);
 657                 vc4_qpu_disasm(&n->inst->inst, 1);
 658                 fprintf(stderr, "\n");
 659
 660                 for (int i = 0; i < n->child_count; i++) {
 661                         struct schedule_node *child = n->children[i].node;
 662                         if (!child)
 663                                 continue;
 664
 665                         fprintf(stderr, "                 - ");
 666                         vc4_qpu_disasm(&child->inst->inst, 1);
 667                         fprintf(stderr, " (%d parents, %c)\n",
 668                                 child->parent_count,
 669                                 n->children[i].write_after_read ? 'w' : 'r');
 670                 }
 671         }
 672 }
 673
 674 static uint32_t waddr_latency(uint32_t waddr, uint64_t after)
 675 {
 676         if (waddr < 32)
 677                 return 2;
 678
 679         /* Apply some huge latency between texture fetch requests and getting
 680          * their results back.
 681          */
 682         if (waddr == QPU_W_TMU0_S) {
 683                 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU0)
 684                         return 100;
 685         }
 686         if (waddr == QPU_W_TMU1_S) {
 687                 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU1)
 688                         return 100;
 689         }
 690
 691         switch(waddr) {
 692         case QPU_W_SFU_RECIP:
 693         case QPU_W_SFU_RECIPSQRT:
 694         case QPU_W_SFU_EXP:
 695         case QPU_W_SFU_LOG:
 696                 return 3;
 697         default:
 698                 return 1;
 699         }
 700 }
 701
 702 static uint32_t
 703 instruction_latency(struct schedule_node *before, struct schedule_node *after)
 704 {
 705         uint64_t before_inst = before->inst->inst;
 706         uint64_t after_inst = after->inst->inst;
 707
 708         return MAX2(waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_ADD),
 709                                   after_inst),
 710                     waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_MUL),
 711                                   after_inst));
 712 }
 713
 714 /** Recursive computation of the delay member of a node. */
 715 static void
 716 compute_delay(struct schedule_node *n)
 717 {
 718         if (!n->child_count) {
 719                 n->delay = 1;
 720         } else {
 721                 for (int i = 0; i < n->child_count; i++) {
 722                         if (!n->children[i].node->delay)
 723                                 compute_delay(n->children[i].node);
 724                         n->delay = MAX2(n->delay,
 725                                         n->children[i].node->delay +
 726                                         instruction_latency(n, n->children[i].node));
 727                 }
 728         }
 729 }
 730
 731 static void
 732 mark_instruction_scheduled(struct list_head *schedule_list,
 733                            uint32_t time,
 734                            struct schedule_node *node,
 735                            bool war_only)
 736 {
 737         if (!node)
 738                 return;
 739
 740         for (int i = node->child_count - 1; i >= 0; i--) {
 741                 struct schedule_node *child =
 742                         node->children[i].node;
 743
 744                 if (!child)
 745                         continue;
 746
 747                 if (war_only && !node->children[i].write_after_read)
 748                         continue;
 749
 750                 /* If the requirement is only that the node not appear before
 751                  * the last read of its destination, then it can be scheduled
 752                  * immediately after (or paired with!) the thing reading the
 753                  * destination.
 754                  */
 755                 uint32_t latency = 0;
 756                 if (!war_only) {
 757                         latency = instruction_latency(node,
 758                                                       node->children[i].node);
 759                 }
 760
 761                 child->unblocked_time = MAX2(child->unblocked_time,
 762                                              time + latency);
 763                 child->parent_count--;
 764                 if (child->parent_count == 0)
 765                         list_add(&child->link, schedule_list);
 766
 767                 node->children[i].node = NULL;
 768         }
 769 }
 770
 771 static uint32_t
 772 schedule_instructions(struct vc4_compile *c,
 773                       struct choose_scoreboard *scoreboard,
 774                       struct qblock *block,
 775                       struct list_head *schedule_list,
 776                       enum quniform_contents *orig_uniform_contents,
 777                       uint32_t *orig_uniform_data,
 778                       uint32_t *next_uniform)
 779 {
 780         uint32_t time = 0;
 781
 782         if (debug) {
 783                 fprintf(stderr, "initial deps:\n");
 784                 dump_state(schedule_list);
 785                 fprintf(stderr, "\n");
 786         }
 787
 788         /* Remove non-DAG heads from the list. */
 789         list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
 790                 if (n->parent_count != 0)
 791                         list_del(&n->link);
 792         }
 793
 794         while (!list_empty(schedule_list)) {
 795                 struct schedule_node *chosen =
 796                         choose_instruction_to_schedule(scoreboard,
 797                                                        schedule_list,
 798                                                        NULL);
 799                 struct schedule_node *merge = NULL;
 800
 801                 /* If there are no valid instructions to schedule, drop a NOP
 802                  * in.
 803                  */
 804                 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
 805
 806                 if (debug) {
 807                         fprintf(stderr, "t=%4d: current list:\n",
 808                                 time);
 809                         dump_state(schedule_list);
 810                         fprintf(stderr, "t=%4d: chose: ", time);
 811                         vc4_qpu_disasm(&inst, 1);
 812                         fprintf(stderr, "\n");
 813                 }
 814
 815                 /* Schedule this instruction onto the QPU list. Also try to
 816                  * find an instruction to pair with it.
 817                  */
 818                 if (chosen) {
 819                         time = MAX2(chosen->unblocked_time, time);
 820                         list_del(&chosen->link);
 821                         mark_instruction_scheduled(schedule_list, time,
 822                                                    chosen, true);
 823                         if (chosen->uniform != -1) {
 824                                 c->uniform_data[*next_uniform] =
 825                                         orig_uniform_data[chosen->uniform];
 826                                 c->uniform_contents[*next_uniform] =
 827                                         orig_uniform_contents[chosen->uniform];
 828                                 (*next_uniform)++;
 829                         }
 830
 831                         merge = choose_instruction_to_schedule(scoreboard,
 832                                                                schedule_list,
 833                                                                chosen);
 834                         if (merge) {
 835                                 time = MAX2(merge->unblocked_time, time);
 836                                 list_del(&merge->link);
 837                                 inst = qpu_merge_inst(inst, merge->inst->inst);
 838                                 assert(inst != 0);
 839                                 if (merge->uniform != -1) {
 840                                         c->uniform_data[*next_uniform] =
 841                                                 orig_uniform_data[merge->uniform];
 842                                         c->uniform_contents[*next_uniform] =
 843                                                 orig_uniform_contents[merge->uniform];
 844                                         (*next_uniform)++;
 845                                 }
 846
 847                                 if (debug) {
 848                                         fprintf(stderr, "t=%4d: merging: ",
 849                                                 time);
 850                                         vc4_qpu_disasm(&merge->inst->inst, 1);
 851                                         fprintf(stderr, "\n");
 852                                         fprintf(stderr, "            resulting in: ");
 853                                         vc4_qpu_disasm(&inst, 1);
 854                                         fprintf(stderr, "\n");
 855                                 }
 856                         }
 857                 }
 858
 859                 if (debug) {
 860                         fprintf(stderr, "\n");
 861                 }
 862
 863                 qpu_serialize_one_inst(c, inst);
 864
 865                 update_scoreboard_for_chosen(scoreboard, inst);
 866
 867                 /* Now that we've scheduled a new instruction, some of its
 868                  * children can be promoted to the list of instructions ready to
 869                  * be scheduled.  Update the children's unblocked time for this
 870                  * DAG edge as we do so.
 871                  */
 872                 mark_instruction_scheduled(schedule_list, time, chosen, false);
 873                 mark_instruction_scheduled(schedule_list, time, merge, false);
 874
 875                 scoreboard->tick++;
 876                 time++;
 877
 878                 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH) {
 879                         block->branch_qpu_ip = c->qpu_inst_count - 1;
 880                         /* Fill the delay slots.
 881                          *
 882                          * We should fill these with actual instructions,
 883                          * instead, but that will probably need to be done
 884                          * after this, once we know what the leading
 885                          * instructions of the successors are (so we can
 886                          * handle A/B register file write latency)
 887                         */
 888                         inst = qpu_NOP();
 889                         update_scoreboard_for_chosen(scoreboard, inst);
 890                         qpu_serialize_one_inst(c, inst);
 891                         qpu_serialize_one_inst(c, inst);
 892                         qpu_serialize_one_inst(c, inst);
 893                 }
 894         }
 895
 896         return time;
 897 }
 898
 899 static uint32_t
 900 qpu_schedule_instructions_block(struct vc4_compile *c,
 901                                 struct choose_scoreboard *scoreboard,
 902                                 struct qblock *block,
 903                                 enum quniform_contents *orig_uniform_contents,
 904                                 uint32_t *orig_uniform_data,
 905                                 uint32_t *next_uniform)
 906 {
 907         void *mem_ctx = ralloc_context(NULL);
 908         struct list_head schedule_list;
 909
 910         list_inithead(&schedule_list);
 911
 912         /* Wrap each instruction in a scheduler structure. */
 913         uint32_t next_sched_uniform = *next_uniform;
 914         while (!list_empty(&block->qpu_inst_list)) {
 915                 struct queued_qpu_inst *inst =
 916                         (struct queued_qpu_inst *)block->qpu_inst_list.next;
 917                 struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
 918
 919                 n->inst = inst;
 920
 921                 if (reads_uniform(inst->inst)) {
 922                         n->uniform = next_sched_uniform++;
 923                 } else {
 924                         n->uniform = -1;
 925                 }
 926                 list_del(&inst->link);
 927                 list_addtail(&n->link, &schedule_list);
 928         }
 929
 930         calculate_forward_deps(c, &schedule_list);
 931         calculate_reverse_deps(c, &schedule_list);
 932
 933         list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
 934                 compute_delay(n);
 935         }
 936
 937         uint32_t cycles = schedule_instructions(c, scoreboard, block,
 938                                                 &schedule_list,
 939                                                 orig_uniform_contents,
 940                                                 orig_uniform_data,
 941                                                 next_uniform);
 942
 943         ralloc_free(mem_ctx);
 944
 945         return cycles;
 946 }
 947
 948 static void
 949 qpu_set_branch_targets(struct vc4_compile *c)
 950 {
 951         qir_for_each_block(block, c) {
 952                 /* The end block of the program has no branch. */
 953                 if (!block->successors[0])
 954                         continue;
 955
 956                 /* If there was no branch instruction, then the successor
 957                  * block must follow immediately after this one.
 958                  */
 959                 if (block->branch_qpu_ip == ~0) {
 960                         assert(block->end_qpu_ip + 1 ==
 961                                block->successors[0]->start_qpu_ip);
 962                         continue;
 963                 }
 964
 965                 /* Set the branch target for the block that doesn't follow
 966                  * immediately after ours.
 967                  */
 968                 uint64_t *branch_inst = &c->qpu_insts[block->branch_qpu_ip];
 969                 assert(QPU_GET_FIELD(*branch_inst, QPU_SIG) == QPU_SIG_BRANCH);
 970                 assert(QPU_GET_FIELD(*branch_inst, QPU_BRANCH_TARGET) == 0);
 971
 972                 uint32_t branch_target =
 973                         (block->successors[0]->start_qpu_ip -
 974                          (block->branch_qpu_ip + 4)) * sizeof(uint64_t);
 975                 *branch_inst = (*branch_inst |
 976                                 QPU_SET_FIELD(branch_target, QPU_BRANCH_TARGET));
 977
 978                 /* Make sure that the if-we-don't-jump successor was scheduled
 979                  * just after the delay slots.
 980                  */
 981                 if (block->successors[1]) {
 982                         assert(block->successors[1]->start_qpu_ip ==
 983                                block->branch_qpu_ip + 4);
 984                 }
 985         }
 986 }
 987
 988 uint32_t
 989 qpu_schedule_instructions(struct vc4_compile *c)
 990 {
 991         /* We reorder the uniforms as we schedule instructions, so save the
 992          * old data off and replace it.
 993          */
 994         uint32_t *uniform_data = c->uniform_data;
 995         enum quniform_contents *uniform_contents = c->uniform_contents;
 996         c->uniform_contents = ralloc_array(c, enum quniform_contents,
 997                                            c->num_uniforms);
 998         c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
 999         c->uniform_array_size = c->num_uniforms;
1000         uint32_t next_uniform = 0;
1001
1002         struct choose_scoreboard scoreboard;
1003         memset(&scoreboard, 0, sizeof(scoreboard));
1004         scoreboard.last_waddr_a = ~0;
1005         scoreboard.last_waddr_b = ~0;
1006         scoreboard.last_sfu_write_tick = -10;
1007         scoreboard.last_uniforms_reset_tick = -10;
1008
1009         if (debug) {
1010                 fprintf(stderr, "Pre-schedule instructions\n");
1011                 qir_for_each_block(block, c) {
1012                         fprintf(stderr, "BLOCK %d\n", block->index);
1013                         list_for_each_entry(struct queued_qpu_inst, q,
1014                                             &block->qpu_inst_list, link) {
1015                                 vc4_qpu_disasm(&q->inst, 1);
1016                                 fprintf(stderr, "\n");
1017                         }
1018                 }
1019                 fprintf(stderr, "\n");
1020         }
1021
1022         uint32_t cycles = 0;
1023         qir_for_each_block(block, c) {
1024                 block->start_qpu_ip = c->qpu_inst_count;
1025                 block->branch_qpu_ip = ~0;
1026
1027                 cycles += qpu_schedule_instructions_block(c,
1028                                                           &scoreboard,
1029                                                           block,
1030                                                           uniform_contents,
1031                                                           uniform_data,
1032                                                           &next_uniform);
1033
1034                 block->end_qpu_ip = c->qpu_inst_count - 1;
1035         }
1036
1037         qpu_set_branch_targets(c);
1038
1039         assert(next_uniform == c->num_uniforms);
1040
1041         if (debug) {
1042                 fprintf(stderr, "Post-schedule instructions\n");
1043                 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
1044                 fprintf(stderr, "\n");
1045         }
1046
1047         return cycles;
1048 }