src/gallium/drivers/vc4/vc4_qpu_schedule.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  * Copyright © 2014 Broadcom
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 /**
  26  * @file vc4_qpu_schedule.c
  27  *
  28  * The basic model of the list scheduler is to take a basic block, compute a
  29  * DAG of the dependencies, and make a list of the DAG heads.  Heuristically
  30  * pick a DAG head, then put all the children that are now DAG heads into the
  31  * list of things to schedule.
  32  *
  33  * The goal of scheduling here is to pack pairs of operations together in a
  34  * single QPU instruction.
  35  */
  36
  37 #include "vc4_qir.h"
  38 #include "vc4_qpu.h"
  39 #include "util/ralloc.h"
  40
  41 static bool debug;
  42
  43 struct schedule_node_child;
  44
  45 struct schedule_node {
  46         struct list_head link;
  47         struct queued_qpu_inst *inst;
  48         struct schedule_node_child *children;
  49         uint32_t child_count;
  50         uint32_t child_array_size;
  51         uint32_t parent_count;
  52
  53         /* Longest cycles + instruction_latency() of any parent of this node. */
  54         uint32_t unblocked_time;
  55
  56         /**
  57          * Minimum number of cycles from scheduling this instruction until the
  58          * end of the program, based on the slowest dependency chain through
  59          * the children.
  60          */
  61         uint32_t delay;
  62
  63         /**
  64          * cycles between this instruction being scheduled and when its result
  65          * can be consumed.
  66          */
  67         uint32_t latency;
  68
  69         /**
  70          * Which uniform from uniform_data[] this instruction read, or -1 if
  71          * not reading a uniform.
  72          */
  73         int uniform;
  74 };
  75
  76 struct schedule_node_child {
  77         struct schedule_node *node;
  78         bool write_after_read;
  79 };
  80
  81 /* When walking the instructions in reverse, we need to swap before/after in
  82  * add_dep().
  83  */
  84 enum direction { F, R };
  85
  86 struct schedule_state {
  87         struct schedule_node *last_r[6];
  88         struct schedule_node *last_ra[32];
  89         struct schedule_node *last_rb[32];
  90         struct schedule_node *last_sf;
  91         struct schedule_node *last_vpm_read;
  92         struct schedule_node *last_tmu_write;
  93         struct schedule_node *last_tlb;
  94         struct schedule_node *last_vpm;
  95         struct schedule_node *last_uniforms_reset;
  96         enum direction dir;
  97         /* Estimated cycle when the current instruction would start. */
  98         uint32_t time;
  99 };
 100
 101 static void
 102 add_dep(struct schedule_state *state,
 103         struct schedule_node *before,
 104         struct schedule_node *after,
 105         bool write)
 106 {
 107         bool write_after_read = !write && state->dir == R;
 108
 109         if (!before || !after)
 110                 return;
 111
 112         assert(before != after);
 113
 114         if (state->dir == R) {
 115                 struct schedule_node *t = before;
 116                 before = after;
 117                 after = t;
 118         }
 119
 120         for (int i = 0; i < before->child_count; i++) {
 121                 if (before->children[i].node == after &&
 122                     (before->children[i].write_after_read == write_after_read)) {
 123                         return;
 124                 }
 125         }
 126
 127         if (before->child_array_size <= before->child_count) {
 128                 before->child_array_size = MAX2(before->child_array_size * 2, 16);
 129                 before->children = reralloc(before, before->children,
 130                                             struct schedule_node_child,
 131                                             before->child_array_size);
 132         }
 133
 134         before->children[before->child_count].node = after;
 135         before->children[before->child_count].write_after_read =
 136                 write_after_read;
 137         before->child_count++;
 138         after->parent_count++;
 139 }
 140
 141 static void
 142 add_read_dep(struct schedule_state *state,
 143               struct schedule_node *before,
 144               struct schedule_node *after)
 145 {
 146         add_dep(state, before, after, false);
 147 }
 148
 149 static void
 150 add_write_dep(struct schedule_state *state,
 151               struct schedule_node **before,
 152               struct schedule_node *after)
 153 {
 154         add_dep(state, *before, after, true);
 155         *before = after;
 156 }
 157
 158 static bool
 159 qpu_writes_r4(uint64_t inst)
 160 {
 161         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 162
 163         switch(sig) {
 164         case QPU_SIG_COLOR_LOAD:
 165         case QPU_SIG_LOAD_TMU0:
 166         case QPU_SIG_LOAD_TMU1:
 167         case QPU_SIG_ALPHA_MASK_LOAD:
 168                 return true;
 169         default:
 170                 return false;
 171         }
 172 }
 173
 174 static void
 175 process_raddr_deps(struct schedule_state *state, struct schedule_node *n,
 176                    uint32_t raddr, bool is_a)
 177 {
 178         switch (raddr) {
 179         case QPU_R_VARY:
 180                 add_write_dep(state, &state->last_r[5], n);
 181                 break;
 182
 183         case QPU_R_VPM:
 184                 add_write_dep(state, &state->last_vpm_read, n);
 185                 break;
 186
 187         case QPU_R_UNIF:
 188                 add_read_dep(state, state->last_uniforms_reset, n);
 189                 break;
 190
 191         case QPU_R_NOP:
 192         case QPU_R_ELEM_QPU:
 193         case QPU_R_XY_PIXEL_COORD:
 194         case QPU_R_MS_REV_FLAGS:
 195                 break;
 196
 197         default:
 198                 if (raddr < 32) {
 199                         if (is_a)
 200                                 add_read_dep(state, state->last_ra[raddr], n);
 201                         else
 202                                 add_read_dep(state, state->last_rb[raddr], n);
 203                 } else {
 204                         fprintf(stderr, "unknown raddr %d\n", raddr);
 205                         abort();
 206                 }
 207                 break;
 208         }
 209 }
 210
 211 static bool
 212 is_tmu_write(uint32_t waddr)
 213 {
 214         switch (waddr) {
 215         case QPU_W_TMU0_S:
 216         case QPU_W_TMU0_T:
 217         case QPU_W_TMU0_R:
 218         case QPU_W_TMU0_B:
 219         case QPU_W_TMU1_S:
 220         case QPU_W_TMU1_T:
 221         case QPU_W_TMU1_R:
 222         case QPU_W_TMU1_B:
 223                 return true;
 224         default:
 225                 return false;
 226         }
 227 }
 228
 229 static bool
 230 reads_uniform(uint64_t inst)
 231 {
 232         if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_LOAD_IMM)
 233                 return false;
 234
 235         return (QPU_GET_FIELD(inst, QPU_RADDR_A) == QPU_R_UNIF ||
 236                 (QPU_GET_FIELD(inst, QPU_RADDR_B) == QPU_R_UNIF &&
 237                  QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_SMALL_IMM) ||
 238                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_ADD)) ||
 239                 is_tmu_write(QPU_GET_FIELD(inst, QPU_WADDR_MUL)));
 240 }
 241
 242 static void
 243 process_mux_deps(struct schedule_state *state, struct schedule_node *n,
 244                  uint32_t mux)
 245 {
 246         if (mux != QPU_MUX_A && mux != QPU_MUX_B)
 247                 add_read_dep(state, state->last_r[mux], n);
 248 }
 249
 250
 251 static void
 252 process_waddr_deps(struct schedule_state *state, struct schedule_node *n,
 253                    uint32_t waddr, bool is_add)
 254 {
 255         uint64_t inst = n->inst->inst;
 256         bool is_a = is_add ^ ((inst & QPU_WS) != 0);
 257
 258         if (waddr < 32) {
 259                 if (is_a) {
 260                         add_write_dep(state, &state->last_ra[waddr], n);
 261                 } else {
 262                         add_write_dep(state, &state->last_rb[waddr], n);
 263                 }
 264         } else if (is_tmu_write(waddr)) {
 265                 add_write_dep(state, &state->last_tmu_write, n);
 266                 add_read_dep(state, state->last_uniforms_reset, n);
 267         } else if (qpu_waddr_is_tlb(waddr) ||
 268                    waddr == QPU_W_MS_FLAGS) {
 269                 add_write_dep(state, &state->last_tlb, n);
 270         } else {
 271                 switch (waddr) {
 272                 case QPU_W_ACC0:
 273                 case QPU_W_ACC1:
 274                 case QPU_W_ACC2:
 275                 case QPU_W_ACC3:
 276                 case QPU_W_ACC5:
 277                         add_write_dep(state, &state->last_r[waddr - QPU_W_ACC0],
 278                                       n);
 279                         break;
 280
 281                 case QPU_W_VPM:
 282                         add_write_dep(state, &state->last_vpm, n);
 283                         break;
 284
 285                 case QPU_W_VPMVCD_SETUP:
 286                         if (is_a)
 287                                 add_write_dep(state, &state->last_vpm_read, n);
 288                         else
 289                                 add_write_dep(state, &state->last_vpm, n);
 290                         break;
 291
 292                 case QPU_W_SFU_RECIP:
 293                 case QPU_W_SFU_RECIPSQRT:
 294                 case QPU_W_SFU_EXP:
 295                 case QPU_W_SFU_LOG:
 296                         add_write_dep(state, &state->last_r[4], n);
 297                         break;
 298
 299                 case QPU_W_TLB_STENCIL_SETUP:
 300                         /* This isn't a TLB operation that does things like
 301                          * implicitly lock the scoreboard, but it does have to
 302                          * appear before TLB_Z, and each of the TLB_STENCILs
 303                          * have to schedule in the same order relative to each
 304                          * other.
 305                          */
 306                         add_write_dep(state, &state->last_tlb, n);
 307                         break;
 308
 309                 case QPU_W_MS_FLAGS:
 310                         add_write_dep(state, &state->last_tlb, n);
 311                         break;
 312
 313                 case QPU_W_UNIFORMS_ADDRESS:
 314                         add_write_dep(state, &state->last_uniforms_reset, n);
 315                         break;
 316
 317                 case QPU_W_NOP:
 318                         break;
 319
 320                 default:
 321                         fprintf(stderr, "Unknown waddr %d\n", waddr);
 322                         abort();
 323                 }
 324         }
 325 }
 326
 327 static void
 328 process_cond_deps(struct schedule_state *state, struct schedule_node *n,
 329                   uint32_t cond)
 330 {
 331         switch (cond) {
 332         case QPU_COND_NEVER:
 333         case QPU_COND_ALWAYS:
 334                 break;
 335         default:
 336                 add_read_dep(state, state->last_sf, n);
 337                 break;
 338         }
 339 }
 340
 341 /**
 342  * Common code for dependencies that need to be tracked both forward and
 343  * backward.
 344  *
 345  * This is for things like "all reads of r4 have to happen between the r4
 346  * writes that surround them".
 347  */
 348 static void
 349 calculate_deps(struct schedule_state *state, struct schedule_node *n)
 350 {
 351         uint64_t inst = n->inst->inst;
 352         uint32_t add_op = QPU_GET_FIELD(inst, QPU_OP_ADD);
 353         uint32_t mul_op = QPU_GET_FIELD(inst, QPU_OP_MUL);
 354         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 355         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 356         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 357         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 358         uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A);
 359         uint32_t add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
 360         uint32_t mul_a = QPU_GET_FIELD(inst, QPU_MUL_A);
 361         uint32_t mul_b = QPU_GET_FIELD(inst, QPU_MUL_B);
 362         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 363
 364         if (sig != QPU_SIG_LOAD_IMM) {
 365                 process_raddr_deps(state, n, raddr_a, true);
 366                 if (sig != QPU_SIG_SMALL_IMM &&
 367                     sig != QPU_SIG_BRANCH)
 368                         process_raddr_deps(state, n, raddr_b, false);
 369         }
 370
 371         if (add_op != QPU_A_NOP) {
 372                 process_mux_deps(state, n, add_a);
 373                 process_mux_deps(state, n, add_b);
 374         }
 375         if (mul_op != QPU_M_NOP) {
 376                 process_mux_deps(state, n, mul_a);
 377                 process_mux_deps(state, n, mul_b);
 378         }
 379
 380         process_waddr_deps(state, n, waddr_add, true);
 381         process_waddr_deps(state, n, waddr_mul, false);
 382         if (qpu_writes_r4(inst))
 383                 add_write_dep(state, &state->last_r[4], n);
 384
 385         switch (sig) {
 386         case QPU_SIG_SW_BREAKPOINT:
 387         case QPU_SIG_NONE:
 388         case QPU_SIG_THREAD_SWITCH:
 389         case QPU_SIG_LAST_THREAD_SWITCH:
 390         case QPU_SIG_SMALL_IMM:
 391         case QPU_SIG_LOAD_IMM:
 392                 break;
 393
 394         case QPU_SIG_LOAD_TMU0:
 395         case QPU_SIG_LOAD_TMU1:
 396                 /* TMU loads are coming from a FIFO, so ordering is important.
 397                  */
 398                 add_write_dep(state, &state->last_tmu_write, n);
 399                 break;
 400
 401         case QPU_SIG_COLOR_LOAD:
 402                 add_read_dep(state, state->last_tlb, n);
 403                 break;
 404
 405         case QPU_SIG_BRANCH:
 406                 add_read_dep(state, state->last_sf, n);
 407                 break;
 408
 409         case QPU_SIG_PROG_END:
 410         case QPU_SIG_WAIT_FOR_SCOREBOARD:
 411         case QPU_SIG_SCOREBOARD_UNLOCK:
 412         case QPU_SIG_COVERAGE_LOAD:
 413         case QPU_SIG_COLOR_LOAD_END:
 414         case QPU_SIG_ALPHA_MASK_LOAD:
 415                 fprintf(stderr, "Unhandled signal bits %d\n", sig);
 416                 abort();
 417         }
 418
 419         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
 420         process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_MUL));
 421         if ((inst & QPU_SF) && sig != QPU_SIG_BRANCH)
 422                 add_write_dep(state, &state->last_sf, n);
 423 }
 424
 425 static void
 426 calculate_forward_deps(struct vc4_compile *c, struct list_head *schedule_list)
 427 {
 428         struct schedule_state state;
 429
 430         memset(&state, 0, sizeof(state));
 431         state.dir = F;
 432
 433         list_for_each_entry(struct schedule_node, node, schedule_list, link)
 434                 calculate_deps(&state, node);
 435 }
 436
 437 static void
 438 calculate_reverse_deps(struct vc4_compile *c, struct list_head *schedule_list)
 439 {
 440         struct list_head *node;
 441         struct schedule_state state;
 442
 443         memset(&state, 0, sizeof(state));
 444         state.dir = R;
 445
 446         for (node = schedule_list->prev; schedule_list != node; node = node->prev) {
 447                 calculate_deps(&state, (struct schedule_node *)node);
 448         }
 449 }
 450
 451 struct choose_scoreboard {
 452         int tick;
 453         int last_sfu_write_tick;
 454         int last_uniforms_reset_tick;
 455         uint32_t last_waddr_a, last_waddr_b;
 456         bool tlb_locked;
 457 };
 458
 459 static bool
 460 reads_too_soon_after_write(struct choose_scoreboard *scoreboard, uint64_t inst)
 461 {
 462         uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
 463         uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
 464         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 465         uint32_t src_muxes[] = {
 466                 QPU_GET_FIELD(inst, QPU_ADD_A),
 467                 QPU_GET_FIELD(inst, QPU_ADD_B),
 468                 QPU_GET_FIELD(inst, QPU_MUL_A),
 469                 QPU_GET_FIELD(inst, QPU_MUL_B),
 470         };
 471         for (int i = 0; i < ARRAY_SIZE(src_muxes); i++) {
 472                 if ((src_muxes[i] == QPU_MUX_A &&
 473                      raddr_a < 32 &&
 474                      scoreboard->last_waddr_a == raddr_a) ||
 475                     (src_muxes[i] == QPU_MUX_B &&
 476                      sig != QPU_SIG_SMALL_IMM &&
 477                      raddr_b < 32 &&
 478                      scoreboard->last_waddr_b == raddr_b)) {
 479                         return true;
 480                 }
 481
 482                 if (src_muxes[i] == QPU_MUX_R4) {
 483                         if (scoreboard->tick -
 484                             scoreboard->last_sfu_write_tick <= 2) {
 485                                 return true;
 486                         }
 487                 }
 488         }
 489
 490         if (sig == QPU_SIG_SMALL_IMM &&
 491             QPU_GET_FIELD(inst, QPU_SMALL_IMM) >= QPU_SMALL_IMM_MUL_ROT) {
 492                 uint32_t mux_a = QPU_GET_FIELD(inst, QPU_MUL_A);
 493                 uint32_t mux_b = QPU_GET_FIELD(inst, QPU_MUL_B);
 494
 495                 if (scoreboard->last_waddr_a == mux_a + QPU_W_ACC0 ||
 496                     scoreboard->last_waddr_a == mux_b + QPU_W_ACC0 ||
 497                     scoreboard->last_waddr_b == mux_a + QPU_W_ACC0 ||
 498                     scoreboard->last_waddr_b == mux_b + QPU_W_ACC0) {
 499                         return true;
 500                 }
 501         }
 502
 503         if (reads_uniform(inst) &&
 504             scoreboard->tick - scoreboard->last_uniforms_reset_tick <= 2) {
 505                 return true;
 506         }
 507
 508         return false;
 509 }
 510
 511 static bool
 512 pixel_scoreboard_too_soon(struct choose_scoreboard *scoreboard, uint64_t inst)
 513 {
 514         return (scoreboard->tick < 2 && qpu_inst_is_tlb(inst));
 515 }
 516
 517 static int
 518 get_instruction_priority(uint64_t inst)
 519 {
 520         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 521         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 522         uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
 523         uint32_t baseline_score;
 524         uint32_t next_score = 0;
 525
 526         /* Schedule TLB operations as late as possible, to get more
 527          * parallelism between shaders.
 528          */
 529         if (qpu_inst_is_tlb(inst))
 530                 return next_score;
 531         next_score++;
 532
 533         /* Schedule texture read results collection late to hide latency. */
 534         if (sig == QPU_SIG_LOAD_TMU0 || sig == QPU_SIG_LOAD_TMU1)
 535                 return next_score;
 536         next_score++;
 537
 538         /* Default score for things that aren't otherwise special. */
 539         baseline_score = next_score;
 540         next_score++;
 541
 542         /* Schedule texture read setup early to hide their latency better. */
 543         if (is_tmu_write(waddr_add) || is_tmu_write(waddr_mul))
 544                 return next_score;
 545         next_score++;
 546
 547         return baseline_score;
 548 }
 549
 550 static struct schedule_node *
 551 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard,
 552                                struct list_head *schedule_list,
 553                                struct schedule_node *prev_inst)
 554 {
 555         struct schedule_node *chosen = NULL;
 556         int chosen_prio = 0;
 557
 558         list_for_each_entry(struct schedule_node, n, schedule_list, link) {
 559                 uint64_t inst = n->inst->inst;
 560
 561                 /* Don't choose the branch instruction until it's the last one
 562                  * left.  XXX: We could potentially choose it before it's the
 563                  * last one, if the remaining instructions fit in the delay
 564                  * slots.
 565                  */
 566                 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH &&
 567                     !list_is_singular(schedule_list)) {
 568                         continue;
 569                 }
 570
 571                 /* "An instruction must not read from a location in physical
 572                  *  regfile A or B that was written to by the previous
 573                  *  instruction."
 574                  */
 575                 if (reads_too_soon_after_write(scoreboard, inst))
 576                         continue;
 577
 578                 /* "A scoreboard wait must not occur in the first two
 579                  *  instructions of a fragment shader. This is either the
 580                  *  explicit Wait for Scoreboard signal or an implicit wait
 581                  *  with the first tile-buffer read or write instruction."
 582                  */
 583                 if (pixel_scoreboard_too_soon(scoreboard, inst))
 584                         continue;
 585
 586                 /* If we're trying to pair with another instruction, check
 587                  * that they're compatible.
 588                  */
 589                 if (prev_inst) {
 590                         if (prev_inst->uniform != -1 && n->uniform != -1)
 591                                 continue;
 592
 593                         /* Don't merge in something that will lock the TLB.
 594                          * Hopwefully what we have in inst will release some
 595                          * other instructions, allowing us to delay the
 596                          * TLB-locking instruction until later.
 597                          */
 598                         if (!scoreboard->tlb_locked && qpu_inst_is_tlb(inst))
 599                                 continue;
 600
 601                         inst = qpu_merge_inst(prev_inst->inst->inst, inst);
 602                         if (!inst)
 603                                 continue;
 604                 }
 605
 606                 int prio = get_instruction_priority(inst);
 607
 608                 /* Found a valid instruction.  If nothing better comes along,
 609                  * this one works.
 610                  */
 611                 if (!chosen) {
 612                         chosen = n;
 613                         chosen_prio = prio;
 614                         continue;
 615                 }
 616
 617                 if (prio > chosen_prio) {
 618                         chosen = n;
 619                         chosen_prio = prio;
 620                 } else if (prio < chosen_prio) {
 621                         continue;
 622                 }
 623
 624                 if (n->delay > chosen->delay) {
 625                         chosen = n;
 626                         chosen_prio = prio;
 627                 } else if (n->delay < chosen->delay) {
 628                         continue;
 629                 }
 630         }
 631
 632         return chosen;
 633 }
 634
 635 static void
 636 update_scoreboard_for_chosen(struct choose_scoreboard *scoreboard,
 637                              uint64_t inst)
 638 {
 639         uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
 640         uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
 641
 642         if (!(inst & QPU_WS)) {
 643                 scoreboard->last_waddr_a = waddr_add;
 644                 scoreboard->last_waddr_b = waddr_mul;
 645         } else {
 646                 scoreboard->last_waddr_b = waddr_add;
 647                 scoreboard->last_waddr_a = waddr_mul;
 648         }
 649
 650         if ((waddr_add >= QPU_W_SFU_RECIP && waddr_add <= QPU_W_SFU_LOG) ||
 651             (waddr_mul >= QPU_W_SFU_RECIP && waddr_mul <= QPU_W_SFU_LOG)) {
 652                 scoreboard->last_sfu_write_tick = scoreboard->tick;
 653         }
 654
 655         if (waddr_add == QPU_W_UNIFORMS_ADDRESS ||
 656             waddr_mul == QPU_W_UNIFORMS_ADDRESS) {
 657                 scoreboard->last_uniforms_reset_tick = scoreboard->tick;
 658         }
 659
 660         if (qpu_inst_is_tlb(inst))
 661                 scoreboard->tlb_locked = true;
 662 }
 663
 664 static void
 665 dump_state(struct list_head *schedule_list)
 666 {
 667         list_for_each_entry(struct schedule_node, n, schedule_list, link) {
 668                 fprintf(stderr, "         t=%4d: ", n->unblocked_time);
 669                 vc4_qpu_disasm(&n->inst->inst, 1);
 670                 fprintf(stderr, "\n");
 671
 672                 for (int i = 0; i < n->child_count; i++) {
 673                         struct schedule_node *child = n->children[i].node;
 674                         if (!child)
 675                                 continue;
 676
 677                         fprintf(stderr, "                 - ");
 678                         vc4_qpu_disasm(&child->inst->inst, 1);
 679                         fprintf(stderr, " (%d parents, %c)\n",
 680                                 child->parent_count,
 681                                 n->children[i].write_after_read ? 'w' : 'r');
 682                 }
 683         }
 684 }
 685
 686 static uint32_t waddr_latency(uint32_t waddr, uint64_t after)
 687 {
 688         if (waddr < 32)
 689                 return 2;
 690
 691         /* Apply some huge latency between texture fetch requests and getting
 692          * their results back.
 693          */
 694         if (waddr == QPU_W_TMU0_S) {
 695                 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU0)
 696                         return 100;
 697         }
 698         if (waddr == QPU_W_TMU1_S) {
 699                 if (QPU_GET_FIELD(after, QPU_SIG) == QPU_SIG_LOAD_TMU1)
 700                         return 100;
 701         }
 702
 703         switch(waddr) {
 704         case QPU_W_SFU_RECIP:
 705         case QPU_W_SFU_RECIPSQRT:
 706         case QPU_W_SFU_EXP:
 707         case QPU_W_SFU_LOG:
 708                 return 3;
 709         default:
 710                 return 1;
 711         }
 712 }
 713
 714 static uint32_t
 715 instruction_latency(struct schedule_node *before, struct schedule_node *after)
 716 {
 717         uint64_t before_inst = before->inst->inst;
 718         uint64_t after_inst = after->inst->inst;
 719
 720         return MAX2(waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_ADD),
 721                                   after_inst),
 722                     waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_MUL),
 723                                   after_inst));
 724 }
 725
 726 /** Recursive computation of the delay member of a node. */
 727 static void
 728 compute_delay(struct schedule_node *n)
 729 {
 730         if (!n->child_count) {
 731                 n->delay = 1;
 732         } else {
 733                 for (int i = 0; i < n->child_count; i++) {
 734                         if (!n->children[i].node->delay)
 735                                 compute_delay(n->children[i].node);
 736                         n->delay = MAX2(n->delay,
 737                                         n->children[i].node->delay +
 738                                         instruction_latency(n, n->children[i].node));
 739                 }
 740         }
 741 }
 742
 743 static void
 744 mark_instruction_scheduled(struct list_head *schedule_list,
 745                            uint32_t time,
 746                            struct schedule_node *node,
 747                            bool war_only)
 748 {
 749         if (!node)
 750                 return;
 751
 752         for (int i = node->child_count - 1; i >= 0; i--) {
 753                 struct schedule_node *child =
 754                         node->children[i].node;
 755
 756                 if (!child)
 757                         continue;
 758
 759                 if (war_only && !node->children[i].write_after_read)
 760                         continue;
 761
 762                 /* If the requirement is only that the node not appear before
 763                  * the last read of its destination, then it can be scheduled
 764                  * immediately after (or paired with!) the thing reading the
 765                  * destination.
 766                  */
 767                 uint32_t latency = 0;
 768                 if (!war_only) {
 769                         latency = instruction_latency(node,
 770                                                       node->children[i].node);
 771                 }
 772
 773                 child->unblocked_time = MAX2(child->unblocked_time,
 774                                              time + latency);
 775                 child->parent_count--;
 776                 if (child->parent_count == 0)
 777                         list_add(&child->link, schedule_list);
 778
 779                 node->children[i].node = NULL;
 780         }
 781 }
 782
 783 static uint32_t
 784 schedule_instructions(struct vc4_compile *c,
 785                       struct choose_scoreboard *scoreboard,
 786                       struct qblock *block,
 787                       struct list_head *schedule_list,
 788                       enum quniform_contents *orig_uniform_contents,
 789                       uint32_t *orig_uniform_data,
 790                       uint32_t *next_uniform)
 791 {
 792         uint32_t time = 0;
 793
 794         if (debug) {
 795                 fprintf(stderr, "initial deps:\n");
 796                 dump_state(schedule_list);
 797                 fprintf(stderr, "\n");
 798         }
 799
 800         /* Remove non-DAG heads from the list. */
 801         list_for_each_entry_safe(struct schedule_node, n, schedule_list, link) {
 802                 if (n->parent_count != 0)
 803                         list_del(&n->link);
 804         }
 805
 806         while (!list_empty(schedule_list)) {
 807                 struct schedule_node *chosen =
 808                         choose_instruction_to_schedule(scoreboard,
 809                                                        schedule_list,
 810                                                        NULL);
 811                 struct schedule_node *merge = NULL;
 812
 813                 /* If there are no valid instructions to schedule, drop a NOP
 814                  * in.
 815                  */
 816                 uint64_t inst = chosen ? chosen->inst->inst : qpu_NOP();
 817
 818                 if (debug) {
 819                         fprintf(stderr, "t=%4d: current list:\n",
 820                                 time);
 821                         dump_state(schedule_list);
 822                         fprintf(stderr, "t=%4d: chose: ", time);
 823                         vc4_qpu_disasm(&inst, 1);
 824                         fprintf(stderr, "\n");
 825                 }
 826
 827                 /* Schedule this instruction onto the QPU list. Also try to
 828                  * find an instruction to pair with it.
 829                  */
 830                 if (chosen) {
 831                         time = MAX2(chosen->unblocked_time, time);
 832                         list_del(&chosen->link);
 833                         mark_instruction_scheduled(schedule_list, time,
 834                                                    chosen, true);
 835                         if (chosen->uniform != -1) {
 836                                 c->uniform_data[*next_uniform] =
 837                                         orig_uniform_data[chosen->uniform];
 838                                 c->uniform_contents[*next_uniform] =
 839                                         orig_uniform_contents[chosen->uniform];
 840                                 (*next_uniform)++;
 841                         }
 842
 843                         merge = choose_instruction_to_schedule(scoreboard,
 844                                                                schedule_list,
 845                                                                chosen);
 846                         if (merge) {
 847                                 time = MAX2(merge->unblocked_time, time);
 848                                 list_del(&merge->link);
 849                                 inst = qpu_merge_inst(inst, merge->inst->inst);
 850                                 assert(inst != 0);
 851                                 if (merge->uniform != -1) {
 852                                         c->uniform_data[*next_uniform] =
 853                                                 orig_uniform_data[merge->uniform];
 854                                         c->uniform_contents[*next_uniform] =
 855                                                 orig_uniform_contents[merge->uniform];
 856                                         (*next_uniform)++;
 857                                 }
 858
 859                                 if (debug) {
 860                                         fprintf(stderr, "t=%4d: merging: ",
 861                                                 time);
 862                                         vc4_qpu_disasm(&merge->inst->inst, 1);
 863                                         fprintf(stderr, "\n");
 864                                         fprintf(stderr, "            resulting in: ");
 865                                         vc4_qpu_disasm(&inst, 1);
 866                                         fprintf(stderr, "\n");
 867                                 }
 868                         }
 869                 }
 870
 871                 if (debug) {
 872                         fprintf(stderr, "\n");
 873                 }
 874
 875                 qpu_serialize_one_inst(c, inst);
 876
 877                 update_scoreboard_for_chosen(scoreboard, inst);
 878
 879                 /* Now that we've scheduled a new instruction, some of its
 880                  * children can be promoted to the list of instructions ready to
 881                  * be scheduled.  Update the children's unblocked time for this
 882                  * DAG edge as we do so.
 883                  */
 884                 mark_instruction_scheduled(schedule_list, time, chosen, false);
 885                 mark_instruction_scheduled(schedule_list, time, merge, false);
 886
 887                 scoreboard->tick++;
 888                 time++;
 889
 890                 if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH) {
 891                         block->branch_qpu_ip = c->qpu_inst_count - 1;
 892                         /* Fill the delay slots.
 893                          *
 894                          * We should fill these with actual instructions,
 895                          * instead, but that will probably need to be done
 896                          * after this, once we know what the leading
 897                          * instructions of the successors are (so we can
 898                          * handle A/B register file write latency)
 899                         */
 900                         inst = qpu_NOP();
 901                         update_scoreboard_for_chosen(scoreboard, inst);
 902                         qpu_serialize_one_inst(c, inst);
 903                         qpu_serialize_one_inst(c, inst);
 904                         qpu_serialize_one_inst(c, inst);
 905                 }
 906         }
 907
 908         return time;
 909 }
 910
 911 static uint32_t
 912 qpu_schedule_instructions_block(struct vc4_compile *c,
 913                                 struct choose_scoreboard *scoreboard,
 914                                 struct qblock *block,
 915                                 enum quniform_contents *orig_uniform_contents,
 916                                 uint32_t *orig_uniform_data,
 917                                 uint32_t *next_uniform)
 918 {
 919         void *mem_ctx = ralloc_context(NULL);
 920         struct list_head schedule_list;
 921
 922         list_inithead(&schedule_list);
 923
 924         /* Wrap each instruction in a scheduler structure. */
 925         uint32_t next_sched_uniform = *next_uniform;
 926         while (!list_empty(&block->qpu_inst_list)) {
 927                 struct queued_qpu_inst *inst =
 928                         (struct queued_qpu_inst *)block->qpu_inst_list.next;
 929                 struct schedule_node *n = rzalloc(mem_ctx, struct schedule_node);
 930
 931                 n->inst = inst;
 932
 933                 if (reads_uniform(inst->inst)) {
 934                         n->uniform = next_sched_uniform++;
 935                 } else {
 936                         n->uniform = -1;
 937                 }
 938                 list_del(&inst->link);
 939                 list_addtail(&n->link, &schedule_list);
 940         }
 941
 942         calculate_forward_deps(c, &schedule_list);
 943         calculate_reverse_deps(c, &schedule_list);
 944
 945         list_for_each_entry(struct schedule_node, n, &schedule_list, link) {
 946                 compute_delay(n);
 947         }
 948
 949         uint32_t cycles = schedule_instructions(c, scoreboard, block,
 950                                                 &schedule_list,
 951                                                 orig_uniform_contents,
 952                                                 orig_uniform_data,
 953                                                 next_uniform);
 954
 955         ralloc_free(mem_ctx);
 956
 957         return cycles;
 958 }
 959
 960 static void
 961 qpu_set_branch_targets(struct vc4_compile *c)
 962 {
 963         qir_for_each_block(block, c) {
 964                 /* The end block of the program has no branch. */
 965                 if (!block->successors[0])
 966                         continue;
 967
 968                 /* If there was no branch instruction, then the successor
 969                  * block must follow immediately after this one.
 970                  */
 971                 if (block->branch_qpu_ip == ~0) {
 972                         assert(block->end_qpu_ip + 1 ==
 973                                block->successors[0]->start_qpu_ip);
 974                         continue;
 975                 }
 976
 977                 /* Set the branch target for the block that doesn't follow
 978                  * immediately after ours.
 979                  */
 980                 uint64_t *branch_inst = &c->qpu_insts[block->branch_qpu_ip];
 981                 assert(QPU_GET_FIELD(*branch_inst, QPU_SIG) == QPU_SIG_BRANCH);
 982                 assert(QPU_GET_FIELD(*branch_inst, QPU_BRANCH_TARGET) == 0);
 983
 984                 uint32_t branch_target =
 985                         (block->successors[0]->start_qpu_ip -
 986                          (block->branch_qpu_ip + 4)) * sizeof(uint64_t);
 987                 *branch_inst = (*branch_inst |
 988                                 QPU_SET_FIELD(branch_target, QPU_BRANCH_TARGET));
 989
 990                 /* Make sure that the if-we-don't-jump successor was scheduled
 991                  * just after the delay slots.
 992                  */
 993                 if (block->successors[1]) {
 994                         assert(block->successors[1]->start_qpu_ip ==
 995                                block->branch_qpu_ip + 4);
 996                 }
 997         }
 998 }
 999
1000 uint32_t
1001 qpu_schedule_instructions(struct vc4_compile *c)
1002 {
1003         /* We reorder the uniforms as we schedule instructions, so save the
1004          * old data off and replace it.
1005          */
1006         uint32_t *uniform_data = c->uniform_data;
1007         enum quniform_contents *uniform_contents = c->uniform_contents;
1008         c->uniform_contents = ralloc_array(c, enum quniform_contents,
1009                                            c->num_uniforms);
1010         c->uniform_data = ralloc_array(c, uint32_t, c->num_uniforms);
1011         c->uniform_array_size = c->num_uniforms;
1012         uint32_t next_uniform = 0;
1013
1014         struct choose_scoreboard scoreboard;
1015         memset(&scoreboard, 0, sizeof(scoreboard));
1016         scoreboard.last_waddr_a = ~0;
1017         scoreboard.last_waddr_b = ~0;
1018         scoreboard.last_sfu_write_tick = -10;
1019         scoreboard.last_uniforms_reset_tick = -10;
1020
1021         if (debug) {
1022                 fprintf(stderr, "Pre-schedule instructions\n");
1023                 qir_for_each_block(block, c) {
1024                         fprintf(stderr, "BLOCK %d\n", block->index);
1025                         list_for_each_entry(struct queued_qpu_inst, q,
1026                                             &block->qpu_inst_list, link) {
1027                                 vc4_qpu_disasm(&q->inst, 1);
1028                                 fprintf(stderr, "\n");
1029                         }
1030                 }
1031                 fprintf(stderr, "\n");
1032         }
1033
1034         uint32_t cycles = 0;
1035         qir_for_each_block(block, c) {
1036                 block->start_qpu_ip = c->qpu_inst_count;
1037                 block->branch_qpu_ip = ~0;
1038
1039                 cycles += qpu_schedule_instructions_block(c,
1040                                                           &scoreboard,
1041                                                           block,
1042                                                           uniform_contents,
1043                                                           uniform_data,
1044                                                           &next_uniform);
1045
1046                 block->end_qpu_ip = c->qpu_inst_count - 1;
1047         }
1048
1049         qpu_set_branch_targets(c);
1050
1051         assert(next_uniform == c->num_uniforms);
1052
1053         if (debug) {
1054                 fprintf(stderr, "Post-schedule instructions\n");
1055                 vc4_qpu_disasm(c->qpu_insts, c->qpu_inst_count);
1056                 fprintf(stderr, "\n");
1057         }
1058
1059         return cycles;
1060 }