2 * Copyright © 2010 Intel Corporation
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * @file vc4_qpu_schedule.c
28 * The basic model of the list scheduler is to take a basic block, compute a
29 * DAG of the dependencies, and make a list of the DAG heads. Heuristically
30 * pick a DAG head, then put all the children that are now DAG heads into the
31 * list of things to schedule.
33 * The goal of scheduling here is to pack pairs of operations together in a
34 * single QPU instruction.
39 #include "util/ralloc.h"
43 struct schedule_node_child
;
45 struct schedule_node
{
46 struct list_head link
;
47 struct queued_qpu_inst
*inst
;
48 struct schedule_node_child
*children
;
50 uint32_t child_array_size
;
51 uint32_t parent_count
;
53 /* Longest cycles + instruction_latency() of any parent of this node. */
54 uint32_t unblocked_time
;
57 * Minimum number of cycles from scheduling this instruction until the
58 * end of the program, based on the slowest dependency chain through
64 * cycles between this instruction being scheduled and when its result
70 * Which uniform from uniform_data[] this instruction read, or -1 if
71 * not reading a uniform.
76 struct schedule_node_child
{
77 struct schedule_node
*node
;
78 bool write_after_read
;
81 /* When walking the instructions in reverse, we need to swap before/after in
84 enum direction
{ F
, R
};
86 struct schedule_state
{
87 struct schedule_node
*last_r
[6];
88 struct schedule_node
*last_ra
[32];
89 struct schedule_node
*last_rb
[32];
90 struct schedule_node
*last_sf
;
91 struct schedule_node
*last_vpm_read
;
92 struct schedule_node
*last_tmu_write
;
93 struct schedule_node
*last_tlb
;
94 struct schedule_node
*last_vpm
;
95 struct schedule_node
*last_uniforms_reset
;
97 /* Estimated cycle when the current instruction would start. */
102 add_dep(struct schedule_state
*state
,
103 struct schedule_node
*before
,
104 struct schedule_node
*after
,
107 bool write_after_read
= !write
&& state
->dir
== R
;
109 if (!before
|| !after
)
112 assert(before
!= after
);
114 if (state
->dir
== R
) {
115 struct schedule_node
*t
= before
;
120 for (int i
= 0; i
< before
->child_count
; i
++) {
121 if (before
->children
[i
].node
== after
&&
122 (before
->children
[i
].write_after_read
== write_after_read
)) {
127 if (before
->child_array_size
<= before
->child_count
) {
128 before
->child_array_size
= MAX2(before
->child_array_size
* 2, 16);
129 before
->children
= reralloc(before
, before
->children
,
130 struct schedule_node_child
,
131 before
->child_array_size
);
134 before
->children
[before
->child_count
].node
= after
;
135 before
->children
[before
->child_count
].write_after_read
=
137 before
->child_count
++;
138 after
->parent_count
++;
142 add_read_dep(struct schedule_state
*state
,
143 struct schedule_node
*before
,
144 struct schedule_node
*after
)
146 add_dep(state
, before
, after
, false);
150 add_write_dep(struct schedule_state
*state
,
151 struct schedule_node
**before
,
152 struct schedule_node
*after
)
154 add_dep(state
, *before
, after
, true);
159 qpu_writes_r4(uint64_t inst
)
161 uint32_t sig
= QPU_GET_FIELD(inst
, QPU_SIG
);
164 case QPU_SIG_COLOR_LOAD
:
165 case QPU_SIG_LOAD_TMU0
:
166 case QPU_SIG_LOAD_TMU1
:
167 case QPU_SIG_ALPHA_MASK_LOAD
:
175 process_raddr_deps(struct schedule_state
*state
, struct schedule_node
*n
,
176 uint32_t raddr
, bool is_a
)
180 add_write_dep(state
, &state
->last_r
[5], n
);
184 add_write_dep(state
, &state
->last_vpm_read
, n
);
188 add_read_dep(state
, state
->last_uniforms_reset
, n
);
193 case QPU_R_XY_PIXEL_COORD
:
194 case QPU_R_MS_REV_FLAGS
:
200 add_read_dep(state
, state
->last_ra
[raddr
], n
);
202 add_read_dep(state
, state
->last_rb
[raddr
], n
);
204 fprintf(stderr
, "unknown raddr %d\n", raddr
);
212 is_tmu_write(uint32_t waddr
)
230 reads_uniform(uint64_t inst
)
232 if (QPU_GET_FIELD(inst
, QPU_SIG
) == QPU_SIG_LOAD_IMM
)
235 return (QPU_GET_FIELD(inst
, QPU_RADDR_A
) == QPU_R_UNIF
||
236 (QPU_GET_FIELD(inst
, QPU_RADDR_B
) == QPU_R_UNIF
&&
237 QPU_GET_FIELD(inst
, QPU_SIG
) != QPU_SIG_SMALL_IMM
) ||
238 is_tmu_write(QPU_GET_FIELD(inst
, QPU_WADDR_ADD
)) ||
239 is_tmu_write(QPU_GET_FIELD(inst
, QPU_WADDR_MUL
)));
243 process_mux_deps(struct schedule_state
*state
, struct schedule_node
*n
,
246 if (mux
!= QPU_MUX_A
&& mux
!= QPU_MUX_B
)
247 add_read_dep(state
, state
->last_r
[mux
], n
);
252 process_waddr_deps(struct schedule_state
*state
, struct schedule_node
*n
,
253 uint32_t waddr
, bool is_add
)
255 uint64_t inst
= n
->inst
->inst
;
256 bool is_a
= is_add
^ ((inst
& QPU_WS
) != 0);
260 add_write_dep(state
, &state
->last_ra
[waddr
], n
);
262 add_write_dep(state
, &state
->last_rb
[waddr
], n
);
264 } else if (is_tmu_write(waddr
)) {
265 add_write_dep(state
, &state
->last_tmu_write
, n
);
266 add_read_dep(state
, state
->last_uniforms_reset
, n
);
267 } else if (qpu_waddr_is_tlb(waddr
) ||
268 waddr
== QPU_W_MS_FLAGS
) {
269 add_write_dep(state
, &state
->last_tlb
, n
);
277 add_write_dep(state
, &state
->last_r
[waddr
- QPU_W_ACC0
],
282 add_write_dep(state
, &state
->last_vpm
, n
);
285 case QPU_W_VPMVCD_SETUP
:
287 add_write_dep(state
, &state
->last_vpm_read
, n
);
289 add_write_dep(state
, &state
->last_vpm
, n
);
292 case QPU_W_SFU_RECIP
:
293 case QPU_W_SFU_RECIPSQRT
:
296 add_write_dep(state
, &state
->last_r
[4], n
);
299 case QPU_W_TLB_STENCIL_SETUP
:
300 /* This isn't a TLB operation that does things like
301 * implicitly lock the scoreboard, but it does have to
302 * appear before TLB_Z, and each of the TLB_STENCILs
303 * have to schedule in the same order relative to each
306 add_write_dep(state
, &state
->last_tlb
, n
);
310 add_write_dep(state
, &state
->last_tlb
, n
);
313 case QPU_W_UNIFORMS_ADDRESS
:
314 add_write_dep(state
, &state
->last_uniforms_reset
, n
);
321 fprintf(stderr
, "Unknown waddr %d\n", waddr
);
328 process_cond_deps(struct schedule_state
*state
, struct schedule_node
*n
,
333 case QPU_COND_ALWAYS
:
336 add_read_dep(state
, state
->last_sf
, n
);
342 * Common code for dependencies that need to be tracked both forward and
345 * This is for things like "all reads of r4 have to happen between the r4
346 * writes that surround them".
349 calculate_deps(struct schedule_state
*state
, struct schedule_node
*n
)
351 uint64_t inst
= n
->inst
->inst
;
352 uint32_t add_op
= QPU_GET_FIELD(inst
, QPU_OP_ADD
);
353 uint32_t mul_op
= QPU_GET_FIELD(inst
, QPU_OP_MUL
);
354 uint32_t waddr_add
= QPU_GET_FIELD(inst
, QPU_WADDR_ADD
);
355 uint32_t waddr_mul
= QPU_GET_FIELD(inst
, QPU_WADDR_MUL
);
356 uint32_t raddr_a
= QPU_GET_FIELD(inst
, QPU_RADDR_A
);
357 uint32_t raddr_b
= QPU_GET_FIELD(inst
, QPU_RADDR_B
);
358 uint32_t add_a
= QPU_GET_FIELD(inst
, QPU_ADD_A
);
359 uint32_t add_b
= QPU_GET_FIELD(inst
, QPU_ADD_B
);
360 uint32_t mul_a
= QPU_GET_FIELD(inst
, QPU_MUL_A
);
361 uint32_t mul_b
= QPU_GET_FIELD(inst
, QPU_MUL_B
);
362 uint32_t sig
= QPU_GET_FIELD(inst
, QPU_SIG
);
364 if (sig
!= QPU_SIG_LOAD_IMM
) {
365 process_raddr_deps(state
, n
, raddr_a
, true);
366 if (sig
!= QPU_SIG_SMALL_IMM
&&
367 sig
!= QPU_SIG_BRANCH
)
368 process_raddr_deps(state
, n
, raddr_b
, false);
371 if (add_op
!= QPU_A_NOP
) {
372 process_mux_deps(state
, n
, add_a
);
373 process_mux_deps(state
, n
, add_b
);
375 if (mul_op
!= QPU_M_NOP
) {
376 process_mux_deps(state
, n
, mul_a
);
377 process_mux_deps(state
, n
, mul_b
);
380 process_waddr_deps(state
, n
, waddr_add
, true);
381 process_waddr_deps(state
, n
, waddr_mul
, false);
382 if (qpu_writes_r4(inst
))
383 add_write_dep(state
, &state
->last_r
[4], n
);
386 case QPU_SIG_SW_BREAKPOINT
:
388 case QPU_SIG_SMALL_IMM
:
389 case QPU_SIG_LOAD_IMM
:
392 case QPU_SIG_THREAD_SWITCH
:
393 case QPU_SIG_LAST_THREAD_SWITCH
:
394 /* All accumulator contents and flags are undefined after the
397 for (int i
= 0; i
< ARRAY_SIZE(state
->last_r
); i
++)
398 add_write_dep(state
, &state
->last_r
[i
], n
);
399 add_write_dep(state
, &state
->last_sf
, n
);
401 /* Scoreboard-locking operations have to stay after the last
404 add_write_dep(state
, &state
->last_tlb
, n
);
406 add_write_dep(state
, &state
->last_tmu_write
, n
);
409 case QPU_SIG_LOAD_TMU0
:
410 case QPU_SIG_LOAD_TMU1
:
411 /* TMU loads are coming from a FIFO, so ordering is important.
413 add_write_dep(state
, &state
->last_tmu_write
, n
);
416 case QPU_SIG_COLOR_LOAD
:
417 add_read_dep(state
, state
->last_tlb
, n
);
421 add_read_dep(state
, state
->last_sf
, n
);
424 case QPU_SIG_PROG_END
:
425 case QPU_SIG_WAIT_FOR_SCOREBOARD
:
426 case QPU_SIG_SCOREBOARD_UNLOCK
:
427 case QPU_SIG_COVERAGE_LOAD
:
428 case QPU_SIG_COLOR_LOAD_END
:
429 case QPU_SIG_ALPHA_MASK_LOAD
:
430 fprintf(stderr
, "Unhandled signal bits %d\n", sig
);
434 process_cond_deps(state
, n
, QPU_GET_FIELD(inst
, QPU_COND_ADD
));
435 process_cond_deps(state
, n
, QPU_GET_FIELD(inst
, QPU_COND_MUL
));
436 if ((inst
& QPU_SF
) && sig
!= QPU_SIG_BRANCH
)
437 add_write_dep(state
, &state
->last_sf
, n
);
441 calculate_forward_deps(struct vc4_compile
*c
, struct list_head
*schedule_list
)
443 struct schedule_state state
;
445 memset(&state
, 0, sizeof(state
));
448 list_for_each_entry(struct schedule_node
, node
, schedule_list
, link
)
449 calculate_deps(&state
, node
);
453 calculate_reverse_deps(struct vc4_compile
*c
, struct list_head
*schedule_list
)
455 struct schedule_state state
;
457 memset(&state
, 0, sizeof(state
));
460 list_for_each_entry_rev(struct schedule_node
, node
, schedule_list
,
462 calculate_deps(&state
, (struct schedule_node
*)node
);
466 struct choose_scoreboard
{
468 int last_sfu_write_tick
;
469 int last_uniforms_reset_tick
;
470 uint32_t last_waddr_a
, last_waddr_b
;
475 reads_too_soon_after_write(struct choose_scoreboard
*scoreboard
, uint64_t inst
)
477 uint32_t raddr_a
= QPU_GET_FIELD(inst
, QPU_RADDR_A
);
478 uint32_t raddr_b
= QPU_GET_FIELD(inst
, QPU_RADDR_B
);
479 uint32_t sig
= QPU_GET_FIELD(inst
, QPU_SIG
);
481 /* Full immediate loads don't read any registers. */
482 if (sig
== QPU_SIG_LOAD_IMM
)
485 uint32_t src_muxes
[] = {
486 QPU_GET_FIELD(inst
, QPU_ADD_A
),
487 QPU_GET_FIELD(inst
, QPU_ADD_B
),
488 QPU_GET_FIELD(inst
, QPU_MUL_A
),
489 QPU_GET_FIELD(inst
, QPU_MUL_B
),
491 for (int i
= 0; i
< ARRAY_SIZE(src_muxes
); i
++) {
492 if ((src_muxes
[i
] == QPU_MUX_A
&&
494 scoreboard
->last_waddr_a
== raddr_a
) ||
495 (src_muxes
[i
] == QPU_MUX_B
&&
496 sig
!= QPU_SIG_SMALL_IMM
&&
498 scoreboard
->last_waddr_b
== raddr_b
)) {
502 if (src_muxes
[i
] == QPU_MUX_R4
) {
503 if (scoreboard
->tick
-
504 scoreboard
->last_sfu_write_tick
<= 2) {
510 if (sig
== QPU_SIG_SMALL_IMM
&&
511 QPU_GET_FIELD(inst
, QPU_SMALL_IMM
) >= QPU_SMALL_IMM_MUL_ROT
) {
512 uint32_t mux_a
= QPU_GET_FIELD(inst
, QPU_MUL_A
);
513 uint32_t mux_b
= QPU_GET_FIELD(inst
, QPU_MUL_B
);
515 if (scoreboard
->last_waddr_a
== mux_a
+ QPU_W_ACC0
||
516 scoreboard
->last_waddr_a
== mux_b
+ QPU_W_ACC0
||
517 scoreboard
->last_waddr_b
== mux_a
+ QPU_W_ACC0
||
518 scoreboard
->last_waddr_b
== mux_b
+ QPU_W_ACC0
) {
523 if (reads_uniform(inst
) &&
524 scoreboard
->tick
- scoreboard
->last_uniforms_reset_tick
<= 2) {
532 pixel_scoreboard_too_soon(struct choose_scoreboard
*scoreboard
, uint64_t inst
)
534 return (scoreboard
->tick
< 2 && qpu_inst_is_tlb(inst
));
538 get_instruction_priority(uint64_t inst
)
540 uint32_t waddr_add
= QPU_GET_FIELD(inst
, QPU_WADDR_ADD
);
541 uint32_t waddr_mul
= QPU_GET_FIELD(inst
, QPU_WADDR_MUL
);
542 uint32_t sig
= QPU_GET_FIELD(inst
, QPU_SIG
);
543 uint32_t baseline_score
;
544 uint32_t next_score
= 0;
546 /* Schedule TLB operations as late as possible, to get more
547 * parallelism between shaders.
549 if (qpu_inst_is_tlb(inst
))
553 /* Schedule texture read results collection late to hide latency. */
554 if (sig
== QPU_SIG_LOAD_TMU0
|| sig
== QPU_SIG_LOAD_TMU1
)
558 /* Default score for things that aren't otherwise special. */
559 baseline_score
= next_score
;
562 /* Schedule texture read setup early to hide their latency better. */
563 if (is_tmu_write(waddr_add
) || is_tmu_write(waddr_mul
))
567 return baseline_score
;
570 static struct schedule_node
*
571 choose_instruction_to_schedule(struct choose_scoreboard
*scoreboard
,
572 struct list_head
*schedule_list
,
573 struct schedule_node
*prev_inst
)
575 struct schedule_node
*chosen
= NULL
;
578 /* Don't pair up anything with a thread switch signal -- emit_thrsw()
579 * will handle pairing it along with filling the delay slots.
582 uint32_t prev_sig
= QPU_GET_FIELD(prev_inst
->inst
->inst
,
584 if (prev_sig
== QPU_SIG_THREAD_SWITCH
||
585 prev_sig
== QPU_SIG_LAST_THREAD_SWITCH
) {
590 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
591 uint64_t inst
= n
->inst
->inst
;
592 uint32_t sig
= QPU_GET_FIELD(inst
, QPU_SIG
);
594 /* Don't choose the branch instruction until it's the last one
595 * left. XXX: We could potentially choose it before it's the
596 * last one, if the remaining instructions fit in the delay
599 if (sig
== QPU_SIG_BRANCH
&&
600 !list_is_singular(schedule_list
)) {
604 /* "An instruction must not read from a location in physical
605 * regfile A or B that was written to by the previous
608 if (reads_too_soon_after_write(scoreboard
, inst
))
611 /* "A scoreboard wait must not occur in the first two
612 * instructions of a fragment shader. This is either the
613 * explicit Wait for Scoreboard signal or an implicit wait
614 * with the first tile-buffer read or write instruction."
616 if (pixel_scoreboard_too_soon(scoreboard
, inst
))
619 /* If we're trying to pair with another instruction, check
620 * that they're compatible.
623 /* Don't pair up a thread switch signal -- we'll
624 * handle pairing it when we pick it on its own.
626 if (sig
== QPU_SIG_THREAD_SWITCH
||
627 sig
== QPU_SIG_LAST_THREAD_SWITCH
) {
631 if (prev_inst
->uniform
!= -1 && n
->uniform
!= -1)
634 /* Don't merge in something that will lock the TLB.
635 * Hopwefully what we have in inst will release some
636 * other instructions, allowing us to delay the
637 * TLB-locking instruction until later.
639 if (!scoreboard
->tlb_locked
&& qpu_inst_is_tlb(inst
))
642 inst
= qpu_merge_inst(prev_inst
->inst
->inst
, inst
);
647 int prio
= get_instruction_priority(inst
);
649 /* Found a valid instruction. If nothing better comes along,
658 if (prio
> chosen_prio
) {
661 } else if (prio
< chosen_prio
) {
665 if (n
->delay
> chosen
->delay
) {
668 } else if (n
->delay
< chosen
->delay
) {
677 update_scoreboard_for_chosen(struct choose_scoreboard
*scoreboard
,
680 uint32_t waddr_add
= QPU_GET_FIELD(inst
, QPU_WADDR_ADD
);
681 uint32_t waddr_mul
= QPU_GET_FIELD(inst
, QPU_WADDR_MUL
);
683 if (!(inst
& QPU_WS
)) {
684 scoreboard
->last_waddr_a
= waddr_add
;
685 scoreboard
->last_waddr_b
= waddr_mul
;
687 scoreboard
->last_waddr_b
= waddr_add
;
688 scoreboard
->last_waddr_a
= waddr_mul
;
691 if ((waddr_add
>= QPU_W_SFU_RECIP
&& waddr_add
<= QPU_W_SFU_LOG
) ||
692 (waddr_mul
>= QPU_W_SFU_RECIP
&& waddr_mul
<= QPU_W_SFU_LOG
)) {
693 scoreboard
->last_sfu_write_tick
= scoreboard
->tick
;
696 if (waddr_add
== QPU_W_UNIFORMS_ADDRESS
||
697 waddr_mul
== QPU_W_UNIFORMS_ADDRESS
) {
698 scoreboard
->last_uniforms_reset_tick
= scoreboard
->tick
;
701 if (qpu_inst_is_tlb(inst
))
702 scoreboard
->tlb_locked
= true;
706 dump_state(struct list_head
*schedule_list
)
708 list_for_each_entry(struct schedule_node
, n
, schedule_list
, link
) {
709 fprintf(stderr
, " t=%4d: ", n
->unblocked_time
);
710 vc4_qpu_disasm(&n
->inst
->inst
, 1);
711 fprintf(stderr
, "\n");
713 for (int i
= 0; i
< n
->child_count
; i
++) {
714 struct schedule_node
*child
= n
->children
[i
].node
;
718 fprintf(stderr
, " - ");
719 vc4_qpu_disasm(&child
->inst
->inst
, 1);
720 fprintf(stderr
, " (%d parents, %c)\n",
722 n
->children
[i
].write_after_read
? 'w' : 'r');
727 static uint32_t waddr_latency(uint32_t waddr
, uint64_t after
)
732 /* Apply some huge latency between texture fetch requests and getting
733 * their results back.
735 * FIXME: This is actually pretty bogus. If we do:
744 * we count that as worse than
753 * because we associate the first load_tmu0 with the *second* tmu0_s.
755 if (waddr
== QPU_W_TMU0_S
) {
756 if (QPU_GET_FIELD(after
, QPU_SIG
) == QPU_SIG_LOAD_TMU0
)
759 if (waddr
== QPU_W_TMU1_S
) {
760 if (QPU_GET_FIELD(after
, QPU_SIG
) == QPU_SIG_LOAD_TMU1
)
765 case QPU_W_SFU_RECIP
:
766 case QPU_W_SFU_RECIPSQRT
:
776 instruction_latency(struct schedule_node
*before
, struct schedule_node
*after
)
778 uint64_t before_inst
= before
->inst
->inst
;
779 uint64_t after_inst
= after
->inst
->inst
;
781 return MAX2(waddr_latency(QPU_GET_FIELD(before_inst
, QPU_WADDR_ADD
),
783 waddr_latency(QPU_GET_FIELD(before_inst
, QPU_WADDR_MUL
),
787 /** Recursive computation of the delay member of a node. */
789 compute_delay(struct schedule_node
*n
)
791 if (!n
->child_count
) {
794 for (int i
= 0; i
< n
->child_count
; i
++) {
795 if (!n
->children
[i
].node
->delay
)
796 compute_delay(n
->children
[i
].node
);
797 n
->delay
= MAX2(n
->delay
,
798 n
->children
[i
].node
->delay
+
799 instruction_latency(n
, n
->children
[i
].node
));
805 mark_instruction_scheduled(struct list_head
*schedule_list
,
807 struct schedule_node
*node
,
813 for (int i
= node
->child_count
- 1; i
>= 0; i
--) {
814 struct schedule_node
*child
=
815 node
->children
[i
].node
;
820 if (war_only
&& !node
->children
[i
].write_after_read
)
823 /* If the requirement is only that the node not appear before
824 * the last read of its destination, then it can be scheduled
825 * immediately after (or paired with!) the thing reading the
828 uint32_t latency
= 0;
830 latency
= instruction_latency(node
,
831 node
->children
[i
].node
);
834 child
->unblocked_time
= MAX2(child
->unblocked_time
,
836 child
->parent_count
--;
837 if (child
->parent_count
== 0)
838 list_add(&child
->link
, schedule_list
);
840 node
->children
[i
].node
= NULL
;
845 * Emits a THRSW/LTHRSW signal in the stream, trying to move it up to pair
846 * with another instruction.
849 emit_thrsw(struct vc4_compile
*c
,
850 struct choose_scoreboard
*scoreboard
,
853 uint32_t sig
= QPU_GET_FIELD(inst
, QPU_SIG
);
855 /* There should be nothing in a thrsw inst being scheduled other than
858 assert(QPU_GET_FIELD(inst
, QPU_OP_ADD
) == QPU_A_NOP
);
859 assert(QPU_GET_FIELD(inst
, QPU_OP_MUL
) == QPU_M_NOP
);
861 /* Try to find an earlier scheduled instruction that we can merge the
864 int thrsw_ip
= c
->qpu_inst_count
;
865 for (int i
= 1; i
<= MIN2(c
->qpu_inst_count
, 3); i
++) {
866 uint64_t prev_instr
= c
->qpu_insts
[c
->qpu_inst_count
- i
];
867 uint32_t prev_sig
= QPU_GET_FIELD(prev_instr
, QPU_SIG
);
869 if (prev_sig
== QPU_SIG_NONE
)
870 thrsw_ip
= c
->qpu_inst_count
- i
;
873 if (thrsw_ip
!= c
->qpu_inst_count
) {
874 /* Merge the thrsw into the existing instruction. */
875 c
->qpu_insts
[thrsw_ip
] =
876 QPU_UPDATE_FIELD(c
->qpu_insts
[thrsw_ip
], sig
, QPU_SIG
);
878 qpu_serialize_one_inst(c
, inst
);
879 update_scoreboard_for_chosen(scoreboard
, inst
);
882 /* Fill the delay slots. */
883 while (c
->qpu_inst_count
< thrsw_ip
+ 3) {
884 update_scoreboard_for_chosen(scoreboard
, qpu_NOP());
885 qpu_serialize_one_inst(c
, qpu_NOP());
890 schedule_instructions(struct vc4_compile
*c
,
891 struct choose_scoreboard
*scoreboard
,
892 struct qblock
*block
,
893 struct list_head
*schedule_list
,
894 enum quniform_contents
*orig_uniform_contents
,
895 uint32_t *orig_uniform_data
,
896 uint32_t *next_uniform
)
901 fprintf(stderr
, "initial deps:\n");
902 dump_state(schedule_list
);
903 fprintf(stderr
, "\n");
906 /* Remove non-DAG heads from the list. */
907 list_for_each_entry_safe(struct schedule_node
, n
, schedule_list
, link
) {
908 if (n
->parent_count
!= 0)
912 while (!list_empty(schedule_list
)) {
913 struct schedule_node
*chosen
=
914 choose_instruction_to_schedule(scoreboard
,
917 struct schedule_node
*merge
= NULL
;
919 /* If there are no valid instructions to schedule, drop a NOP
922 uint64_t inst
= chosen
? chosen
->inst
->inst
: qpu_NOP();
925 fprintf(stderr
, "t=%4d: current list:\n",
927 dump_state(schedule_list
);
928 fprintf(stderr
, "t=%4d: chose: ", time
);
929 vc4_qpu_disasm(&inst
, 1);
930 fprintf(stderr
, "\n");
933 /* Schedule this instruction onto the QPU list. Also try to
934 * find an instruction to pair with it.
937 time
= MAX2(chosen
->unblocked_time
, time
);
938 list_del(&chosen
->link
);
939 mark_instruction_scheduled(schedule_list
, time
,
941 if (chosen
->uniform
!= -1) {
942 c
->uniform_data
[*next_uniform
] =
943 orig_uniform_data
[chosen
->uniform
];
944 c
->uniform_contents
[*next_uniform
] =
945 orig_uniform_contents
[chosen
->uniform
];
949 merge
= choose_instruction_to_schedule(scoreboard
,
953 time
= MAX2(merge
->unblocked_time
, time
);
954 list_del(&merge
->link
);
955 inst
= qpu_merge_inst(inst
, merge
->inst
->inst
);
957 if (merge
->uniform
!= -1) {
958 c
->uniform_data
[*next_uniform
] =
959 orig_uniform_data
[merge
->uniform
];
960 c
->uniform_contents
[*next_uniform
] =
961 orig_uniform_contents
[merge
->uniform
];
966 fprintf(stderr
, "t=%4d: merging: ",
968 vc4_qpu_disasm(&merge
->inst
->inst
, 1);
969 fprintf(stderr
, "\n");
970 fprintf(stderr
, " resulting in: ");
971 vc4_qpu_disasm(&inst
, 1);
972 fprintf(stderr
, "\n");
978 fprintf(stderr
, "\n");
981 /* Now that we've scheduled a new instruction, some of its
982 * children can be promoted to the list of instructions ready to
983 * be scheduled. Update the children's unblocked time for this
984 * DAG edge as we do so.
986 mark_instruction_scheduled(schedule_list
, time
, chosen
, false);
987 mark_instruction_scheduled(schedule_list
, time
, merge
, false);
989 if (QPU_GET_FIELD(inst
, QPU_SIG
) == QPU_SIG_THREAD_SWITCH
||
990 QPU_GET_FIELD(inst
, QPU_SIG
) == QPU_SIG_LAST_THREAD_SWITCH
) {
991 emit_thrsw(c
, scoreboard
, inst
);
993 qpu_serialize_one_inst(c
, inst
);
994 update_scoreboard_for_chosen(scoreboard
, inst
);
1000 if (QPU_GET_FIELD(inst
, QPU_SIG
) == QPU_SIG_BRANCH
) {
1001 block
->branch_qpu_ip
= c
->qpu_inst_count
- 1;
1002 /* Fill the delay slots.
1004 * We should fill these with actual instructions,
1005 * instead, but that will probably need to be done
1006 * after this, once we know what the leading
1007 * instructions of the successors are (so we can
1008 * handle A/B register file write latency)
1011 update_scoreboard_for_chosen(scoreboard
, inst
);
1012 qpu_serialize_one_inst(c
, inst
);
1013 qpu_serialize_one_inst(c
, inst
);
1014 qpu_serialize_one_inst(c
, inst
);
1022 qpu_schedule_instructions_block(struct vc4_compile
*c
,
1023 struct choose_scoreboard
*scoreboard
,
1024 struct qblock
*block
,
1025 enum quniform_contents
*orig_uniform_contents
,
1026 uint32_t *orig_uniform_data
,
1027 uint32_t *next_uniform
)
1029 void *mem_ctx
= ralloc_context(NULL
);
1030 struct list_head schedule_list
;
1032 list_inithead(&schedule_list
);
1034 /* Wrap each instruction in a scheduler structure. */
1035 uint32_t next_sched_uniform
= *next_uniform
;
1036 while (!list_empty(&block
->qpu_inst_list
)) {
1037 struct queued_qpu_inst
*inst
=
1038 (struct queued_qpu_inst
*)block
->qpu_inst_list
.next
;
1039 struct schedule_node
*n
= rzalloc(mem_ctx
, struct schedule_node
);
1043 if (reads_uniform(inst
->inst
)) {
1044 n
->uniform
= next_sched_uniform
++;
1048 list_del(&inst
->link
);
1049 list_addtail(&n
->link
, &schedule_list
);
1052 calculate_forward_deps(c
, &schedule_list
);
1053 calculate_reverse_deps(c
, &schedule_list
);
1055 list_for_each_entry(struct schedule_node
, n
, &schedule_list
, link
) {
1059 uint32_t cycles
= schedule_instructions(c
, scoreboard
, block
,
1061 orig_uniform_contents
,
1065 ralloc_free(mem_ctx
);
1071 qpu_set_branch_targets(struct vc4_compile
*c
)
1073 qir_for_each_block(block
, c
) {
1074 /* The end block of the program has no branch. */
1075 if (!block
->successors
[0])
1078 /* If there was no branch instruction, then the successor
1079 * block must follow immediately after this one.
1081 if (block
->branch_qpu_ip
== ~0) {
1082 assert(block
->end_qpu_ip
+ 1 ==
1083 block
->successors
[0]->start_qpu_ip
);
1087 /* Set the branch target for the block that doesn't follow
1088 * immediately after ours.
1090 uint64_t *branch_inst
= &c
->qpu_insts
[block
->branch_qpu_ip
];
1091 assert(QPU_GET_FIELD(*branch_inst
, QPU_SIG
) == QPU_SIG_BRANCH
);
1092 assert(QPU_GET_FIELD(*branch_inst
, QPU_BRANCH_TARGET
) == 0);
1094 uint32_t branch_target
=
1095 (block
->successors
[0]->start_qpu_ip
-
1096 (block
->branch_qpu_ip
+ 4)) * sizeof(uint64_t);
1097 *branch_inst
= (*branch_inst
|
1098 QPU_SET_FIELD(branch_target
, QPU_BRANCH_TARGET
));
1100 /* Make sure that the if-we-don't-jump successor was scheduled
1101 * just after the delay slots.
1103 if (block
->successors
[1]) {
1104 assert(block
->successors
[1]->start_qpu_ip
==
1105 block
->branch_qpu_ip
+ 4);
1111 qpu_schedule_instructions(struct vc4_compile
*c
)
1113 /* We reorder the uniforms as we schedule instructions, so save the
1114 * old data off and replace it.
1116 uint32_t *uniform_data
= c
->uniform_data
;
1117 enum quniform_contents
*uniform_contents
= c
->uniform_contents
;
1118 c
->uniform_contents
= ralloc_array(c
, enum quniform_contents
,
1120 c
->uniform_data
= ralloc_array(c
, uint32_t, c
->num_uniforms
);
1121 c
->uniform_array_size
= c
->num_uniforms
;
1122 uint32_t next_uniform
= 0;
1124 struct choose_scoreboard scoreboard
;
1125 memset(&scoreboard
, 0, sizeof(scoreboard
));
1126 scoreboard
.last_waddr_a
= ~0;
1127 scoreboard
.last_waddr_b
= ~0;
1128 scoreboard
.last_sfu_write_tick
= -10;
1129 scoreboard
.last_uniforms_reset_tick
= -10;
1132 fprintf(stderr
, "Pre-schedule instructions\n");
1133 qir_for_each_block(block
, c
) {
1134 fprintf(stderr
, "BLOCK %d\n", block
->index
);
1135 list_for_each_entry(struct queued_qpu_inst
, q
,
1136 &block
->qpu_inst_list
, link
) {
1137 vc4_qpu_disasm(&q
->inst
, 1);
1138 fprintf(stderr
, "\n");
1141 fprintf(stderr
, "\n");
1144 uint32_t cycles
= 0;
1145 qir_for_each_block(block
, c
) {
1146 block
->start_qpu_ip
= c
->qpu_inst_count
;
1147 block
->branch_qpu_ip
= ~0;
1149 cycles
+= qpu_schedule_instructions_block(c
,
1156 block
->end_qpu_ip
= c
->qpu_inst_count
- 1;
1159 qpu_set_branch_targets(c
);
1161 assert(next_uniform
== c
->num_uniforms
);
1164 fprintf(stderr
, "Post-schedule instructions\n");
1165 vc4_qpu_disasm(c
->qpu_insts
, c
->qpu_inst_count
);
1166 fprintf(stderr
, "\n");