2 * Copyright © 2014 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 writes_reg(uint64_t inst
, uint32_t w
)
29 return (QPU_GET_FIELD(inst
, QPU_WADDR_ADD
) == w
||
30 QPU_GET_FIELD(inst
, QPU_WADDR_MUL
) == w
);
34 _reads_reg(uint64_t inst
, uint32_t r
, bool ignore_a
, bool ignore_b
)
39 { QPU_GET_FIELD(inst
, QPU_ADD_A
) },
40 { QPU_GET_FIELD(inst
, QPU_ADD_B
) },
41 { QPU_GET_FIELD(inst
, QPU_MUL_A
) },
42 { QPU_GET_FIELD(inst
, QPU_MUL_B
) },
45 for (int i
= 0; i
< ARRAY_SIZE(src_regs
); i
++) {
47 src_regs
[i
].mux
== QPU_MUX_A
&&
48 (QPU_GET_FIELD(inst
, QPU_RADDR_A
) == r
))
52 src_regs
[i
].mux
== QPU_MUX_B
&&
53 (QPU_GET_FIELD(inst
, QPU_RADDR_B
) == r
))
61 reads_reg(uint64_t inst
, uint32_t r
)
63 return _reads_reg(inst
, r
, false, false);
67 reads_a_reg(uint64_t inst
, uint32_t r
)
69 return _reads_reg(inst
, r
, false, true);
73 reads_b_reg(uint64_t inst
, uint32_t r
)
75 return _reads_reg(inst
, r
, true, false);
79 writes_sfu(uint64_t inst
)
81 return (writes_reg(inst
, QPU_W_SFU_RECIP
) ||
82 writes_reg(inst
, QPU_W_SFU_RECIPSQRT
) ||
83 writes_reg(inst
, QPU_W_SFU_EXP
) ||
84 writes_reg(inst
, QPU_W_SFU_LOG
));
88 * Checks for the instruction restrictions from page 37 ("Summary of
89 * Instruction Restrictions").
92 vc4_qpu_validate(uint64_t *insts
, uint32_t num_inst
)
94 for (int i
= 0; i
< num_inst
; i
++) {
95 uint64_t inst
= insts
[i
];
97 if (QPU_GET_FIELD(inst
, QPU_SIG
) != QPU_SIG_PROG_END
)
100 /* "The Thread End instruction must not write to either physical
103 assert(QPU_GET_FIELD(inst
, QPU_WADDR_ADD
) >= 32);
104 assert(QPU_GET_FIELD(inst
, QPU_WADDR_MUL
) >= 32);
106 /* Two delay slots will be executed. */
107 assert(i
+ 2 <= num_inst
);
109 for (int j
= i
; j
< i
+ 2; j
++) {
110 /* "The last three instructions of any program
111 * (Thread End plus the following two delay-slot
112 * instructions) must not do varyings read, uniforms
113 * read or any kind of VPM, VDR, or VDW read or
116 assert(!writes_reg(insts
[j
], QPU_W_VPM
));
117 assert(!reads_reg(insts
[j
], QPU_R_VARY
));
118 assert(!reads_reg(insts
[j
], QPU_R_UNIF
));
119 assert(!reads_reg(insts
[j
], QPU_R_VPM
));
121 /* "The Thread End instruction and the following two
122 * delay slot instructions must not write or read
123 * address 14 in either regfile A or B."
125 assert(!writes_reg(insts
[j
], 14));
126 assert(!reads_reg(insts
[j
], 14));
130 /* "The final program instruction (the second delay slot
131 * instruction) must not do a TLB Z write."
133 assert(!writes_reg(insts
[i
+ 2], QPU_W_TLB_Z
));
136 /* "A scoreboard wait must not occur in the first two instructions of
137 * a fragment shader. This is either the explicit Wait for Scoreboard
138 * signal or an implicit wait with the first tile-buffer read or
139 * write instruction."
141 for (int i
= 0; i
< 2; i
++) {
142 uint64_t inst
= insts
[i
];
144 assert(QPU_GET_FIELD(inst
, QPU_SIG
) != QPU_SIG_COLOR_LOAD
);
145 assert(QPU_GET_FIELD(inst
, QPU_SIG
) !=
146 QPU_SIG_WAIT_FOR_SCOREBOARD
);
147 assert(!writes_reg(inst
, QPU_W_TLB_COLOR_MS
));
148 assert(!writes_reg(inst
, QPU_W_TLB_COLOR_ALL
));
149 assert(!writes_reg(inst
, QPU_W_TLB_Z
));
153 /* "If TMU_NOSWAP is written, the write must be three instructions
154 * before the first TMU write instruction. For example, if
155 * TMU_NOSWAP is written in the first shader instruction, the first
156 * TMU write cannot occur before the 4th shader instruction."
158 int last_tmu_noswap
= -10;
159 for (int i
= 0; i
< num_inst
; i
++) {
160 uint64_t inst
= insts
[i
];
162 assert((i
- last_tmu_noswap
) > 3 ||
163 (!writes_reg(inst
, QPU_W_TMU0_S
) &&
164 !writes_reg(inst
, QPU_W_TMU1_S
)));
166 if (writes_reg(inst
, QPU_W_TMU_NOSWAP
))
170 /* "An instruction must not read from a location in physical regfile A
171 * or B that was written to by the previous instruction."
173 for (int i
= 0; i
< num_inst
- 1; i
++) {
174 uint64_t inst
= insts
[i
];
175 uint32_t add_waddr
= QPU_GET_FIELD(inst
, QPU_WADDR_ADD
);
176 uint32_t mul_waddr
= QPU_GET_FIELD(inst
, QPU_WADDR_MUL
);
177 uint32_t waddr_a
, waddr_b
;
187 assert(waddr_a
>= 32 || !reads_a_reg(insts
[i
+ 1], waddr_a
));
188 assert(waddr_b
>= 32 || !reads_b_reg(insts
[i
+ 1], waddr_b
));
191 /* "After an SFU lookup instruction, accumulator r4 must not be read
192 * in the following two instructions. Any other instruction that
193 * results in r4 being written (that is, TMU read, TLB read, SFU
194 * lookup) cannot occur in the two instructions following an SFU
197 int last_sfu_inst
= -10;
198 for (int i
= 0; i
< num_inst
- 1; i
++) {
199 uint64_t inst
= insts
[i
];
201 assert(i
- last_sfu_inst
> 2 ||
202 (!writes_sfu(inst
) &&
203 !writes_reg(inst
, QPU_W_TMU0_S
) &&
204 !writes_reg(inst
, QPU_W_TMU1_S
) &&
205 QPU_GET_FIELD(inst
, QPU_SIG
) != QPU_SIG_COLOR_LOAD
));
207 if (writes_sfu(inst
))
211 int last_r5_write
= -10;
212 for (int i
= 0; i
< num_inst
- 1; i
++) {
213 uint64_t inst
= insts
[i
];
215 /* "An instruction that does a vector rotate by r5 must not
216 * immediately follow an instruction that writes to r5."
218 assert(last_r5_write
!= i
- 1 ||
219 QPU_GET_FIELD(inst
, QPU_SIG
) != QPU_SIG_SMALL_IMM
||
220 QPU_GET_FIELD(inst
, QPU_SMALL_IMM
) != 48);
223 /* "An instruction that does a vector rotate must not immediately
224 * follow an instruction that writes to the accumulator that is being
230 /* "After an instruction that does a TLB Z write, the multisample mask
231 * must not be read as an instruction input argument in the following
232 * two instruction. The TLB Z write instruction can, however, be
233 * followed immediately by a TLB color write."
235 for (int i
= 0; i
< num_inst
- 1; i
++) {
236 uint64_t inst
= insts
[i
];
237 if (writes_reg(inst
, QPU_W_TLB_Z
)) {
238 assert(!reads_a_reg(insts
[i
+ 1], QPU_R_MS_REV_FLAGS
));
239 assert(!reads_a_reg(insts
[i
+ 2], QPU_R_MS_REV_FLAGS
));
244 * "A single instruction can only perform a maximum of one of the
245 * following closely coupled peripheral accesses in a single
246 * instruction: TMU write, TMU read, TLB write, TLB read, TLB
247 * combined color read and write, SFU write, Mutex read or Semaphore
250 for (int i
= 0; i
< num_inst
- 1; i
++) {
251 uint64_t inst
= insts
[i
];
253 static const uint32_t specials
[] = {
271 for (int j
= 0; j
< ARRAY_SIZE(specials
); j
++) {
272 if (writes_reg(inst
, specials
[j
]))
276 if (reads_reg(inst
, QPU_R_MUTEX_ACQUIRE
))
279 /* XXX: semaphore, combined color read/write? */
280 switch (QPU_GET_FIELD(inst
, QPU_SIG
)) {
281 case QPU_SIG_COLOR_LOAD
:
282 case QPU_SIG_COLOR_LOAD_END
:
283 case QPU_SIG_LOAD_TMU0
:
284 case QPU_SIG_LOAD_TMU1
:
288 assert(accesses
<= 1);