src/gallium/drivers/vc4/vc4_register_allocate.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/ralloc.h"
  25 #include "util/register_allocate.h"
  26 #include "vc4_context.h"
  27 #include "vc4_qir.h"
  28 #include "vc4_qpu.h"
  29
  30 #define QPU_R(file, index) { QPU_MUX_##file, index }
  31
  32 static const struct qpu_reg vc4_regs[] = {
  33         { QPU_MUX_R0, 0},
  34         { QPU_MUX_R1, 0},
  35         { QPU_MUX_R2, 0},
  36         { QPU_MUX_R3, 0},
  37         { QPU_MUX_R4, 0},
  38         QPU_R(A, 0),
  39         QPU_R(B, 0),
  40         QPU_R(A, 1),
  41         QPU_R(B, 1),
  42         QPU_R(A, 2),
  43         QPU_R(B, 2),
  44         QPU_R(A, 3),
  45         QPU_R(B, 3),
  46         QPU_R(A, 4),
  47         QPU_R(B, 4),
  48         QPU_R(A, 5),
  49         QPU_R(B, 5),
  50         QPU_R(A, 6),
  51         QPU_R(B, 6),
  52         QPU_R(A, 7),
  53         QPU_R(B, 7),
  54         QPU_R(A, 8),
  55         QPU_R(B, 8),
  56         QPU_R(A, 9),
  57         QPU_R(B, 9),
  58         QPU_R(A, 10),
  59         QPU_R(B, 10),
  60         QPU_R(A, 11),
  61         QPU_R(B, 11),
  62         QPU_R(A, 12),
  63         QPU_R(B, 12),
  64         QPU_R(A, 13),
  65         QPU_R(B, 13),
  66         QPU_R(A, 14),
  67         QPU_R(B, 14),
  68         QPU_R(A, 15),
  69         QPU_R(B, 15),
  70         QPU_R(A, 16),
  71         QPU_R(B, 16),
  72         QPU_R(A, 17),
  73         QPU_R(B, 17),
  74         QPU_R(A, 18),
  75         QPU_R(B, 18),
  76         QPU_R(A, 19),
  77         QPU_R(B, 19),
  78         QPU_R(A, 20),
  79         QPU_R(B, 20),
  80         QPU_R(A, 21),
  81         QPU_R(B, 21),
  82         QPU_R(A, 22),
  83         QPU_R(B, 22),
  84         QPU_R(A, 23),
  85         QPU_R(B, 23),
  86         QPU_R(A, 24),
  87         QPU_R(B, 24),
  88         QPU_R(A, 25),
  89         QPU_R(B, 25),
  90         QPU_R(A, 26),
  91         QPU_R(B, 26),
  92         QPU_R(A, 27),
  93         QPU_R(B, 27),
  94         QPU_R(A, 28),
  95         QPU_R(B, 28),
  96         QPU_R(A, 29),
  97         QPU_R(B, 29),
  98         QPU_R(A, 30),
  99         QPU_R(B, 30),
 100         QPU_R(A, 31),
 101         QPU_R(B, 31),
 102 };
 103 #define ACC_INDEX     0
 104 #define AB_INDEX      (ACC_INDEX + 5)
 105
 106 static void
 107 vc4_alloc_reg_set(struct vc4_context *vc4)
 108 {
 109         assert(vc4_regs[AB_INDEX].addr == 0);
 110         assert(vc4_regs[AB_INDEX + 1].addr == 0);
 111         STATIC_ASSERT(ARRAY_SIZE(vc4_regs) == AB_INDEX + 64);
 112
 113         if (vc4->regs)
 114                 return;
 115
 116         vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true);
 117
 118         /* The physical regfiles split us into two classes, with [0] being the
 119          * whole space and [1] being the bottom half (for threaded fragment
 120          * shaders).
 121          */
 122         for (int i = 0; i < 2; i++) {
 123                 vc4->reg_class_any[i] = ra_alloc_reg_class(vc4->regs);
 124                 vc4->reg_class_a_or_b[i] = ra_alloc_reg_class(vc4->regs);
 125                 vc4->reg_class_a_or_b_or_acc[i] = ra_alloc_reg_class(vc4->regs);
 126                 vc4->reg_class_r4_or_a[i] = ra_alloc_reg_class(vc4->regs);
 127                 vc4->reg_class_a[i] = ra_alloc_reg_class(vc4->regs);
 128         }
 129         vc4->reg_class_r0_r3 = ra_alloc_reg_class(vc4->regs);
 130
 131         /* r0-r3 */
 132         for (uint32_t i = ACC_INDEX; i < ACC_INDEX + 4; i++) {
 133                 ra_class_add_reg(vc4->regs, vc4->reg_class_r0_r3, i);
 134                 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[0], i);
 135                 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[1], i);
 136         }
 137
 138         /* R4 gets a special class because it can't be written as a general
 139          * purpose register. (it's TMU_NOSWAP as a write address).
 140          */
 141         for (int i = 0; i < 2; i++) {
 142                 ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a[i],
 143                                  ACC_INDEX + 4);
 144         }
 145
 146         /* A/B */
 147         for (uint32_t i = AB_INDEX; i < AB_INDEX + 64; i ++) {
 148                 /* Reserve ra14/rb14 for spilling fixup_raddr_conflict() in
 149                  * vc4_qpu_emit.c
 150                  */
 151                 if (vc4_regs[i].addr == 14)
 152                         continue;
 153
 154                 ra_class_add_reg(vc4->regs, vc4->reg_class_any[0], i);
 155                 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b[0], i);
 156                 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[0], i);
 157
 158                 if (vc4_regs[i].addr < 16) {
 159                         ra_class_add_reg(vc4->regs, vc4->reg_class_any[1], i);
 160                         ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b[1], i);
 161                         ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[1], i);
 162                 }
 163
 164
 165                 /* A only */
 166                 if (((i - AB_INDEX) & 1) == 0) {
 167                         ra_class_add_reg(vc4->regs, vc4->reg_class_a[0], i);
 168                         ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a[0], i);
 169
 170                         if (vc4_regs[i].addr < 16) {
 171                                 ra_class_add_reg(vc4->regs,
 172                                                  vc4->reg_class_a[1], i);
 173                                 ra_class_add_reg(vc4->regs,
 174                                                  vc4->reg_class_r4_or_a[1], i);
 175                         }
 176                 }
 177         }
 178
 179         ra_set_finalize(vc4->regs, NULL);
 180 }
 181
 182 struct node_to_temp_map {
 183         uint32_t temp;
 184         uint32_t priority;
 185 };
 186
 187 static int
 188 node_to_temp_priority(const void *in_a, const void *in_b)
 189 {
 190         const struct node_to_temp_map *a = in_a;
 191         const struct node_to_temp_map *b = in_b;
 192
 193         return a->priority - b->priority;
 194 }
 195
 196 #define CLASS_BIT_A                     (1 << 0)
 197 #define CLASS_BIT_B                     (1 << 1)
 198 #define CLASS_BIT_R4                    (1 << 2)
 199 #define CLASS_BIT_R0_R3                 (1 << 4)
 200
 201 /**
 202  * Returns a mapping from QFILE_TEMP indices to struct qpu_regs.
 203  *
 204  * The return value should be freed by the caller.
 205  */
 206 struct qpu_reg *
 207 vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c)
 208 {
 209         struct node_to_temp_map map[c->num_temps];
 210         uint32_t temp_to_node[c->num_temps];
 211         uint8_t class_bits[c->num_temps];
 212         struct qpu_reg *temp_registers = calloc(c->num_temps,
 213                                                 sizeof(*temp_registers));
 214
 215         /* If things aren't ever written (undefined values), just read from
 216          * r0.
 217          */
 218         for (uint32_t i = 0; i < c->num_temps; i++)
 219                 temp_registers[i] = qpu_rn(0);
 220
 221         vc4_alloc_reg_set(vc4);
 222
 223         struct ra_graph *g = ra_alloc_interference_graph(vc4->regs,
 224                                                          c->num_temps);
 225
 226         /* Compute the live ranges so we can figure out interference. */
 227         qir_calculate_live_intervals(c);
 228
 229         for (uint32_t i = 0; i < c->num_temps; i++) {
 230                 map[i].temp = i;
 231                 map[i].priority = c->temp_end[i] - c->temp_start[i];
 232         }
 233         qsort(map, c->num_temps, sizeof(map[0]), node_to_temp_priority);
 234         for (uint32_t i = 0; i < c->num_temps; i++) {
 235                 temp_to_node[map[i].temp] = i;
 236         }
 237
 238         /* Figure out our register classes and preallocated registers.  We
 239          * start with any temp being able to be in any file, then instructions
 240          * incrementally remove bits that the temp definitely can't be in.
 241          */
 242         memset(class_bits,
 243                CLASS_BIT_A | CLASS_BIT_B | CLASS_BIT_R4 | CLASS_BIT_R0_R3,
 244                sizeof(class_bits));
 245
 246         int ip = 0;
 247         qir_for_each_inst_inorder(inst, c) {
 248                 if (qir_writes_r4(inst)) {
 249                         /* This instruction writes r4 (and optionally moves
 250                          * its result to a temp), so nothing else can be
 251                          * stored in r4 across it.
 252                          */
 253                         for (int i = 0; i < c->num_temps; i++) {
 254                                 if (c->temp_start[i] < ip && c->temp_end[i] > ip)
 255                                         class_bits[i] &= ~CLASS_BIT_R4;
 256                         }
 257                 } else {
 258                         /* R4 can't be written as a general purpose
 259                          * register. (it's TMU_NOSWAP as a write address).
 260                          */
 261                         if (inst->dst.file == QFILE_TEMP)
 262                                 class_bits[inst->dst.index] &= ~CLASS_BIT_R4;
 263                 }
 264
 265                 switch (inst->op) {
 266                 case QOP_FRAG_Z:
 267                         ra_set_node_reg(g, temp_to_node[inst->dst.index],
 268                                         AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2 + 1);
 269                         break;
 270
 271                 case QOP_FRAG_W:
 272                         ra_set_node_reg(g, temp_to_node[inst->dst.index],
 273                                         AB_INDEX + QPU_R_FRAG_PAYLOAD_ZW * 2);
 274                         break;
 275
 276                 case QOP_ROT_MUL:
 277                         assert(inst->src[0].file == QFILE_TEMP);
 278                         class_bits[inst->src[0].index] &= CLASS_BIT_R0_R3;
 279                         break;
 280
 281                 case QOP_THRSW:
 282                         /* All accumulators are invalidated across a thread
 283                          * switch.
 284                          */
 285                         for (int i = 0; i < c->num_temps; i++) {
 286                                 if (c->temp_start[i] < ip && c->temp_end[i] > ip)
 287                                         class_bits[i] &= ~(CLASS_BIT_R0_R3 |
 288                                                            CLASS_BIT_R4);
 289                         }
 290                         break;
 291
 292                 default:
 293                         break;
 294                 }
 295
 296                 if (inst->dst.pack && !qir_is_mul(inst)) {
 297                         /* The non-MUL pack flags require an A-file dst
 298                          * register.
 299                          */
 300                         class_bits[inst->dst.index] &= CLASS_BIT_A;
 301                 }
 302
 303                 /* Apply restrictions for src unpacks.  The integer unpacks
 304                  * can only be done from regfile A, while float unpacks can be
 305                  * either A or R4.
 306                  */
 307                 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
 308                         if (inst->src[i].file == QFILE_TEMP &&
 309                             inst->src[i].pack) {
 310                                 if (qir_is_float_input(inst)) {
 311                                         class_bits[inst->src[i].index] &=
 312                                                 CLASS_BIT_A | CLASS_BIT_R4;
 313                                 } else {
 314                                         class_bits[inst->src[i].index] &=
 315                                                 CLASS_BIT_A;
 316                                 }
 317                         }
 318                 }
 319
 320                 ip++;
 321         }
 322
 323         for (uint32_t i = 0; i < c->num_temps; i++) {
 324                 int node = temp_to_node[i];
 325
 326                 switch (class_bits[i]) {
 327                 case CLASS_BIT_A | CLASS_BIT_B | CLASS_BIT_R4 | CLASS_BIT_R0_R3:
 328                         ra_set_node_class(g, node,
 329                                           vc4->reg_class_any[c->fs_threaded]);
 330                         break;
 331                 case CLASS_BIT_A | CLASS_BIT_B:
 332                         ra_set_node_class(g, node,
 333                                           vc4->reg_class_a_or_b[c->fs_threaded]);
 334                         break;
 335                 case CLASS_BIT_A | CLASS_BIT_B | CLASS_BIT_R0_R3:
 336                         ra_set_node_class(g, node,
 337                                           vc4->reg_class_a_or_b_or_acc[c->fs_threaded]);
 338                         break;
 339                 case CLASS_BIT_A | CLASS_BIT_R4:
 340                         ra_set_node_class(g, node,
 341                                           vc4->reg_class_r4_or_a[c->fs_threaded]);
 342                         break;
 343                 case CLASS_BIT_A:
 344                         ra_set_node_class(g, node,
 345                                           vc4->reg_class_a[c->fs_threaded]);
 346                         break;
 347                 case CLASS_BIT_R0_R3:
 348                         ra_set_node_class(g, node, vc4->reg_class_r0_r3);
 349                         break;
 350
 351                 default:
 352                         /* DDX/DDY used across thread switched might get us
 353                          * here.
 354                          */
 355                         if (c->fs_threaded) {
 356                                 c->failed = true;
 357                                 return NULL;
 358                         }
 359
 360                         fprintf(stderr, "temp %d: bad class bits: 0x%x\n",
 361                                 i, class_bits[i]);
 362                         abort();
 363                         break;
 364                 }
 365         }
 366
 367         for (uint32_t i = 0; i < c->num_temps; i++) {
 368                 for (uint32_t j = i + 1; j < c->num_temps; j++) {
 369                         if (!(c->temp_start[i] >= c->temp_end[j] ||
 370                               c->temp_start[j] >= c->temp_end[i])) {
 371                                 ra_add_node_interference(g,
 372                                                          temp_to_node[i],
 373                                                          temp_to_node[j]);
 374                         }
 375                 }
 376         }
 377
 378         bool ok = ra_allocate(g);
 379         if (!ok) {
 380                 if (!c->fs_threaded) {
 381                         fprintf(stderr, "Failed to register allocate:\n");
 382                         qir_dump(c);
 383                 }
 384
 385                 c->failed = true;
 386                 return NULL;
 387         }
 388
 389         for (uint32_t i = 0; i < c->num_temps; i++) {
 390                 temp_registers[i] = vc4_regs[ra_get_node_reg(g, temp_to_node[i])];
 391
 392                 /* If the value's never used, just write to the NOP register
 393                  * for clarity in debug output.
 394                  */
 395                 if (c->temp_start[i] == c->temp_end[i])
 396                         temp_registers[i] = qpu_ra(QPU_W_NOP);
 397         }
 398
 399         ralloc_free(g);
 400
 401         return temp_registers;
 402 }