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broadcom/vc4: Scissor blits performed using the rendering engine.
[mesa.git] / src / gallium / drivers / vc4 / vc4_resource.c
1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/u_blit.h"
26 #include "util/u_memory.h"
27 #include "util/u_format.h"
28 #include "util/u_inlines.h"
29 #include "util/u_surface.h"
30 #include "util/u_upload_mgr.h"
31
32 #include "drm_fourcc.h"
33 #include "vc4_drm.h"
34 #include "vc4_screen.h"
35 #include "vc4_context.h"
36 #include "vc4_resource.h"
37 #include "vc4_tiling.h"
38
39 #ifndef DRM_FORMAT_MOD_INVALID
40 #define DRM_FORMAT_MOD_INVALID ((1ULL << 56) - 1)
41 #endif
42
43 static bool
44 vc4_resource_bo_alloc(struct vc4_resource *rsc)
45 {
46 struct pipe_resource *prsc = &rsc->base;
47 struct pipe_screen *pscreen = prsc->screen;
48 struct vc4_bo *bo;
49
50 if (vc4_debug & VC4_DEBUG_SURFACE) {
51 fprintf(stderr, "alloc %p: size %d + offset %d -> %d\n",
52 rsc,
53 rsc->slices[0].size,
54 rsc->slices[0].offset,
55 rsc->slices[0].offset +
56 rsc->slices[0].size +
57 rsc->cube_map_stride * (prsc->array_size - 1));
58 }
59
60 bo = vc4_bo_alloc(vc4_screen(pscreen),
61 rsc->slices[0].offset +
62 rsc->slices[0].size +
63 rsc->cube_map_stride * (prsc->array_size - 1),
64 "resource");
65 if (bo) {
66 vc4_bo_unreference(&rsc->bo);
67 rsc->bo = bo;
68 return true;
69 } else {
70 return false;
71 }
72 }
73
74 static void
75 vc4_resource_transfer_unmap(struct pipe_context *pctx,
76 struct pipe_transfer *ptrans)
77 {
78 struct vc4_context *vc4 = vc4_context(pctx);
79 struct vc4_transfer *trans = vc4_transfer(ptrans);
80
81 if (trans->map) {
82 struct vc4_resource *rsc;
83 struct vc4_resource_slice *slice;
84 if (trans->ss_resource) {
85 rsc = vc4_resource(trans->ss_resource);
86 slice = &rsc->slices[0];
87 } else {
88 rsc = vc4_resource(ptrans->resource);
89 slice = &rsc->slices[ptrans->level];
90 }
91
92 if (ptrans->usage & PIPE_TRANSFER_WRITE) {
93 vc4_store_tiled_image(rsc->bo->map + slice->offset +
94 ptrans->box.z * rsc->cube_map_stride,
95 slice->stride,
96 trans->map, ptrans->stride,
97 slice->tiling, rsc->cpp,
98 &ptrans->box);
99 }
100 free(trans->map);
101 }
102
103 if (trans->ss_resource && (ptrans->usage & PIPE_TRANSFER_WRITE)) {
104 struct pipe_blit_info blit;
105 memset(&blit, 0, sizeof(blit));
106
107 blit.src.resource = trans->ss_resource;
108 blit.src.format = trans->ss_resource->format;
109 blit.src.box.width = trans->ss_box.width;
110 blit.src.box.height = trans->ss_box.height;
111 blit.src.box.depth = 1;
112
113 blit.dst.resource = ptrans->resource;
114 blit.dst.format = ptrans->resource->format;
115 blit.dst.level = ptrans->level;
116 blit.dst.box = trans->ss_box;
117
118 blit.mask = util_format_get_mask(ptrans->resource->format);
119 blit.filter = PIPE_TEX_FILTER_NEAREST;
120
121 pctx->blit(pctx, &blit);
122
123 pipe_resource_reference(&trans->ss_resource, NULL);
124 }
125
126 pipe_resource_reference(&ptrans->resource, NULL);
127 slab_free(&vc4->transfer_pool, ptrans);
128 }
129
130 static struct pipe_resource *
131 vc4_get_temp_resource(struct pipe_context *pctx,
132 struct pipe_resource *prsc,
133 const struct pipe_box *box)
134 {
135 struct pipe_resource temp_setup;
136
137 memset(&temp_setup, 0, sizeof(temp_setup));
138 temp_setup.target = prsc->target;
139 temp_setup.format = prsc->format;
140 temp_setup.width0 = box->width;
141 temp_setup.height0 = box->height;
142 temp_setup.depth0 = 1;
143 temp_setup.array_size = 1;
144
145 return pctx->screen->resource_create(pctx->screen, &temp_setup);
146 }
147
148 static void *
149 vc4_resource_transfer_map(struct pipe_context *pctx,
150 struct pipe_resource *prsc,
151 unsigned level, unsigned usage,
152 const struct pipe_box *box,
153 struct pipe_transfer **pptrans)
154 {
155 struct vc4_context *vc4 = vc4_context(pctx);
156 struct vc4_resource *rsc = vc4_resource(prsc);
157 struct vc4_transfer *trans;
158 struct pipe_transfer *ptrans;
159 enum pipe_format format = prsc->format;
160 char *buf;
161
162 /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is
163 * being mapped.
164 */
165 if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
166 !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
167 !(prsc->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) &&
168 prsc->last_level == 0 &&
169 prsc->width0 == box->width &&
170 prsc->height0 == box->height &&
171 prsc->depth0 == box->depth &&
172 prsc->array_size == 1 &&
173 rsc->bo->private) {
174 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
175 }
176
177 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
178 if (vc4_resource_bo_alloc(rsc)) {
179 /* If it might be bound as one of our vertex buffers,
180 * make sure we re-emit vertex buffer state.
181 */
182 if (prsc->bind & PIPE_BIND_VERTEX_BUFFER)
183 vc4->dirty |= VC4_DIRTY_VTXBUF;
184 } else {
185 /* If we failed to reallocate, flush users so that we
186 * don't violate any syncing requirements.
187 */
188 vc4_flush_jobs_reading_resource(vc4, prsc);
189 }
190 } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
191 /* If we're writing and the buffer is being used by the CL, we
192 * have to flush the CL first. If we're only reading, we need
193 * to flush if the CL has written our buffer.
194 */
195 if (usage & PIPE_TRANSFER_WRITE)
196 vc4_flush_jobs_reading_resource(vc4, prsc);
197 else
198 vc4_flush_jobs_writing_resource(vc4, prsc);
199 }
200
201 if (usage & PIPE_TRANSFER_WRITE) {
202 rsc->writes++;
203 rsc->initialized_buffers = ~0;
204 }
205
206 trans = slab_alloc(&vc4->transfer_pool);
207 if (!trans)
208 return NULL;
209
210 /* XXX: Handle DONTBLOCK, DISCARD_RANGE, PERSISTENT, COHERENT. */
211
212 /* slab_alloc_st() doesn't zero: */
213 memset(trans, 0, sizeof(*trans));
214 ptrans = &trans->base;
215
216 pipe_resource_reference(&ptrans->resource, prsc);
217 ptrans->level = level;
218 ptrans->usage = usage;
219 ptrans->box = *box;
220
221 /* If the resource is multisampled, we need to resolve to single
222 * sample. This seems like it should be handled at a higher layer.
223 */
224 if (prsc->nr_samples > 1) {
225 trans->ss_resource = vc4_get_temp_resource(pctx, prsc, box);
226 if (!trans->ss_resource)
227 goto fail;
228 assert(!trans->ss_resource->nr_samples);
229
230 /* The ptrans->box gets modified for tile alignment, so save
231 * the original box for unmap time.
232 */
233 trans->ss_box = *box;
234
235 if (usage & PIPE_TRANSFER_READ) {
236 struct pipe_blit_info blit;
237 memset(&blit, 0, sizeof(blit));
238
239 blit.src.resource = ptrans->resource;
240 blit.src.format = ptrans->resource->format;
241 blit.src.level = ptrans->level;
242 blit.src.box = trans->ss_box;
243
244 blit.dst.resource = trans->ss_resource;
245 blit.dst.format = trans->ss_resource->format;
246 blit.dst.box.width = trans->ss_box.width;
247 blit.dst.box.height = trans->ss_box.height;
248 blit.dst.box.depth = 1;
249
250 blit.mask = util_format_get_mask(prsc->format);
251 blit.filter = PIPE_TEX_FILTER_NEAREST;
252
253 pctx->blit(pctx, &blit);
254 vc4_flush_jobs_writing_resource(vc4, blit.dst.resource);
255 }
256
257 /* The rest of the mapping process should use our temporary. */
258 prsc = trans->ss_resource;
259 rsc = vc4_resource(prsc);
260 ptrans->box.x = 0;
261 ptrans->box.y = 0;
262 ptrans->box.z = 0;
263 }
264
265 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
266 buf = vc4_bo_map_unsynchronized(rsc->bo);
267 else
268 buf = vc4_bo_map(rsc->bo);
269 if (!buf) {
270 fprintf(stderr, "Failed to map bo\n");
271 goto fail;
272 }
273
274 *pptrans = ptrans;
275
276 struct vc4_resource_slice *slice = &rsc->slices[level];
277 if (rsc->tiled) {
278 uint32_t utile_w = vc4_utile_width(rsc->cpp);
279 uint32_t utile_h = vc4_utile_height(rsc->cpp);
280
281 /* No direct mappings of tiled, since we need to manually
282 * tile/untile.
283 */
284 if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
285 return NULL;
286
287 if (format == PIPE_FORMAT_ETC1_RGB8) {
288 /* ETC1 is arranged as 64-bit blocks, where each block
289 * is 4x4 pixels. Texture tiling operates on the
290 * 64-bit block the way it would an uncompressed
291 * pixels.
292 */
293 assert(!(ptrans->box.x & 3));
294 assert(!(ptrans->box.y & 3));
295 ptrans->box.x >>= 2;
296 ptrans->box.y >>= 2;
297 ptrans->box.width = (ptrans->box.width + 3) >> 2;
298 ptrans->box.height = (ptrans->box.height + 3) >> 2;
299 }
300
301 /* We need to align the box to utile boundaries, since that's
302 * what load/store operates on. This may cause us to need to
303 * read out the original contents in that border area. Right
304 * now we just read out the entire contents, including the
305 * middle area that will just get overwritten.
306 */
307 uint32_t box_start_x = ptrans->box.x & (utile_w - 1);
308 uint32_t box_start_y = ptrans->box.y & (utile_h - 1);
309 bool needs_load = (usage & PIPE_TRANSFER_READ) != 0;
310
311 if (box_start_x) {
312 ptrans->box.width += box_start_x;
313 ptrans->box.x -= box_start_x;
314 needs_load = true;
315 }
316 if (box_start_y) {
317 ptrans->box.height += box_start_y;
318 ptrans->box.y -= box_start_y;
319 needs_load = true;
320 }
321 if (ptrans->box.width & (utile_w - 1)) {
322 /* We only need to force a load if our border region
323 * we're extending into is actually part of the
324 * texture.
325 */
326 uint32_t slice_width = u_minify(prsc->width0, level);
327 if (ptrans->box.x + ptrans->box.width != slice_width)
328 needs_load = true;
329 ptrans->box.width = align(ptrans->box.width, utile_w);
330 }
331 if (ptrans->box.height & (utile_h - 1)) {
332 uint32_t slice_height = u_minify(prsc->height0, level);
333 if (ptrans->box.y + ptrans->box.height != slice_height)
334 needs_load = true;
335 ptrans->box.height = align(ptrans->box.height, utile_h);
336 }
337
338 ptrans->stride = ptrans->box.width * rsc->cpp;
339 ptrans->layer_stride = ptrans->stride * ptrans->box.height;
340
341 trans->map = malloc(ptrans->layer_stride * ptrans->box.depth);
342
343 if (needs_load) {
344 vc4_load_tiled_image(trans->map, ptrans->stride,
345 buf + slice->offset +
346 ptrans->box.z * rsc->cube_map_stride,
347 slice->stride,
348 slice->tiling, rsc->cpp,
349 &ptrans->box);
350 }
351 return (trans->map +
352 box_start_x * rsc->cpp +
353 box_start_y * ptrans->stride);
354 } else {
355 ptrans->stride = slice->stride;
356 ptrans->layer_stride = ptrans->stride;
357
358 return buf + slice->offset +
359 ptrans->box.y / util_format_get_blockheight(format) * ptrans->stride +
360 ptrans->box.x / util_format_get_blockwidth(format) * rsc->cpp +
361 ptrans->box.z * rsc->cube_map_stride;
362 }
363
364
365 fail:
366 vc4_resource_transfer_unmap(pctx, ptrans);
367 return NULL;
368 }
369
370 static void
371 vc4_resource_destroy(struct pipe_screen *pscreen,
372 struct pipe_resource *prsc)
373 {
374 struct vc4_screen *screen = vc4_screen(pscreen);
375 struct vc4_resource *rsc = vc4_resource(prsc);
376 pipe_resource_reference(&rsc->shadow_parent, NULL);
377 vc4_bo_unreference(&rsc->bo);
378
379 if (rsc->scanout)
380 renderonly_scanout_destroy(rsc->scanout, screen->ro);
381
382 free(rsc);
383 }
384
385 static boolean
386 vc4_resource_get_handle(struct pipe_screen *pscreen,
387 struct pipe_context *pctx,
388 struct pipe_resource *prsc,
389 struct winsys_handle *whandle,
390 unsigned usage)
391 {
392 struct vc4_screen *screen = vc4_screen(pscreen);
393 struct vc4_resource *rsc = vc4_resource(prsc);
394
395 whandle->stride = rsc->slices[0].stride;
396 whandle->offset = 0;
397
398 /* If we're passing some reference to our BO out to some other part of
399 * the system, then we can't do any optimizations about only us being
400 * the ones seeing it (like BO caching or shadow update avoidance).
401 */
402 rsc->bo->private = false;
403
404 if (rsc->tiled)
405 whandle->modifier = DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
406 else
407 whandle->modifier = DRM_FORMAT_MOD_LINEAR;
408
409 switch (whandle->type) {
410 case DRM_API_HANDLE_TYPE_SHARED:
411 if (screen->ro) {
412 /* This could probably be supported, assuming that a
413 * control node was used for pl111.
414 */
415 fprintf(stderr, "flink unsupported with pl111\n");
416 return FALSE;
417 }
418
419 return vc4_bo_flink(rsc->bo, &whandle->handle);
420 case DRM_API_HANDLE_TYPE_KMS:
421 if (screen->ro && renderonly_get_handle(rsc->scanout, whandle))
422 return TRUE;
423 whandle->handle = rsc->bo->handle;
424 return TRUE;
425 case DRM_API_HANDLE_TYPE_FD:
426 /* FDs are cross-device, so we can export directly from vc4.
427 */
428 whandle->handle = vc4_bo_get_dmabuf(rsc->bo);
429 return whandle->handle != -1;
430 }
431
432 return FALSE;
433 }
434
435 static void
436 vc4_setup_slices(struct vc4_resource *rsc, const char *caller)
437 {
438 struct pipe_resource *prsc = &rsc->base;
439 uint32_t width = prsc->width0;
440 uint32_t height = prsc->height0;
441 if (prsc->format == PIPE_FORMAT_ETC1_RGB8) {
442 width = (width + 3) >> 2;
443 height = (height + 3) >> 2;
444 }
445
446 uint32_t pot_width = util_next_power_of_two(width);
447 uint32_t pot_height = util_next_power_of_two(height);
448 uint32_t offset = 0;
449 uint32_t utile_w = vc4_utile_width(rsc->cpp);
450 uint32_t utile_h = vc4_utile_height(rsc->cpp);
451
452 for (int i = prsc->last_level; i >= 0; i--) {
453 struct vc4_resource_slice *slice = &rsc->slices[i];
454
455 uint32_t level_width, level_height;
456 if (i == 0) {
457 level_width = width;
458 level_height = height;
459 } else {
460 level_width = u_minify(pot_width, i);
461 level_height = u_minify(pot_height, i);
462 }
463
464 if (!rsc->tiled) {
465 slice->tiling = VC4_TILING_FORMAT_LINEAR;
466 if (prsc->nr_samples > 1) {
467 /* MSAA (4x) surfaces are stored as raw tile buffer contents. */
468 level_width = align(level_width, 32);
469 level_height = align(level_height, 32);
470 } else {
471 level_width = align(level_width, utile_w);
472 }
473 } else {
474 if (vc4_size_is_lt(level_width, level_height,
475 rsc->cpp)) {
476 slice->tiling = VC4_TILING_FORMAT_LT;
477 level_width = align(level_width, utile_w);
478 level_height = align(level_height, utile_h);
479 } else {
480 slice->tiling = VC4_TILING_FORMAT_T;
481 level_width = align(level_width,
482 4 * 2 * utile_w);
483 level_height = align(level_height,
484 4 * 2 * utile_h);
485 }
486 }
487
488 slice->offset = offset;
489 slice->stride = (level_width * rsc->cpp *
490 MAX2(prsc->nr_samples, 1));
491 slice->size = level_height * slice->stride;
492
493 offset += slice->size;
494
495 if (vc4_debug & VC4_DEBUG_SURFACE) {
496 static const char tiling_chars[] = {
497 [VC4_TILING_FORMAT_LINEAR] = 'R',
498 [VC4_TILING_FORMAT_LT] = 'L',
499 [VC4_TILING_FORMAT_T] = 'T'
500 };
501 fprintf(stderr,
502 "rsc %s %p (format %s: vc4 %d), %dx%d: "
503 "level %d (%c) -> %dx%d, stride %d@0x%08x\n",
504 caller, rsc,
505 util_format_short_name(prsc->format),
506 rsc->vc4_format,
507 prsc->width0, prsc->height0,
508 i, tiling_chars[slice->tiling],
509 level_width, level_height,
510 slice->stride, slice->offset);
511 }
512 }
513
514 /* The texture base pointer that has to point to level 0 doesn't have
515 * intra-page bits, so we have to align it, and thus shift up all the
516 * smaller slices.
517 */
518 uint32_t page_align_offset = (align(rsc->slices[0].offset, 4096) -
519 rsc->slices[0].offset);
520 if (page_align_offset) {
521 for (int i = 0; i <= prsc->last_level; i++)
522 rsc->slices[i].offset += page_align_offset;
523 }
524
525 /* Cube map faces appear as whole miptrees at a page-aligned offset
526 * from the first face's miptree.
527 */
528 if (prsc->target == PIPE_TEXTURE_CUBE) {
529 rsc->cube_map_stride = align(rsc->slices[0].offset +
530 rsc->slices[0].size, 4096);
531 }
532 }
533
534 static struct vc4_resource *
535 vc4_resource_setup(struct pipe_screen *pscreen,
536 const struct pipe_resource *tmpl)
537 {
538 struct vc4_resource *rsc = CALLOC_STRUCT(vc4_resource);
539 if (!rsc)
540 return NULL;
541 struct pipe_resource *prsc = &rsc->base;
542
543 *prsc = *tmpl;
544
545 pipe_reference_init(&prsc->reference, 1);
546 prsc->screen = pscreen;
547
548 if (prsc->nr_samples <= 1)
549 rsc->cpp = util_format_get_blocksize(tmpl->format);
550 else
551 rsc->cpp = sizeof(uint32_t);
552
553 assert(rsc->cpp);
554
555 return rsc;
556 }
557
558 static enum vc4_texture_data_type
559 get_resource_texture_format(struct pipe_resource *prsc)
560 {
561 struct vc4_resource *rsc = vc4_resource(prsc);
562 uint8_t format = vc4_get_tex_format(prsc->format);
563
564 if (!rsc->tiled) {
565 if (prsc->nr_samples > 1) {
566 return ~0;
567 } else {
568 assert(format == VC4_TEXTURE_TYPE_RGBA8888);
569 return VC4_TEXTURE_TYPE_RGBA32R;
570 }
571 }
572
573 return format;
574 }
575
576 static bool
577 find_modifier(uint64_t needle, const uint64_t *haystack, int count)
578 {
579 int i;
580
581 for (i = 0; i < count; i++) {
582 if (haystack[i] == needle)
583 return true;
584 }
585
586 return false;
587 }
588
589 static struct pipe_resource *
590 vc4_resource_create_with_modifiers(struct pipe_screen *pscreen,
591 const struct pipe_resource *tmpl,
592 const uint64_t *modifiers,
593 int count)
594 {
595 struct vc4_screen *screen = vc4_screen(pscreen);
596 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
597 struct pipe_resource *prsc = &rsc->base;
598 bool linear_ok = find_modifier(DRM_FORMAT_MOD_LINEAR, modifiers, count);
599 /* Use a tiled layout if we can, for better 3D performance. */
600 bool should_tile = true;
601
602 /* VBOs/PBOs are untiled (and 1 height). */
603 if (tmpl->target == PIPE_BUFFER)
604 should_tile = false;
605
606 /* MSAA buffers are linear. */
607 if (tmpl->nr_samples > 1)
608 should_tile = false;
609
610 /* No tiling when we're sharing with another device (pl111). */
611 if (screen->ro && (tmpl->bind & PIPE_BIND_SCANOUT))
612 should_tile = false;
613
614 /* Cursors are always linear, and the user can request linear as well.
615 */
616 if (tmpl->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR))
617 should_tile = false;
618
619 /* No shared objects with LT format -- the kernel only has T-format
620 * metadata. LT objects are small enough it's not worth the trouble to
621 * give them metadata to tile.
622 */
623 if ((tmpl->bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT)) &&
624 vc4_size_is_lt(prsc->width0, prsc->height0, rsc->cpp))
625 should_tile = false;
626
627 /* If we're sharing or scanning out, we need the ioctl present to
628 * inform the kernel or the other side.
629 */
630 if ((tmpl->bind & (PIPE_BIND_SHARED |
631 PIPE_BIND_SCANOUT)) && !screen->has_tiling_ioctl)
632 should_tile = false;
633
634 /* No user-specified modifier; determine our own. */
635 if (count == 1 && modifiers[0] == DRM_FORMAT_MOD_INVALID) {
636 linear_ok = true;
637 rsc->tiled = should_tile;
638 } else if (should_tile &&
639 find_modifier(DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
640 modifiers, count)) {
641 rsc->tiled = true;
642 } else if (linear_ok) {
643 rsc->tiled = false;
644 } else {
645 fprintf(stderr, "Unsupported modifier requested\n");
646 return NULL;
647 }
648
649 if (tmpl->target != PIPE_BUFFER)
650 rsc->vc4_format = get_resource_texture_format(prsc);
651
652 vc4_setup_slices(rsc, "create");
653 if (!vc4_resource_bo_alloc(rsc))
654 goto fail;
655
656 if (screen->has_tiling_ioctl) {
657 uint64_t modifier;
658 if (rsc->tiled)
659 modifier = DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED;
660 else
661 modifier = DRM_FORMAT_MOD_LINEAR;
662 struct drm_vc4_set_tiling set_tiling = {
663 .handle = rsc->bo->handle,
664 .modifier = modifier,
665 };
666 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_SET_TILING,
667 &set_tiling);
668 if (ret != 0)
669 goto fail;
670 }
671
672 if (screen->ro && tmpl->bind & PIPE_BIND_SCANOUT) {
673 rsc->scanout =
674 renderonly_scanout_for_resource(prsc, screen->ro, NULL);
675 if (!rsc->scanout)
676 goto fail;
677 }
678
679 return prsc;
680 fail:
681 vc4_resource_destroy(pscreen, prsc);
682 return NULL;
683 }
684
685 struct pipe_resource *
686 vc4_resource_create(struct pipe_screen *pscreen,
687 const struct pipe_resource *tmpl)
688 {
689 const uint64_t mod = DRM_FORMAT_MOD_INVALID;
690 return vc4_resource_create_with_modifiers(pscreen, tmpl, &mod, 1);
691 }
692
693 static struct pipe_resource *
694 vc4_resource_from_handle(struct pipe_screen *pscreen,
695 const struct pipe_resource *tmpl,
696 struct winsys_handle *whandle,
697 unsigned usage)
698 {
699 struct vc4_screen *screen = vc4_screen(pscreen);
700 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
701 struct pipe_resource *prsc = &rsc->base;
702 struct vc4_resource_slice *slice = &rsc->slices[0];
703
704 if (!rsc)
705 return NULL;
706
707 if (whandle->offset != 0) {
708 fprintf(stderr,
709 "Attempt to import unsupported winsys offset %u\n",
710 whandle->offset);
711 return NULL;
712 }
713
714 switch (whandle->type) {
715 case DRM_API_HANDLE_TYPE_SHARED:
716 rsc->bo = vc4_bo_open_name(screen,
717 whandle->handle, whandle->stride);
718 break;
719 case DRM_API_HANDLE_TYPE_FD:
720 rsc->bo = vc4_bo_open_dmabuf(screen,
721 whandle->handle, whandle->stride);
722 break;
723 default:
724 fprintf(stderr,
725 "Attempt to import unsupported handle type %d\n",
726 whandle->type);
727 }
728
729 if (!rsc->bo)
730 goto fail;
731
732 struct drm_vc4_get_tiling get_tiling = {
733 .handle = rsc->bo->handle,
734 };
735 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_TILING, &get_tiling);
736
737 if (ret != 0) {
738 whandle->modifier = DRM_FORMAT_MOD_LINEAR;
739 } else if (whandle->modifier == DRM_FORMAT_MOD_INVALID) {
740 whandle->modifier = get_tiling.modifier;
741 } else if (whandle->modifier != get_tiling.modifier) {
742 fprintf(stderr,
743 "Modifier 0x%llx vs. tiling (0x%llx) mismatch\n",
744 (long long)whandle->modifier, get_tiling.modifier);
745 goto fail;
746 }
747
748 switch (whandle->modifier) {
749 case DRM_FORMAT_MOD_LINEAR:
750 rsc->tiled = false;
751 break;
752 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
753 rsc->tiled = true;
754 break;
755 default:
756 fprintf(stderr,
757 "Attempt to import unsupported modifier 0x%llx\n",
758 (long long)whandle->modifier);
759 goto fail;
760 }
761
762 rsc->vc4_format = get_resource_texture_format(prsc);
763 vc4_setup_slices(rsc, "import");
764
765 if (screen->ro) {
766 /* Make sure that renderonly has a handle to our buffer in the
767 * display's fd, so that a later renderonly_get_handle()
768 * returns correct handles or GEM names.
769 */
770 rsc->scanout =
771 renderonly_create_gpu_import_for_resource(prsc,
772 screen->ro,
773 NULL);
774 if (!rsc->scanout)
775 goto fail;
776 }
777
778 if (whandle->stride != slice->stride) {
779 static bool warned = false;
780 if (!warned) {
781 warned = true;
782 fprintf(stderr,
783 "Attempting to import %dx%d %s with "
784 "unsupported stride %d instead of %d\n",
785 prsc->width0, prsc->height0,
786 util_format_short_name(prsc->format),
787 whandle->stride,
788 slice->stride);
789 }
790 goto fail;
791 }
792
793 return prsc;
794
795 fail:
796 vc4_resource_destroy(pscreen, prsc);
797 return NULL;
798 }
799
800 static struct pipe_surface *
801 vc4_create_surface(struct pipe_context *pctx,
802 struct pipe_resource *ptex,
803 const struct pipe_surface *surf_tmpl)
804 {
805 struct vc4_surface *surface = CALLOC_STRUCT(vc4_surface);
806 struct vc4_resource *rsc = vc4_resource(ptex);
807
808 if (!surface)
809 return NULL;
810
811 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
812
813 struct pipe_surface *psurf = &surface->base;
814 unsigned level = surf_tmpl->u.tex.level;
815
816 pipe_reference_init(&psurf->reference, 1);
817 pipe_resource_reference(&psurf->texture, ptex);
818
819 psurf->context = pctx;
820 psurf->format = surf_tmpl->format;
821 psurf->width = u_minify(ptex->width0, level);
822 psurf->height = u_minify(ptex->height0, level);
823 psurf->u.tex.level = level;
824 psurf->u.tex.first_layer = surf_tmpl->u.tex.first_layer;
825 psurf->u.tex.last_layer = surf_tmpl->u.tex.last_layer;
826 surface->offset = (rsc->slices[level].offset +
827 psurf->u.tex.first_layer * rsc->cube_map_stride);
828 surface->tiling = rsc->slices[level].tiling;
829
830 return &surface->base;
831 }
832
833 static void
834 vc4_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
835 {
836 pipe_resource_reference(&psurf->texture, NULL);
837 FREE(psurf);
838 }
839
840 static void
841 vc4_dump_surface_non_msaa(struct pipe_surface *psurf)
842 {
843 struct pipe_resource *prsc = psurf->texture;
844 struct vc4_resource *rsc = vc4_resource(prsc);
845 uint32_t *map = vc4_bo_map(rsc->bo);
846 uint32_t stride = rsc->slices[0].stride / 4;
847 uint32_t width = psurf->width;
848 uint32_t height = psurf->height;
849 uint32_t chunk_w = width / 79;
850 uint32_t chunk_h = height / 40;
851 uint32_t found_colors[10];
852 uint32_t num_found_colors = 0;
853
854 if (rsc->vc4_format != VC4_TEXTURE_TYPE_RGBA32R) {
855 fprintf(stderr, "%s: Unsupported format %s\n",
856 __func__, util_format_short_name(psurf->format));
857 return;
858 }
859
860 for (int by = 0; by < height; by += chunk_h) {
861 for (int bx = 0; bx < width; bx += chunk_w) {
862 int all_found_color = -1; /* nothing found */
863
864 for (int y = by; y < MIN2(height, by + chunk_h); y++) {
865 for (int x = bx; x < MIN2(width, bx + chunk_w); x++) {
866 uint32_t pix = map[y * stride + x];
867
868 int i;
869 for (i = 0; i < num_found_colors; i++) {
870 if (pix == found_colors[i])
871 break;
872 }
873 if (i == num_found_colors &&
874 num_found_colors <
875 ARRAY_SIZE(found_colors)) {
876 found_colors[num_found_colors++] = pix;
877 }
878
879 if (i < num_found_colors) {
880 if (all_found_color == -1)
881 all_found_color = i;
882 else if (i != all_found_color)
883 all_found_color = ARRAY_SIZE(found_colors);
884 }
885 }
886 }
887 /* If all pixels for this chunk have a consistent
888 * value, then print a character for it. Either a
889 * fixed name (particularly common for piglit tests),
890 * or a runtime-generated number.
891 */
892 if (all_found_color >= 0 &&
893 all_found_color < ARRAY_SIZE(found_colors)) {
894 static const struct {
895 uint32_t val;
896 const char *c;
897 } named_colors[] = {
898 { 0xff000000, "█" },
899 { 0x00000000, "█" },
900 { 0xffff0000, "r" },
901 { 0xff00ff00, "g" },
902 { 0xff0000ff, "b" },
903 { 0xffffffff, "w" },
904 };
905 int i;
906 for (i = 0; i < ARRAY_SIZE(named_colors); i++) {
907 if (named_colors[i].val ==
908 found_colors[all_found_color]) {
909 fprintf(stderr, "%s",
910 named_colors[i].c);
911 break;
912 }
913 }
914 /* For unnamed colors, print a number and the
915 * numbers will have values printed at the
916 * end.
917 */
918 if (i == ARRAY_SIZE(named_colors)) {
919 fprintf(stderr, "%c",
920 '0' + all_found_color);
921 }
922 } else {
923 /* If there's no consistent color, print this.
924 */
925 fprintf(stderr, ".");
926 }
927 }
928 fprintf(stderr, "\n");
929 }
930
931 for (int i = 0; i < num_found_colors; i++) {
932 fprintf(stderr, "color %d: 0x%08x\n", i, found_colors[i]);
933 }
934 }
935
936 static uint32_t
937 vc4_surface_msaa_get_sample(struct pipe_surface *psurf,
938 uint32_t x, uint32_t y, uint32_t sample)
939 {
940 struct pipe_resource *prsc = psurf->texture;
941 struct vc4_resource *rsc = vc4_resource(prsc);
942 uint32_t tile_w = 32, tile_h = 32;
943 uint32_t tiles_w = DIV_ROUND_UP(psurf->width, 32);
944
945 uint32_t tile_x = x / tile_w;
946 uint32_t tile_y = y / tile_h;
947 uint32_t *tile = (vc4_bo_map(rsc->bo) +
948 VC4_TILE_BUFFER_SIZE * (tile_y * tiles_w + tile_x));
949 uint32_t subtile_x = x % tile_w;
950 uint32_t subtile_y = y % tile_h;
951
952 uint32_t quad_samples = VC4_MAX_SAMPLES * 4;
953 uint32_t tile_stride = quad_samples * tile_w / 2;
954
955 return *((uint32_t *)tile +
956 (subtile_y >> 1) * tile_stride +
957 (subtile_x >> 1) * quad_samples +
958 ((subtile_y & 1) << 1) +
959 (subtile_x & 1) +
960 sample);
961 }
962
963 static void
964 vc4_dump_surface_msaa_char(struct pipe_surface *psurf,
965 uint32_t start_x, uint32_t start_y,
966 uint32_t w, uint32_t h)
967 {
968 bool all_same_color = true;
969 uint32_t all_pix = 0;
970
971 for (int y = start_y; y < start_y + h; y++) {
972 for (int x = start_x; x < start_x + w; x++) {
973 for (int s = 0; s < VC4_MAX_SAMPLES; s++) {
974 uint32_t pix = vc4_surface_msaa_get_sample(psurf,
975 x, y,
976 s);
977 if (x == start_x && y == start_y)
978 all_pix = pix;
979 else if (all_pix != pix)
980 all_same_color = false;
981 }
982 }
983 }
984 if (all_same_color) {
985 static const struct {
986 uint32_t val;
987 const char *c;
988 } named_colors[] = {
989 { 0xff000000, "█" },
990 { 0x00000000, "█" },
991 { 0xffff0000, "r" },
992 { 0xff00ff00, "g" },
993 { 0xff0000ff, "b" },
994 { 0xffffffff, "w" },
995 };
996 int i;
997 for (i = 0; i < ARRAY_SIZE(named_colors); i++) {
998 if (named_colors[i].val == all_pix) {
999 fprintf(stderr, "%s",
1000 named_colors[i].c);
1001 return;
1002 }
1003 }
1004 fprintf(stderr, "x");
1005 } else {
1006 fprintf(stderr, ".");
1007 }
1008 }
1009
1010 static void
1011 vc4_dump_surface_msaa(struct pipe_surface *psurf)
1012 {
1013 uint32_t tile_w = 32, tile_h = 32;
1014 uint32_t tiles_w = DIV_ROUND_UP(psurf->width, tile_w);
1015 uint32_t tiles_h = DIV_ROUND_UP(psurf->height, tile_h);
1016 uint32_t char_w = 140, char_h = 60;
1017 uint32_t char_w_per_tile = char_w / tiles_w - 1;
1018 uint32_t char_h_per_tile = char_h / tiles_h - 1;
1019
1020 fprintf(stderr, "Surface: %dx%d (%dx MSAA)\n",
1021 psurf->width, psurf->height, psurf->texture->nr_samples);
1022
1023 for (int x = 0; x < (char_w_per_tile + 1) * tiles_w; x++)
1024 fprintf(stderr, "-");
1025 fprintf(stderr, "\n");
1026
1027 for (int ty = 0; ty < psurf->height; ty += tile_h) {
1028 for (int y = 0; y < char_h_per_tile; y++) {
1029
1030 for (int tx = 0; tx < psurf->width; tx += tile_w) {
1031 for (int x = 0; x < char_w_per_tile; x++) {
1032 uint32_t bx1 = (x * tile_w /
1033 char_w_per_tile);
1034 uint32_t bx2 = ((x + 1) * tile_w /
1035 char_w_per_tile);
1036 uint32_t by1 = (y * tile_h /
1037 char_h_per_tile);
1038 uint32_t by2 = ((y + 1) * tile_h /
1039 char_h_per_tile);
1040
1041 vc4_dump_surface_msaa_char(psurf,
1042 tx + bx1,
1043 ty + by1,
1044 bx2 - bx1,
1045 by2 - by1);
1046 }
1047 fprintf(stderr, "|");
1048 }
1049 fprintf(stderr, "\n");
1050 }
1051
1052 for (int x = 0; x < (char_w_per_tile + 1) * tiles_w; x++)
1053 fprintf(stderr, "-");
1054 fprintf(stderr, "\n");
1055 }
1056 }
1057
1058 /** Debug routine to dump the contents of an 8888 surface to the console */
1059 void
1060 vc4_dump_surface(struct pipe_surface *psurf)
1061 {
1062 if (!psurf)
1063 return;
1064
1065 if (psurf->texture->nr_samples > 1)
1066 vc4_dump_surface_msaa(psurf);
1067 else
1068 vc4_dump_surface_non_msaa(psurf);
1069 }
1070
1071 static void
1072 vc4_flush_resource(struct pipe_context *pctx, struct pipe_resource *resource)
1073 {
1074 /* All calls to flush_resource are followed by a flush of the context,
1075 * so there's nothing to do.
1076 */
1077 }
1078
1079 void
1080 vc4_update_shadow_baselevel_texture(struct pipe_context *pctx,
1081 struct pipe_sampler_view *view)
1082 {
1083 struct vc4_resource *shadow = vc4_resource(view->texture);
1084 struct vc4_resource *orig = vc4_resource(shadow->shadow_parent);
1085 assert(orig);
1086
1087 if (shadow->writes == orig->writes && orig->bo->private)
1088 return;
1089
1090 perf_debug("Updating %dx%d@%d shadow texture due to %s\n",
1091 orig->base.width0, orig->base.height0,
1092 view->u.tex.first_level,
1093 view->u.tex.first_level ? "base level" : "raster layout");
1094
1095 for (int i = 0; i <= shadow->base.last_level; i++) {
1096 unsigned width = u_minify(shadow->base.width0, i);
1097 unsigned height = u_minify(shadow->base.height0, i);
1098 struct pipe_blit_info info = {
1099 .dst = {
1100 .resource = &shadow->base,
1101 .level = i,
1102 .box = {
1103 .x = 0,
1104 .y = 0,
1105 .z = 0,
1106 .width = width,
1107 .height = height,
1108 .depth = 1,
1109 },
1110 .format = shadow->base.format,
1111 },
1112 .src = {
1113 .resource = &orig->base,
1114 .level = view->u.tex.first_level + i,
1115 .box = {
1116 .x = 0,
1117 .y = 0,
1118 .z = 0,
1119 .width = width,
1120 .height = height,
1121 .depth = 1,
1122 },
1123 .format = orig->base.format,
1124 },
1125 .mask = ~0,
1126 };
1127 pctx->blit(pctx, &info);
1128 }
1129
1130 shadow->writes = orig->writes;
1131 }
1132
1133 /**
1134 * Converts a 4-byte index buffer to 2 bytes.
1135 *
1136 * Since GLES2 only has support for 1 and 2-byte indices, the hardware doesn't
1137 * include 4-byte index support, and we have to shrink it down.
1138 *
1139 * There's no fallback support for when indices end up being larger than 2^16,
1140 * though it will at least assertion fail. Also, if the original index data
1141 * was in user memory, it would be nice to not have uploaded it to a VBO
1142 * before translating.
1143 */
1144 struct pipe_resource *
1145 vc4_get_shadow_index_buffer(struct pipe_context *pctx,
1146 const struct pipe_draw_info *info,
1147 uint32_t offset,
1148 uint32_t count,
1149 uint32_t *shadow_offset)
1150 {
1151 struct vc4_context *vc4 = vc4_context(pctx);
1152 struct vc4_resource *orig = vc4_resource(info->index.resource);
1153 perf_debug("Fallback conversion for %d uint indices\n", count);
1154
1155 void *data;
1156 struct pipe_resource *shadow_rsc = NULL;
1157 u_upload_alloc(vc4->uploader, 0, count * 2, 4,
1158 shadow_offset, &shadow_rsc, &data);
1159 uint16_t *dst = data;
1160
1161 struct pipe_transfer *src_transfer = NULL;
1162 const uint32_t *src;
1163 if (info->has_user_indices) {
1164 src = info->index.user;
1165 } else {
1166 src = pipe_buffer_map_range(pctx, &orig->base,
1167 offset,
1168 count * 4,
1169 PIPE_TRANSFER_READ, &src_transfer);
1170 }
1171
1172 for (int i = 0; i < count; i++) {
1173 uint32_t src_index = src[i];
1174 assert(src_index <= 0xffff);
1175 dst[i] = src_index;
1176 }
1177
1178 if (src_transfer)
1179 pctx->transfer_unmap(pctx, src_transfer);
1180
1181 return shadow_rsc;
1182 }
1183
1184 void
1185 vc4_resource_screen_init(struct pipe_screen *pscreen)
1186 {
1187 struct vc4_screen *screen = vc4_screen(pscreen);
1188
1189 pscreen->resource_create = vc4_resource_create;
1190 pscreen->resource_create_with_modifiers =
1191 vc4_resource_create_with_modifiers;
1192 pscreen->resource_from_handle = vc4_resource_from_handle;
1193 pscreen->resource_destroy = u_resource_destroy_vtbl;
1194 pscreen->resource_get_handle = vc4_resource_get_handle;
1195 pscreen->resource_destroy = vc4_resource_destroy;
1196
1197 /* Test if the kernel has GET_TILING; it will return -EINVAL if the
1198 * ioctl does not exist, but -ENOENT if we pass an impossible handle.
1199 * 0 cannot be a valid GEM object, so use that.
1200 */
1201 struct drm_vc4_get_tiling get_tiling = {
1202 .handle = 0x0,
1203 };
1204 int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_TILING, &get_tiling);
1205 if (ret == -1 && errno == ENOENT)
1206 screen->has_tiling_ioctl = true;
1207 }
1208
1209 void
1210 vc4_resource_context_init(struct pipe_context *pctx)
1211 {
1212 pctx->transfer_map = vc4_resource_transfer_map;
1213 pctx->transfer_flush_region = u_default_transfer_flush_region;
1214 pctx->transfer_unmap = vc4_resource_transfer_unmap;
1215 pctx->buffer_subdata = u_default_buffer_subdata;
1216 pctx->texture_subdata = u_default_texture_subdata;
1217 pctx->create_surface = vc4_create_surface;
1218 pctx->surface_destroy = vc4_surface_destroy;
1219 pctx->resource_copy_region = util_resource_copy_region;
1220 pctx->blit = vc4_blit;
1221 pctx->flush_resource = vc4_flush_resource;
1222 }