vc4: Add support for rebasing texture levels so firstlevel == 0.
[mesa.git] / src / gallium / drivers / vc4 / vc4_resource.c
1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_format.h"
27 #include "util/u_inlines.h"
28 #include "util/u_surface.h"
29 #include "util/u_blitter.h"
30
31 #include "vc4_screen.h"
32 #include "vc4_context.h"
33 #include "vc4_resource.h"
34 #include "vc4_tiling.h"
35
36 static void
37 vc4_resource_transfer_unmap(struct pipe_context *pctx,
38 struct pipe_transfer *ptrans)
39 {
40 struct vc4_context *vc4 = vc4_context(pctx);
41 struct vc4_transfer *trans = vc4_transfer(ptrans);
42 struct pipe_resource *prsc = ptrans->resource;
43 struct vc4_resource *rsc = vc4_resource(prsc);
44 struct vc4_resource_slice *slice = &rsc->slices[ptrans->level];
45
46 if (trans->map) {
47 if (ptrans->usage & PIPE_TRANSFER_WRITE) {
48 vc4_store_tiled_image(rsc->bo->map + slice->offset +
49 ptrans->box.z * rsc->cube_map_stride,
50 slice->stride,
51 trans->map, ptrans->stride,
52 slice->tiling, rsc->cpp,
53 &ptrans->box);
54 }
55 free(trans->map);
56 }
57
58 pipe_resource_reference(&ptrans->resource, NULL);
59 util_slab_free(&vc4->transfer_pool, ptrans);
60 }
61
62 static void *
63 vc4_resource_transfer_map(struct pipe_context *pctx,
64 struct pipe_resource *prsc,
65 unsigned level, unsigned usage,
66 const struct pipe_box *box,
67 struct pipe_transfer **pptrans)
68 {
69 struct vc4_context *vc4 = vc4_context(pctx);
70 struct vc4_resource *rsc = vc4_resource(prsc);
71 struct vc4_resource_slice *slice = &rsc->slices[level];
72 struct vc4_transfer *trans;
73 struct pipe_transfer *ptrans;
74 enum pipe_format format = prsc->format;
75 char *buf;
76
77 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
78 uint32_t size = rsc->bo->size;
79 vc4_bo_unreference(&rsc->bo);
80 rsc->bo = vc4_bo_alloc(vc4->screen, size, "resource");
81 }
82
83 if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED))
84 vc4_flush_for_bo(pctx, rsc->bo);
85
86 if (usage & PIPE_TRANSFER_WRITE)
87 rsc->writes++;
88
89 trans = util_slab_alloc(&vc4->transfer_pool);
90 if (!trans)
91 return NULL;
92
93 /* XXX: Handle DONTBLOCK, DISCARD_RANGE, PERSISTENT, COHERENT. */
94
95 /* util_slab_alloc() doesn't zero: */
96 memset(trans, 0, sizeof(*trans));
97 ptrans = &trans->base;
98
99 pipe_resource_reference(&ptrans->resource, prsc);
100 ptrans->level = level;
101 ptrans->usage = usage;
102 ptrans->box = *box;
103
104 /* Note that the current kernel implementation is synchronous, so no
105 * need to do syncing stuff here yet.
106 */
107
108 buf = vc4_bo_map(rsc->bo);
109 if (!buf) {
110 fprintf(stderr, "Failed to map bo\n");
111 goto fail;
112 }
113
114 *pptrans = ptrans;
115
116 if (rsc->tiled) {
117 uint32_t utile_w = vc4_utile_width(rsc->cpp);
118 uint32_t utile_h = vc4_utile_height(rsc->cpp);
119
120 /* No direct mappings of tiled, since we need to manually
121 * tile/untile.
122 */
123 if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
124 return NULL;
125
126 /* We need to align the box to utile boundaries, since that's
127 * what load/store operate on.
128 */
129 uint32_t box_start_x = ptrans->box.x & (utile_w - 1);
130 uint32_t box_start_y = ptrans->box.y & (utile_h - 1);
131 ptrans->box.width += box_start_x;
132 ptrans->box.x -= box_start_x;
133 ptrans->box.height += box_start_y;
134 ptrans->box.y -= box_start_y;
135 ptrans->box.width = align(ptrans->box.width, utile_w);
136 ptrans->box.height = align(ptrans->box.height, utile_h);
137
138 ptrans->stride = ptrans->box.width * rsc->cpp;
139 ptrans->layer_stride = ptrans->stride;
140
141 trans->map = malloc(ptrans->stride * ptrans->box.height);
142 if (usage & PIPE_TRANSFER_READ) {
143 vc4_load_tiled_image(trans->map, ptrans->stride,
144 buf + slice->offset +
145 box->z * rsc->cube_map_stride,
146 slice->stride,
147 slice->tiling, rsc->cpp,
148 &ptrans->box);
149 }
150 return (trans->map +
151 box_start_x * rsc->cpp +
152 box_start_y * ptrans->stride);
153 } else {
154 ptrans->stride = slice->stride;
155 ptrans->layer_stride = ptrans->stride;
156
157 return buf + slice->offset +
158 box->y / util_format_get_blockheight(format) * ptrans->stride +
159 box->x / util_format_get_blockwidth(format) * rsc->cpp +
160 box->z * rsc->cube_map_stride;
161 }
162
163
164 fail:
165 vc4_resource_transfer_unmap(pctx, ptrans);
166 return NULL;
167 }
168
169 static void
170 vc4_resource_destroy(struct pipe_screen *pscreen,
171 struct pipe_resource *prsc)
172 {
173 struct vc4_resource *rsc = vc4_resource(prsc);
174 pipe_resource_reference(&rsc->shadow_parent, NULL);
175 vc4_bo_unreference(&rsc->bo);
176 free(rsc);
177 }
178
179 static boolean
180 vc4_resource_get_handle(struct pipe_screen *pscreen,
181 struct pipe_resource *prsc,
182 struct winsys_handle *handle)
183 {
184 struct vc4_resource *rsc = vc4_resource(prsc);
185
186 return vc4_screen_bo_get_handle(pscreen, rsc->bo, rsc->slices[0].stride,
187 handle);
188 }
189
190 static const struct u_resource_vtbl vc4_resource_vtbl = {
191 .resource_get_handle = vc4_resource_get_handle,
192 .resource_destroy = vc4_resource_destroy,
193 .transfer_map = vc4_resource_transfer_map,
194 .transfer_flush_region = u_default_transfer_flush_region,
195 .transfer_unmap = vc4_resource_transfer_unmap,
196 .transfer_inline_write = u_default_transfer_inline_write,
197 };
198
199 static void
200 vc4_setup_slices(struct vc4_resource *rsc)
201 {
202 struct pipe_resource *prsc = &rsc->base.b;
203 uint32_t width = prsc->width0;
204 uint32_t height = prsc->height0;
205 uint32_t pot_width = util_next_power_of_two(width);
206 uint32_t pot_height = util_next_power_of_two(height);
207 uint32_t offset = 0;
208 uint32_t utile_w = vc4_utile_width(rsc->cpp);
209 uint32_t utile_h = vc4_utile_height(rsc->cpp);
210
211 for (int i = prsc->last_level; i >= 0; i--) {
212 struct vc4_resource_slice *slice = &rsc->slices[i];
213
214 uint32_t level_width, level_height;
215 if (i == 0) {
216 level_width = width;
217 level_height = height;
218 } else {
219 level_width = u_minify(pot_width, i);
220 level_height = u_minify(pot_height, i);
221 }
222
223 if (rsc->tiled == VC4_TILING_FORMAT_LINEAR) {
224 slice->tiling = VC4_TILING_FORMAT_LINEAR;
225 level_width = align(level_width, 16);
226 } else {
227 if (vc4_size_is_lt(level_width, level_height,
228 rsc->cpp)) {
229 slice->tiling = VC4_TILING_FORMAT_LT;
230 level_width = align(level_width, utile_w);
231 level_height = align(level_height, utile_h);
232 } else {
233 slice->tiling = VC4_TILING_FORMAT_T;
234 level_width = align(level_width,
235 4 * 2 * utile_w);
236 level_height = align(level_height,
237 4 * 2 * utile_h);
238 }
239 }
240
241 slice->offset = offset;
242 slice->stride = level_width * rsc->cpp;
243 slice->size = level_height * slice->stride;
244
245 offset += slice->size;
246 }
247
248 /* The texture base pointer that has to point to level 0 doesn't have
249 * intra-page bits, so we have to align it, and thus shift up all the
250 * smaller slices.
251 */
252 uint32_t page_align_offset = (align(rsc->slices[0].offset, 4096) -
253 rsc->slices[0].offset);
254 if (page_align_offset) {
255 for (int i = 0; i <= prsc->last_level; i++)
256 rsc->slices[i].offset += page_align_offset;
257 }
258
259 /* Cube map faces appear as whole miptrees at a page-aligned offset
260 * from the first face's miptree.
261 */
262 if (prsc->target == PIPE_TEXTURE_CUBE) {
263 rsc->cube_map_stride = align(rsc->slices[0].offset +
264 rsc->slices[0].size, 4096);
265 }
266 }
267
268 static struct vc4_resource *
269 vc4_resource_setup(struct pipe_screen *pscreen,
270 const struct pipe_resource *tmpl)
271 {
272 struct vc4_resource *rsc = CALLOC_STRUCT(vc4_resource);
273 if (!rsc)
274 return NULL;
275 struct pipe_resource *prsc = &rsc->base.b;
276
277 *prsc = *tmpl;
278
279 pipe_reference_init(&prsc->reference, 1);
280 prsc->screen = pscreen;
281
282 rsc->base.vtbl = &vc4_resource_vtbl;
283 rsc->cpp = util_format_get_blocksize(tmpl->format);
284
285 assert(rsc->cpp);
286
287 return rsc;
288 }
289
290 static enum vc4_texture_data_type
291 get_resource_texture_format(struct pipe_resource *prsc)
292 {
293 struct vc4_resource *rsc = vc4_resource(prsc);
294 uint8_t format = vc4_get_tex_format(prsc->format);
295
296 if (!rsc->tiled) {
297 assert(format == VC4_TEXTURE_TYPE_RGBA8888);
298 return VC4_TEXTURE_TYPE_RGBA32R;
299 }
300
301 return format;
302 }
303
304 struct pipe_resource *
305 vc4_resource_create(struct pipe_screen *pscreen,
306 const struct pipe_resource *tmpl)
307 {
308 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
309 struct pipe_resource *prsc = &rsc->base.b;
310
311 /* We have to make shared be untiled, since we don't have any way to
312 * communicate metadata about tiling currently.
313 */
314 if (tmpl->target == PIPE_BUFFER ||
315 (tmpl->bind & (PIPE_BIND_SCANOUT |
316 PIPE_BIND_LINEAR |
317 PIPE_BIND_SHARED |
318 PIPE_BIND_CURSOR))) {
319 rsc->tiled = false;
320 } else {
321 rsc->tiled = true;
322 }
323
324 vc4_setup_slices(rsc);
325
326 rsc->bo = vc4_bo_alloc(vc4_screen(pscreen),
327 rsc->slices[0].offset +
328 rsc->slices[0].size +
329 rsc->cube_map_stride * (prsc->array_size - 1),
330 "resource");
331 if (!rsc->bo)
332 goto fail;
333
334 if (tmpl->target != PIPE_BUFFER)
335 rsc->vc4_format = get_resource_texture_format(prsc);
336
337 return prsc;
338 fail:
339 vc4_resource_destroy(pscreen, prsc);
340 return NULL;
341 }
342
343 static struct pipe_resource *
344 vc4_resource_from_handle(struct pipe_screen *pscreen,
345 const struct pipe_resource *tmpl,
346 struct winsys_handle *handle)
347 {
348 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
349 struct pipe_resource *prsc = &rsc->base.b;
350 struct vc4_resource_slice *slice = &rsc->slices[0];
351
352 if (!rsc)
353 return NULL;
354
355 rsc->tiled = false;
356 rsc->bo = vc4_screen_bo_from_handle(pscreen, handle, &slice->stride);
357 if (!rsc->bo)
358 goto fail;
359
360 #ifdef USE_VC4_SIMULATOR
361 slice->stride = align(prsc->width0 * rsc->cpp, 16);
362 #endif
363 slice->tiling = VC4_TILING_FORMAT_LINEAR;
364
365 rsc->vc4_format = get_resource_texture_format(prsc);
366
367 return prsc;
368
369 fail:
370 vc4_resource_destroy(pscreen, prsc);
371 return NULL;
372 }
373
374 static struct pipe_surface *
375 vc4_create_surface(struct pipe_context *pctx,
376 struct pipe_resource *ptex,
377 const struct pipe_surface *surf_tmpl)
378 {
379 struct vc4_surface *surface = CALLOC_STRUCT(vc4_surface);
380 struct vc4_resource *rsc = vc4_resource(ptex);
381
382 if (!surface)
383 return NULL;
384
385 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
386
387 struct pipe_surface *psurf = &surface->base;
388 unsigned level = surf_tmpl->u.tex.level;
389
390 pipe_reference_init(&psurf->reference, 1);
391 pipe_resource_reference(&psurf->texture, ptex);
392
393 psurf->context = pctx;
394 psurf->format = surf_tmpl->format;
395 psurf->width = u_minify(ptex->width0, level);
396 psurf->height = u_minify(ptex->height0, level);
397 psurf->u.tex.level = level;
398 psurf->u.tex.first_layer = surf_tmpl->u.tex.first_layer;
399 psurf->u.tex.last_layer = surf_tmpl->u.tex.last_layer;
400 surface->offset = rsc->slices[level].offset;
401 surface->tiling = rsc->slices[level].tiling;
402
403 return &surface->base;
404 }
405
406 static void
407 vc4_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
408 {
409 pipe_resource_reference(&psurf->texture, NULL);
410 FREE(psurf);
411 }
412
413 static void
414 vc4_flush_resource(struct pipe_context *pctx, struct pipe_resource *resource)
415 {
416 struct vc4_context *vc4 = vc4_context(pctx);
417
418 /* XXX: Skip this if we don't have any queued drawing to it. */
419 vc4->base.flush(pctx, NULL, 0);
420 }
421 static bool
422 render_blit(struct pipe_context *ctx, struct pipe_blit_info *info)
423 {
424 struct vc4_context *vc4 = vc4_context(ctx);
425
426 if (!util_blitter_is_blit_supported(vc4->blitter, info)) {
427 fprintf(stderr, "blit unsupported %s -> %s",
428 util_format_short_name(info->src.resource->format),
429 util_format_short_name(info->dst.resource->format));
430 return false;
431 }
432
433 util_blitter_save_vertex_buffer_slot(vc4->blitter, vc4->vertexbuf.vb);
434 util_blitter_save_vertex_elements(vc4->blitter, vc4->vtx);
435 util_blitter_save_vertex_shader(vc4->blitter, vc4->prog.bind_vs);
436 util_blitter_save_rasterizer(vc4->blitter, vc4->rasterizer);
437 util_blitter_save_viewport(vc4->blitter, &vc4->viewport);
438 util_blitter_save_scissor(vc4->blitter, &vc4->scissor);
439 util_blitter_save_fragment_shader(vc4->blitter, vc4->prog.bind_fs);
440 util_blitter_save_blend(vc4->blitter, vc4->blend);
441 util_blitter_save_depth_stencil_alpha(vc4->blitter, vc4->zsa);
442 util_blitter_save_stencil_ref(vc4->blitter, &vc4->stencil_ref);
443 util_blitter_save_sample_mask(vc4->blitter, vc4->sample_mask);
444 util_blitter_save_framebuffer(vc4->blitter, &vc4->framebuffer);
445 util_blitter_save_fragment_sampler_states(vc4->blitter,
446 vc4->fragtex.num_samplers,
447 (void **)vc4->fragtex.samplers);
448 util_blitter_save_fragment_sampler_views(vc4->blitter,
449 vc4->fragtex.num_textures, vc4->fragtex.textures);
450
451 util_blitter_blit(vc4->blitter, info);
452
453 return true;
454 }
455
456 /* Optimal hardware path for blitting pixels.
457 * Scaling, format conversion, up- and downsampling (resolve) are allowed.
458 */
459 static void
460 vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
461 {
462 struct pipe_blit_info info = *blit_info;
463
464 if (info.src.resource->nr_samples > 1 &&
465 info.dst.resource->nr_samples <= 1 &&
466 !util_format_is_depth_or_stencil(info.src.resource->format) &&
467 !util_format_is_pure_integer(info.src.resource->format)) {
468 fprintf(stderr, "color resolve unimplemented");
469 return;
470 }
471
472 if (util_try_blit_via_copy_region(pctx, &info)) {
473 return; /* done */
474 }
475
476 if (info.mask & PIPE_MASK_S) {
477 fprintf(stderr, "cannot blit stencil, skipping");
478 info.mask &= ~PIPE_MASK_S;
479 }
480
481 render_blit(pctx, &info);
482 }
483
484 void
485 vc4_update_shadow_baselevel_texture(struct pipe_context *pctx,
486 struct pipe_sampler_view *view)
487 {
488 struct vc4_resource *shadow = vc4_resource(view->texture);
489 struct vc4_resource *orig = vc4_resource(shadow->shadow_parent);
490 assert(orig);
491
492 if (shadow->writes == orig->writes)
493 return;
494
495 for (int i = 0; i <= shadow->base.b.last_level; i++) {
496 struct pipe_box box = {
497 .x = 0,
498 .y = 0,
499 .z = 0,
500 .width = u_minify(shadow->base.b.width0, i),
501 .height = u_minify(shadow->base.b.height0, i),
502 .depth = 1,
503 };
504
505 util_resource_copy_region(pctx,
506 &shadow->base.b, i, 0, 0, 0,
507 &orig->base.b,
508 view->u.tex.first_level + i,
509 &box);
510 }
511
512 shadow->writes = orig->writes;
513 }
514
515 void
516 vc4_resource_screen_init(struct pipe_screen *pscreen)
517 {
518 pscreen->resource_create = vc4_resource_create;
519 pscreen->resource_from_handle = vc4_resource_from_handle;
520 pscreen->resource_get_handle = u_resource_get_handle_vtbl;
521 pscreen->resource_destroy = u_resource_destroy_vtbl;
522 }
523
524 void
525 vc4_resource_context_init(struct pipe_context *pctx)
526 {
527 pctx->transfer_map = u_transfer_map_vtbl;
528 pctx->transfer_flush_region = u_transfer_flush_region_vtbl;
529 pctx->transfer_unmap = u_transfer_unmap_vtbl;
530 pctx->transfer_inline_write = u_transfer_inline_write_vtbl;
531 pctx->create_surface = vc4_create_surface;
532 pctx->surface_destroy = vc4_surface_destroy;
533 pctx->resource_copy_region = util_resource_copy_region;
534 pctx->blit = vc4_blit;
535 pctx->flush_resource = vc4_flush_resource;
536 }