vc4: Add support for enabling early Z discards.
[mesa.git] / src / gallium / drivers / vc4 / vc4_resource.c
1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_format.h"
27 #include "util/u_inlines.h"
28 #include "util/u_surface.h"
29 #include "util/u_blitter.h"
30
31 #include "vc4_screen.h"
32 #include "vc4_context.h"
33 #include "vc4_resource.h"
34 #include "vc4_tiling.h"
35
36 static void
37 vc4_resource_bo_alloc(struct vc4_resource *rsc)
38 {
39 struct pipe_resource *prsc = &rsc->base.b;
40 struct pipe_screen *pscreen = prsc->screen;
41
42 vc4_bo_unreference(&rsc->bo);
43 rsc->bo = vc4_bo_alloc(vc4_screen(pscreen),
44 rsc->slices[0].offset +
45 rsc->slices[0].size +
46 rsc->cube_map_stride * (prsc->array_size - 1),
47 "resource");
48 }
49
50 static void
51 vc4_resource_transfer_unmap(struct pipe_context *pctx,
52 struct pipe_transfer *ptrans)
53 {
54 struct vc4_context *vc4 = vc4_context(pctx);
55 struct vc4_transfer *trans = vc4_transfer(ptrans);
56 struct pipe_resource *prsc = ptrans->resource;
57 struct vc4_resource *rsc = vc4_resource(prsc);
58 struct vc4_resource_slice *slice = &rsc->slices[ptrans->level];
59
60 if (trans->map) {
61 if (ptrans->usage & PIPE_TRANSFER_WRITE) {
62 vc4_store_tiled_image(rsc->bo->map + slice->offset +
63 ptrans->box.z * rsc->cube_map_stride,
64 slice->stride,
65 trans->map, ptrans->stride,
66 slice->tiling, rsc->cpp,
67 &ptrans->box);
68 }
69 free(trans->map);
70 }
71
72 pipe_resource_reference(&ptrans->resource, NULL);
73 util_slab_free(&vc4->transfer_pool, ptrans);
74 }
75
76 static void *
77 vc4_resource_transfer_map(struct pipe_context *pctx,
78 struct pipe_resource *prsc,
79 unsigned level, unsigned usage,
80 const struct pipe_box *box,
81 struct pipe_transfer **pptrans)
82 {
83 struct vc4_context *vc4 = vc4_context(pctx);
84 struct vc4_resource *rsc = vc4_resource(prsc);
85 struct vc4_resource_slice *slice = &rsc->slices[level];
86 struct vc4_transfer *trans;
87 struct pipe_transfer *ptrans;
88 enum pipe_format format = prsc->format;
89 char *buf;
90
91 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
92 vc4_resource_bo_alloc(rsc);
93 } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
94 if (vc4_cl_references_bo(pctx, rsc->bo)) {
95 if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
96 prsc->last_level == 0 &&
97 prsc->width0 == box->width &&
98 prsc->height0 == box->height &&
99 prsc->depth0 == box->depth) {
100 vc4_resource_bo_alloc(rsc);
101 } else {
102 vc4_flush(pctx);
103 }
104 }
105 }
106
107 if (usage & PIPE_TRANSFER_WRITE)
108 rsc->writes++;
109
110 trans = util_slab_alloc(&vc4->transfer_pool);
111 if (!trans)
112 return NULL;
113
114 /* XXX: Handle DONTBLOCK, DISCARD_RANGE, PERSISTENT, COHERENT. */
115
116 /* util_slab_alloc() doesn't zero: */
117 memset(trans, 0, sizeof(*trans));
118 ptrans = &trans->base;
119
120 pipe_resource_reference(&ptrans->resource, prsc);
121 ptrans->level = level;
122 ptrans->usage = usage;
123 ptrans->box = *box;
124
125 /* Note that the current kernel implementation is synchronous, so no
126 * need to do syncing stuff here yet.
127 */
128
129 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
130 buf = vc4_bo_map_unsynchronized(rsc->bo);
131 else
132 buf = vc4_bo_map(rsc->bo);
133 if (!buf) {
134 fprintf(stderr, "Failed to map bo\n");
135 goto fail;
136 }
137
138 *pptrans = ptrans;
139
140 if (rsc->tiled) {
141 uint32_t utile_w = vc4_utile_width(rsc->cpp);
142 uint32_t utile_h = vc4_utile_height(rsc->cpp);
143
144 /* No direct mappings of tiled, since we need to manually
145 * tile/untile.
146 */
147 if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
148 return NULL;
149
150 /* We need to align the box to utile boundaries, since that's
151 * what load/store operate on.
152 */
153 uint32_t box_start_x = ptrans->box.x & (utile_w - 1);
154 uint32_t box_start_y = ptrans->box.y & (utile_h - 1);
155 ptrans->box.width += box_start_x;
156 ptrans->box.x -= box_start_x;
157 ptrans->box.height += box_start_y;
158 ptrans->box.y -= box_start_y;
159 ptrans->box.width = align(ptrans->box.width, utile_w);
160 ptrans->box.height = align(ptrans->box.height, utile_h);
161
162 ptrans->stride = ptrans->box.width * rsc->cpp;
163 ptrans->layer_stride = ptrans->stride;
164
165 trans->map = malloc(ptrans->stride * ptrans->box.height);
166 if (usage & PIPE_TRANSFER_READ) {
167 vc4_load_tiled_image(trans->map, ptrans->stride,
168 buf + slice->offset +
169 box->z * rsc->cube_map_stride,
170 slice->stride,
171 slice->tiling, rsc->cpp,
172 &ptrans->box);
173 }
174 return (trans->map +
175 box_start_x * rsc->cpp +
176 box_start_y * ptrans->stride);
177 } else {
178 ptrans->stride = slice->stride;
179 ptrans->layer_stride = ptrans->stride;
180
181 return buf + slice->offset +
182 box->y / util_format_get_blockheight(format) * ptrans->stride +
183 box->x / util_format_get_blockwidth(format) * rsc->cpp +
184 box->z * rsc->cube_map_stride;
185 }
186
187
188 fail:
189 vc4_resource_transfer_unmap(pctx, ptrans);
190 return NULL;
191 }
192
193 static void
194 vc4_resource_destroy(struct pipe_screen *pscreen,
195 struct pipe_resource *prsc)
196 {
197 struct vc4_resource *rsc = vc4_resource(prsc);
198 pipe_resource_reference(&rsc->shadow_parent, NULL);
199 vc4_bo_unreference(&rsc->bo);
200 free(rsc);
201 }
202
203 static boolean
204 vc4_resource_get_handle(struct pipe_screen *pscreen,
205 struct pipe_resource *prsc,
206 struct winsys_handle *handle)
207 {
208 struct vc4_resource *rsc = vc4_resource(prsc);
209
210 return vc4_screen_bo_get_handle(pscreen, rsc->bo, rsc->slices[0].stride,
211 handle);
212 }
213
214 static const struct u_resource_vtbl vc4_resource_vtbl = {
215 .resource_get_handle = vc4_resource_get_handle,
216 .resource_destroy = vc4_resource_destroy,
217 .transfer_map = vc4_resource_transfer_map,
218 .transfer_flush_region = u_default_transfer_flush_region,
219 .transfer_unmap = vc4_resource_transfer_unmap,
220 .transfer_inline_write = u_default_transfer_inline_write,
221 };
222
223 static void
224 vc4_setup_slices(struct vc4_resource *rsc)
225 {
226 struct pipe_resource *prsc = &rsc->base.b;
227 uint32_t width = prsc->width0;
228 uint32_t height = prsc->height0;
229 uint32_t pot_width = util_next_power_of_two(width);
230 uint32_t pot_height = util_next_power_of_two(height);
231 uint32_t offset = 0;
232 uint32_t utile_w = vc4_utile_width(rsc->cpp);
233 uint32_t utile_h = vc4_utile_height(rsc->cpp);
234
235 for (int i = prsc->last_level; i >= 0; i--) {
236 struct vc4_resource_slice *slice = &rsc->slices[i];
237
238 uint32_t level_width, level_height;
239 if (i == 0) {
240 level_width = width;
241 level_height = height;
242 } else {
243 level_width = u_minify(pot_width, i);
244 level_height = u_minify(pot_height, i);
245 }
246
247 if (rsc->tiled == VC4_TILING_FORMAT_LINEAR) {
248 slice->tiling = VC4_TILING_FORMAT_LINEAR;
249 level_width = align(level_width, 16);
250 } else {
251 if (vc4_size_is_lt(level_width, level_height,
252 rsc->cpp)) {
253 slice->tiling = VC4_TILING_FORMAT_LT;
254 level_width = align(level_width, utile_w);
255 level_height = align(level_height, utile_h);
256 } else {
257 slice->tiling = VC4_TILING_FORMAT_T;
258 level_width = align(level_width,
259 4 * 2 * utile_w);
260 level_height = align(level_height,
261 4 * 2 * utile_h);
262 }
263 }
264
265 slice->offset = offset;
266 slice->stride = level_width * rsc->cpp;
267 slice->size = level_height * slice->stride;
268
269 offset += slice->size;
270 }
271
272 /* The texture base pointer that has to point to level 0 doesn't have
273 * intra-page bits, so we have to align it, and thus shift up all the
274 * smaller slices.
275 */
276 uint32_t page_align_offset = (align(rsc->slices[0].offset, 4096) -
277 rsc->slices[0].offset);
278 if (page_align_offset) {
279 for (int i = 0; i <= prsc->last_level; i++)
280 rsc->slices[i].offset += page_align_offset;
281 }
282
283 /* Cube map faces appear as whole miptrees at a page-aligned offset
284 * from the first face's miptree.
285 */
286 if (prsc->target == PIPE_TEXTURE_CUBE) {
287 rsc->cube_map_stride = align(rsc->slices[0].offset +
288 rsc->slices[0].size, 4096);
289 }
290 }
291
292 static struct vc4_resource *
293 vc4_resource_setup(struct pipe_screen *pscreen,
294 const struct pipe_resource *tmpl)
295 {
296 struct vc4_resource *rsc = CALLOC_STRUCT(vc4_resource);
297 if (!rsc)
298 return NULL;
299 struct pipe_resource *prsc = &rsc->base.b;
300
301 *prsc = *tmpl;
302
303 pipe_reference_init(&prsc->reference, 1);
304 prsc->screen = pscreen;
305
306 rsc->base.vtbl = &vc4_resource_vtbl;
307 rsc->cpp = util_format_get_blocksize(tmpl->format);
308
309 assert(rsc->cpp);
310
311 return rsc;
312 }
313
314 static enum vc4_texture_data_type
315 get_resource_texture_format(struct pipe_resource *prsc)
316 {
317 struct vc4_resource *rsc = vc4_resource(prsc);
318 uint8_t format = vc4_get_tex_format(prsc->format);
319
320 if (!rsc->tiled) {
321 assert(format == VC4_TEXTURE_TYPE_RGBA8888);
322 return VC4_TEXTURE_TYPE_RGBA32R;
323 }
324
325 return format;
326 }
327
328 struct pipe_resource *
329 vc4_resource_create(struct pipe_screen *pscreen,
330 const struct pipe_resource *tmpl)
331 {
332 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
333 struct pipe_resource *prsc = &rsc->base.b;
334
335 /* We have to make shared be untiled, since we don't have any way to
336 * communicate metadata about tiling currently.
337 */
338 if (tmpl->target == PIPE_BUFFER ||
339 (tmpl->bind & (PIPE_BIND_SCANOUT |
340 PIPE_BIND_LINEAR |
341 PIPE_BIND_SHARED |
342 PIPE_BIND_CURSOR))) {
343 rsc->tiled = false;
344 } else {
345 rsc->tiled = true;
346 }
347
348 vc4_setup_slices(rsc);
349 vc4_resource_bo_alloc(rsc);
350 if (!rsc->bo)
351 goto fail;
352
353 if (tmpl->target != PIPE_BUFFER)
354 rsc->vc4_format = get_resource_texture_format(prsc);
355
356 return prsc;
357 fail:
358 vc4_resource_destroy(pscreen, prsc);
359 return NULL;
360 }
361
362 static struct pipe_resource *
363 vc4_resource_from_handle(struct pipe_screen *pscreen,
364 const struct pipe_resource *tmpl,
365 struct winsys_handle *handle)
366 {
367 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
368 struct pipe_resource *prsc = &rsc->base.b;
369 struct vc4_resource_slice *slice = &rsc->slices[0];
370
371 if (!rsc)
372 return NULL;
373
374 rsc->tiled = false;
375 rsc->bo = vc4_screen_bo_from_handle(pscreen, handle, &slice->stride);
376 if (!rsc->bo)
377 goto fail;
378
379 #ifdef USE_VC4_SIMULATOR
380 slice->stride = align(prsc->width0 * rsc->cpp, 16);
381 #endif
382 slice->tiling = VC4_TILING_FORMAT_LINEAR;
383
384 rsc->vc4_format = get_resource_texture_format(prsc);
385
386 return prsc;
387
388 fail:
389 vc4_resource_destroy(pscreen, prsc);
390 return NULL;
391 }
392
393 static struct pipe_surface *
394 vc4_create_surface(struct pipe_context *pctx,
395 struct pipe_resource *ptex,
396 const struct pipe_surface *surf_tmpl)
397 {
398 struct vc4_surface *surface = CALLOC_STRUCT(vc4_surface);
399 struct vc4_resource *rsc = vc4_resource(ptex);
400
401 if (!surface)
402 return NULL;
403
404 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
405
406 struct pipe_surface *psurf = &surface->base;
407 unsigned level = surf_tmpl->u.tex.level;
408
409 pipe_reference_init(&psurf->reference, 1);
410 pipe_resource_reference(&psurf->texture, ptex);
411
412 psurf->context = pctx;
413 psurf->format = surf_tmpl->format;
414 psurf->width = u_minify(ptex->width0, level);
415 psurf->height = u_minify(ptex->height0, level);
416 psurf->u.tex.level = level;
417 psurf->u.tex.first_layer = surf_tmpl->u.tex.first_layer;
418 psurf->u.tex.last_layer = surf_tmpl->u.tex.last_layer;
419 surface->offset = rsc->slices[level].offset;
420 surface->tiling = rsc->slices[level].tiling;
421
422 return &surface->base;
423 }
424
425 static void
426 vc4_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
427 {
428 pipe_resource_reference(&psurf->texture, NULL);
429 FREE(psurf);
430 }
431
432 static void
433 vc4_flush_resource(struct pipe_context *pctx, struct pipe_resource *resource)
434 {
435 struct vc4_context *vc4 = vc4_context(pctx);
436
437 /* XXX: Skip this if we don't have any queued drawing to it. */
438 vc4->base.flush(pctx, NULL, 0);
439 }
440 static bool
441 render_blit(struct pipe_context *ctx, struct pipe_blit_info *info)
442 {
443 struct vc4_context *vc4 = vc4_context(ctx);
444
445 if (!util_blitter_is_blit_supported(vc4->blitter, info)) {
446 fprintf(stderr, "blit unsupported %s -> %s",
447 util_format_short_name(info->src.resource->format),
448 util_format_short_name(info->dst.resource->format));
449 return false;
450 }
451
452 util_blitter_save_vertex_buffer_slot(vc4->blitter, vc4->vertexbuf.vb);
453 util_blitter_save_vertex_elements(vc4->blitter, vc4->vtx);
454 util_blitter_save_vertex_shader(vc4->blitter, vc4->prog.bind_vs);
455 util_blitter_save_rasterizer(vc4->blitter, vc4->rasterizer);
456 util_blitter_save_viewport(vc4->blitter, &vc4->viewport);
457 util_blitter_save_scissor(vc4->blitter, &vc4->scissor);
458 util_blitter_save_fragment_shader(vc4->blitter, vc4->prog.bind_fs);
459 util_blitter_save_blend(vc4->blitter, vc4->blend);
460 util_blitter_save_depth_stencil_alpha(vc4->blitter, vc4->zsa);
461 util_blitter_save_stencil_ref(vc4->blitter, &vc4->stencil_ref);
462 util_blitter_save_sample_mask(vc4->blitter, vc4->sample_mask);
463 util_blitter_save_framebuffer(vc4->blitter, &vc4->framebuffer);
464 util_blitter_save_fragment_sampler_states(vc4->blitter,
465 vc4->fragtex.num_samplers,
466 (void **)vc4->fragtex.samplers);
467 util_blitter_save_fragment_sampler_views(vc4->blitter,
468 vc4->fragtex.num_textures, vc4->fragtex.textures);
469
470 util_blitter_blit(vc4->blitter, info);
471
472 return true;
473 }
474
475 /* Optimal hardware path for blitting pixels.
476 * Scaling, format conversion, up- and downsampling (resolve) are allowed.
477 */
478 static void
479 vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
480 {
481 struct pipe_blit_info info = *blit_info;
482
483 if (info.src.resource->nr_samples > 1 &&
484 info.dst.resource->nr_samples <= 1 &&
485 !util_format_is_depth_or_stencil(info.src.resource->format) &&
486 !util_format_is_pure_integer(info.src.resource->format)) {
487 fprintf(stderr, "color resolve unimplemented");
488 return;
489 }
490
491 if (util_try_blit_via_copy_region(pctx, &info)) {
492 return; /* done */
493 }
494
495 if (info.mask & PIPE_MASK_S) {
496 fprintf(stderr, "cannot blit stencil, skipping");
497 info.mask &= ~PIPE_MASK_S;
498 }
499
500 render_blit(pctx, &info);
501 }
502
503 void
504 vc4_update_shadow_baselevel_texture(struct pipe_context *pctx,
505 struct pipe_sampler_view *view)
506 {
507 struct vc4_resource *shadow = vc4_resource(view->texture);
508 struct vc4_resource *orig = vc4_resource(shadow->shadow_parent);
509 assert(orig);
510
511 if (shadow->writes == orig->writes)
512 return;
513
514 for (int i = 0; i <= shadow->base.b.last_level; i++) {
515 struct pipe_box box = {
516 .x = 0,
517 .y = 0,
518 .z = 0,
519 .width = u_minify(shadow->base.b.width0, i),
520 .height = u_minify(shadow->base.b.height0, i),
521 .depth = 1,
522 };
523
524 util_resource_copy_region(pctx,
525 &shadow->base.b, i, 0, 0, 0,
526 &orig->base.b,
527 view->u.tex.first_level + i,
528 &box);
529 }
530
531 shadow->writes = orig->writes;
532 }
533
534 /**
535 * Converts a 4-byte index buffer to 2 bytes.
536 *
537 * Since GLES2 only has support for 1 and 2-byte indices, the hardware doesn't
538 * include 4-byte index support, and we have to shrink it down.
539 *
540 * There's no fallback support for when indices end up being larger than 2^16,
541 * though it will at least assertion fail. Also, if the original index data
542 * was in user memory, it would be nice to not have uploaded it to a VBO
543 * before translating.
544 */
545 void
546 vc4_update_shadow_index_buffer(struct pipe_context *pctx,
547 const struct pipe_index_buffer *ib)
548 {
549 struct vc4_resource *shadow = vc4_resource(ib->buffer);
550 struct vc4_resource *orig = vc4_resource(shadow->shadow_parent);
551 uint32_t count = shadow->base.b.width0 / 2;
552
553 if (shadow->writes == orig->writes)
554 return;
555
556 struct pipe_transfer *src_transfer;
557 uint32_t *src = pipe_buffer_map_range(pctx, &orig->base.b,
558 ib->offset,
559 count * 4,
560 PIPE_TRANSFER_READ, &src_transfer);
561
562 struct pipe_transfer *dst_transfer;
563 uint16_t *dst = pipe_buffer_map_range(pctx, &shadow->base.b,
564 0,
565 count * 2,
566 PIPE_TRANSFER_WRITE, &dst_transfer);
567
568 for (int i = 0; i < count; i++) {
569 uint32_t src_index = src[i];
570 assert(src_index <= 0xffff);
571 dst[i] = src_index;
572 }
573
574 pctx->transfer_unmap(pctx, dst_transfer);
575 pctx->transfer_unmap(pctx, src_transfer);
576
577 shadow->writes = orig->writes;
578 }
579
580 void
581 vc4_resource_screen_init(struct pipe_screen *pscreen)
582 {
583 pscreen->resource_create = vc4_resource_create;
584 pscreen->resource_from_handle = vc4_resource_from_handle;
585 pscreen->resource_get_handle = u_resource_get_handle_vtbl;
586 pscreen->resource_destroy = u_resource_destroy_vtbl;
587 }
588
589 void
590 vc4_resource_context_init(struct pipe_context *pctx)
591 {
592 pctx->transfer_map = u_transfer_map_vtbl;
593 pctx->transfer_flush_region = u_transfer_flush_region_vtbl;
594 pctx->transfer_unmap = u_transfer_unmap_vtbl;
595 pctx->transfer_inline_write = u_transfer_inline_write_vtbl;
596 pctx->create_surface = vc4_create_surface;
597 pctx->surface_destroy = vc4_surface_destroy;
598 pctx->resource_copy_region = util_resource_copy_region;
599 pctx->blit = vc4_blit;
600 pctx->flush_resource = vc4_flush_resource;
601 }