2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "util/u_memory.h"
26 #include "util/u_format.h"
27 #include "util/u_inlines.h"
28 #include "util/u_surface.h"
29 #include "util/u_blitter.h"
31 #include "vc4_screen.h"
32 #include "vc4_context.h"
33 #include "vc4_resource.h"
34 #include "vc4_tiling.h"
37 vc4_resource_bo_alloc(struct vc4_resource
*rsc
)
39 struct pipe_resource
*prsc
= &rsc
->base
.b
;
40 struct pipe_screen
*pscreen
= prsc
->screen
;
42 vc4_bo_unreference(&rsc
->bo
);
43 rsc
->bo
= vc4_bo_alloc(vc4_screen(pscreen
),
44 rsc
->slices
[0].offset
+
46 rsc
->cube_map_stride
* (prsc
->array_size
- 1),
51 vc4_resource_transfer_unmap(struct pipe_context
*pctx
,
52 struct pipe_transfer
*ptrans
)
54 struct vc4_context
*vc4
= vc4_context(pctx
);
55 struct vc4_transfer
*trans
= vc4_transfer(ptrans
);
56 struct pipe_resource
*prsc
= ptrans
->resource
;
57 struct vc4_resource
*rsc
= vc4_resource(prsc
);
58 struct vc4_resource_slice
*slice
= &rsc
->slices
[ptrans
->level
];
61 if (ptrans
->usage
& PIPE_TRANSFER_WRITE
) {
62 vc4_store_tiled_image(rsc
->bo
->map
+ slice
->offset
+
63 ptrans
->box
.z
* rsc
->cube_map_stride
,
65 trans
->map
, ptrans
->stride
,
66 slice
->tiling
, rsc
->cpp
,
72 pipe_resource_reference(&ptrans
->resource
, NULL
);
73 util_slab_free(&vc4
->transfer_pool
, ptrans
);
77 vc4_resource_transfer_map(struct pipe_context
*pctx
,
78 struct pipe_resource
*prsc
,
79 unsigned level
, unsigned usage
,
80 const struct pipe_box
*box
,
81 struct pipe_transfer
**pptrans
)
83 struct vc4_context
*vc4
= vc4_context(pctx
);
84 struct vc4_resource
*rsc
= vc4_resource(prsc
);
85 struct vc4_resource_slice
*slice
= &rsc
->slices
[level
];
86 struct vc4_transfer
*trans
;
87 struct pipe_transfer
*ptrans
;
88 enum pipe_format format
= prsc
->format
;
91 if (usage
& PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
) {
92 vc4_resource_bo_alloc(rsc
);
93 } else if (!(usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)) {
94 if (vc4_cl_references_bo(pctx
, rsc
->bo
)) {
95 if ((usage
& PIPE_TRANSFER_DISCARD_RANGE
) &&
96 prsc
->last_level
== 0 &&
97 prsc
->width0
== box
->width
&&
98 prsc
->height0
== box
->height
&&
99 prsc
->depth0
== box
->depth
) {
100 vc4_resource_bo_alloc(rsc
);
107 if (usage
& PIPE_TRANSFER_WRITE
)
110 trans
= util_slab_alloc(&vc4
->transfer_pool
);
114 /* XXX: Handle DONTBLOCK, DISCARD_RANGE, PERSISTENT, COHERENT. */
116 /* util_slab_alloc() doesn't zero: */
117 memset(trans
, 0, sizeof(*trans
));
118 ptrans
= &trans
->base
;
120 pipe_resource_reference(&ptrans
->resource
, prsc
);
121 ptrans
->level
= level
;
122 ptrans
->usage
= usage
;
125 /* Note that the current kernel implementation is synchronous, so no
126 * need to do syncing stuff here yet.
129 if (usage
& PIPE_TRANSFER_UNSYNCHRONIZED
)
130 buf
= vc4_bo_map_unsynchronized(rsc
->bo
);
132 buf
= vc4_bo_map(rsc
->bo
);
134 fprintf(stderr
, "Failed to map bo\n");
141 uint32_t utile_w
= vc4_utile_width(rsc
->cpp
);
142 uint32_t utile_h
= vc4_utile_height(rsc
->cpp
);
144 /* No direct mappings of tiled, since we need to manually
147 if (usage
& PIPE_TRANSFER_MAP_DIRECTLY
)
150 /* We need to align the box to utile boundaries, since that's
151 * what load/store operate on.
153 uint32_t box_start_x
= ptrans
->box
.x
& (utile_w
- 1);
154 uint32_t box_start_y
= ptrans
->box
.y
& (utile_h
- 1);
155 ptrans
->box
.width
+= box_start_x
;
156 ptrans
->box
.x
-= box_start_x
;
157 ptrans
->box
.height
+= box_start_y
;
158 ptrans
->box
.y
-= box_start_y
;
159 ptrans
->box
.width
= align(ptrans
->box
.width
, utile_w
);
160 ptrans
->box
.height
= align(ptrans
->box
.height
, utile_h
);
162 ptrans
->stride
= ptrans
->box
.width
* rsc
->cpp
;
163 ptrans
->layer_stride
= ptrans
->stride
;
165 trans
->map
= malloc(ptrans
->stride
* ptrans
->box
.height
);
166 if (usage
& PIPE_TRANSFER_READ
) {
167 vc4_load_tiled_image(trans
->map
, ptrans
->stride
,
168 buf
+ slice
->offset
+
169 box
->z
* rsc
->cube_map_stride
,
171 slice
->tiling
, rsc
->cpp
,
175 box_start_x
* rsc
->cpp
+
176 box_start_y
* ptrans
->stride
);
178 ptrans
->stride
= slice
->stride
;
179 ptrans
->layer_stride
= ptrans
->stride
;
181 return buf
+ slice
->offset
+
182 box
->y
/ util_format_get_blockheight(format
) * ptrans
->stride
+
183 box
->x
/ util_format_get_blockwidth(format
) * rsc
->cpp
+
184 box
->z
* rsc
->cube_map_stride
;
189 vc4_resource_transfer_unmap(pctx
, ptrans
);
194 vc4_resource_destroy(struct pipe_screen
*pscreen
,
195 struct pipe_resource
*prsc
)
197 struct vc4_resource
*rsc
= vc4_resource(prsc
);
198 pipe_resource_reference(&rsc
->shadow_parent
, NULL
);
199 vc4_bo_unreference(&rsc
->bo
);
204 vc4_resource_get_handle(struct pipe_screen
*pscreen
,
205 struct pipe_resource
*prsc
,
206 struct winsys_handle
*handle
)
208 struct vc4_resource
*rsc
= vc4_resource(prsc
);
210 return vc4_screen_bo_get_handle(pscreen
, rsc
->bo
, rsc
->slices
[0].stride
,
214 static const struct u_resource_vtbl vc4_resource_vtbl
= {
215 .resource_get_handle
= vc4_resource_get_handle
,
216 .resource_destroy
= vc4_resource_destroy
,
217 .transfer_map
= vc4_resource_transfer_map
,
218 .transfer_flush_region
= u_default_transfer_flush_region
,
219 .transfer_unmap
= vc4_resource_transfer_unmap
,
220 .transfer_inline_write
= u_default_transfer_inline_write
,
224 vc4_setup_slices(struct vc4_resource
*rsc
)
226 struct pipe_resource
*prsc
= &rsc
->base
.b
;
227 uint32_t width
= prsc
->width0
;
228 uint32_t height
= prsc
->height0
;
229 uint32_t pot_width
= util_next_power_of_two(width
);
230 uint32_t pot_height
= util_next_power_of_two(height
);
232 uint32_t utile_w
= vc4_utile_width(rsc
->cpp
);
233 uint32_t utile_h
= vc4_utile_height(rsc
->cpp
);
235 for (int i
= prsc
->last_level
; i
>= 0; i
--) {
236 struct vc4_resource_slice
*slice
= &rsc
->slices
[i
];
238 uint32_t level_width
, level_height
;
241 level_height
= height
;
243 level_width
= u_minify(pot_width
, i
);
244 level_height
= u_minify(pot_height
, i
);
247 if (rsc
->tiled
== VC4_TILING_FORMAT_LINEAR
) {
248 slice
->tiling
= VC4_TILING_FORMAT_LINEAR
;
249 level_width
= align(level_width
, 16);
251 if (vc4_size_is_lt(level_width
, level_height
,
253 slice
->tiling
= VC4_TILING_FORMAT_LT
;
254 level_width
= align(level_width
, utile_w
);
255 level_height
= align(level_height
, utile_h
);
257 slice
->tiling
= VC4_TILING_FORMAT_T
;
258 level_width
= align(level_width
,
260 level_height
= align(level_height
,
265 slice
->offset
= offset
;
266 slice
->stride
= level_width
* rsc
->cpp
;
267 slice
->size
= level_height
* slice
->stride
;
269 offset
+= slice
->size
;
272 /* The texture base pointer that has to point to level 0 doesn't have
273 * intra-page bits, so we have to align it, and thus shift up all the
276 uint32_t page_align_offset
= (align(rsc
->slices
[0].offset
, 4096) -
277 rsc
->slices
[0].offset
);
278 if (page_align_offset
) {
279 for (int i
= 0; i
<= prsc
->last_level
; i
++)
280 rsc
->slices
[i
].offset
+= page_align_offset
;
283 /* Cube map faces appear as whole miptrees at a page-aligned offset
284 * from the first face's miptree.
286 if (prsc
->target
== PIPE_TEXTURE_CUBE
) {
287 rsc
->cube_map_stride
= align(rsc
->slices
[0].offset
+
288 rsc
->slices
[0].size
, 4096);
292 static struct vc4_resource
*
293 vc4_resource_setup(struct pipe_screen
*pscreen
,
294 const struct pipe_resource
*tmpl
)
296 struct vc4_resource
*rsc
= CALLOC_STRUCT(vc4_resource
);
299 struct pipe_resource
*prsc
= &rsc
->base
.b
;
303 pipe_reference_init(&prsc
->reference
, 1);
304 prsc
->screen
= pscreen
;
306 rsc
->base
.vtbl
= &vc4_resource_vtbl
;
307 rsc
->cpp
= util_format_get_blocksize(tmpl
->format
);
314 static enum vc4_texture_data_type
315 get_resource_texture_format(struct pipe_resource
*prsc
)
317 struct vc4_resource
*rsc
= vc4_resource(prsc
);
318 uint8_t format
= vc4_get_tex_format(prsc
->format
);
321 assert(format
== VC4_TEXTURE_TYPE_RGBA8888
);
322 return VC4_TEXTURE_TYPE_RGBA32R
;
328 struct pipe_resource
*
329 vc4_resource_create(struct pipe_screen
*pscreen
,
330 const struct pipe_resource
*tmpl
)
332 struct vc4_resource
*rsc
= vc4_resource_setup(pscreen
, tmpl
);
333 struct pipe_resource
*prsc
= &rsc
->base
.b
;
335 /* We have to make shared be untiled, since we don't have any way to
336 * communicate metadata about tiling currently.
338 if (tmpl
->target
== PIPE_BUFFER
||
339 (tmpl
->bind
& (PIPE_BIND_SCANOUT
|
342 PIPE_BIND_CURSOR
))) {
348 vc4_setup_slices(rsc
);
349 vc4_resource_bo_alloc(rsc
);
353 if (tmpl
->target
!= PIPE_BUFFER
)
354 rsc
->vc4_format
= get_resource_texture_format(prsc
);
358 vc4_resource_destroy(pscreen
, prsc
);
362 static struct pipe_resource
*
363 vc4_resource_from_handle(struct pipe_screen
*pscreen
,
364 const struct pipe_resource
*tmpl
,
365 struct winsys_handle
*handle
)
367 struct vc4_resource
*rsc
= vc4_resource_setup(pscreen
, tmpl
);
368 struct pipe_resource
*prsc
= &rsc
->base
.b
;
369 struct vc4_resource_slice
*slice
= &rsc
->slices
[0];
375 rsc
->bo
= vc4_screen_bo_from_handle(pscreen
, handle
);
379 #ifdef USE_VC4_SIMULATOR
380 slice
->stride
= align(prsc
->width0
* rsc
->cpp
, 16);
382 slice
->stride
= handle
->stride
;
384 slice
->tiling
= VC4_TILING_FORMAT_LINEAR
;
386 rsc
->vc4_format
= get_resource_texture_format(prsc
);
391 vc4_resource_destroy(pscreen
, prsc
);
395 static struct pipe_surface
*
396 vc4_create_surface(struct pipe_context
*pctx
,
397 struct pipe_resource
*ptex
,
398 const struct pipe_surface
*surf_tmpl
)
400 struct vc4_surface
*surface
= CALLOC_STRUCT(vc4_surface
);
401 struct vc4_resource
*rsc
= vc4_resource(ptex
);
406 assert(surf_tmpl
->u
.tex
.first_layer
== surf_tmpl
->u
.tex
.last_layer
);
408 struct pipe_surface
*psurf
= &surface
->base
;
409 unsigned level
= surf_tmpl
->u
.tex
.level
;
411 pipe_reference_init(&psurf
->reference
, 1);
412 pipe_resource_reference(&psurf
->texture
, ptex
);
414 psurf
->context
= pctx
;
415 psurf
->format
= surf_tmpl
->format
;
416 psurf
->width
= u_minify(ptex
->width0
, level
);
417 psurf
->height
= u_minify(ptex
->height0
, level
);
418 psurf
->u
.tex
.level
= level
;
419 psurf
->u
.tex
.first_layer
= surf_tmpl
->u
.tex
.first_layer
;
420 psurf
->u
.tex
.last_layer
= surf_tmpl
->u
.tex
.last_layer
;
421 surface
->offset
= rsc
->slices
[level
].offset
;
422 surface
->tiling
= rsc
->slices
[level
].tiling
;
424 return &surface
->base
;
428 vc4_surface_destroy(struct pipe_context
*pctx
, struct pipe_surface
*psurf
)
430 pipe_resource_reference(&psurf
->texture
, NULL
);
435 vc4_flush_resource(struct pipe_context
*pctx
, struct pipe_resource
*resource
)
437 /* All calls to flush_resource are followed by a flush of the context,
438 * so there's nothing to do.
443 render_blit(struct pipe_context
*ctx
, struct pipe_blit_info
*info
)
445 struct vc4_context
*vc4
= vc4_context(ctx
);
447 if (!util_blitter_is_blit_supported(vc4
->blitter
, info
)) {
448 fprintf(stderr
, "blit unsupported %s -> %s",
449 util_format_short_name(info
->src
.resource
->format
),
450 util_format_short_name(info
->dst
.resource
->format
));
454 util_blitter_save_vertex_buffer_slot(vc4
->blitter
, vc4
->vertexbuf
.vb
);
455 util_blitter_save_vertex_elements(vc4
->blitter
, vc4
->vtx
);
456 util_blitter_save_vertex_shader(vc4
->blitter
, vc4
->prog
.bind_vs
);
457 util_blitter_save_rasterizer(vc4
->blitter
, vc4
->rasterizer
);
458 util_blitter_save_viewport(vc4
->blitter
, &vc4
->viewport
);
459 util_blitter_save_scissor(vc4
->blitter
, &vc4
->scissor
);
460 util_blitter_save_fragment_shader(vc4
->blitter
, vc4
->prog
.bind_fs
);
461 util_blitter_save_blend(vc4
->blitter
, vc4
->blend
);
462 util_blitter_save_depth_stencil_alpha(vc4
->blitter
, vc4
->zsa
);
463 util_blitter_save_stencil_ref(vc4
->blitter
, &vc4
->stencil_ref
);
464 util_blitter_save_sample_mask(vc4
->blitter
, vc4
->sample_mask
);
465 util_blitter_save_framebuffer(vc4
->blitter
, &vc4
->framebuffer
);
466 util_blitter_save_fragment_sampler_states(vc4
->blitter
,
467 vc4
->fragtex
.num_samplers
,
468 (void **)vc4
->fragtex
.samplers
);
469 util_blitter_save_fragment_sampler_views(vc4
->blitter
,
470 vc4
->fragtex
.num_textures
, vc4
->fragtex
.textures
);
472 util_blitter_blit(vc4
->blitter
, info
);
477 /* Optimal hardware path for blitting pixels.
478 * Scaling, format conversion, up- and downsampling (resolve) are allowed.
481 vc4_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
)
483 struct pipe_blit_info info
= *blit_info
;
485 if (info
.src
.resource
->nr_samples
> 1 &&
486 info
.dst
.resource
->nr_samples
<= 1 &&
487 !util_format_is_depth_or_stencil(info
.src
.resource
->format
) &&
488 !util_format_is_pure_integer(info
.src
.resource
->format
)) {
489 fprintf(stderr
, "color resolve unimplemented");
493 if (util_try_blit_via_copy_region(pctx
, &info
)) {
497 if (info
.mask
& PIPE_MASK_S
) {
498 fprintf(stderr
, "cannot blit stencil, skipping");
499 info
.mask
&= ~PIPE_MASK_S
;
502 render_blit(pctx
, &info
);
506 vc4_update_shadow_baselevel_texture(struct pipe_context
*pctx
,
507 struct pipe_sampler_view
*view
)
509 struct vc4_resource
*shadow
= vc4_resource(view
->texture
);
510 struct vc4_resource
*orig
= vc4_resource(shadow
->shadow_parent
);
513 if (shadow
->writes
== orig
->writes
)
516 for (int i
= 0; i
<= shadow
->base
.b
.last_level
; i
++) {
517 struct pipe_box box
= {
521 .width
= u_minify(shadow
->base
.b
.width0
, i
),
522 .height
= u_minify(shadow
->base
.b
.height0
, i
),
526 util_resource_copy_region(pctx
,
527 &shadow
->base
.b
, i
, 0, 0, 0,
529 view
->u
.tex
.first_level
+ i
,
533 shadow
->writes
= orig
->writes
;
537 * Converts a 4-byte index buffer to 2 bytes.
539 * Since GLES2 only has support for 1 and 2-byte indices, the hardware doesn't
540 * include 4-byte index support, and we have to shrink it down.
542 * There's no fallback support for when indices end up being larger than 2^16,
543 * though it will at least assertion fail. Also, if the original index data
544 * was in user memory, it would be nice to not have uploaded it to a VBO
545 * before translating.
548 vc4_update_shadow_index_buffer(struct pipe_context
*pctx
,
549 const struct pipe_index_buffer
*ib
)
551 struct vc4_resource
*shadow
= vc4_resource(ib
->buffer
);
552 struct vc4_resource
*orig
= vc4_resource(shadow
->shadow_parent
);
553 uint32_t count
= shadow
->base
.b
.width0
/ 2;
555 if (shadow
->writes
== orig
->writes
)
558 struct pipe_transfer
*src_transfer
;
559 uint32_t *src
= pipe_buffer_map_range(pctx
, &orig
->base
.b
,
562 PIPE_TRANSFER_READ
, &src_transfer
);
564 struct pipe_transfer
*dst_transfer
;
565 uint16_t *dst
= pipe_buffer_map_range(pctx
, &shadow
->base
.b
,
568 PIPE_TRANSFER_WRITE
, &dst_transfer
);
570 for (int i
= 0; i
< count
; i
++) {
571 uint32_t src_index
= src
[i
];
572 assert(src_index
<= 0xffff);
576 pctx
->transfer_unmap(pctx
, dst_transfer
);
577 pctx
->transfer_unmap(pctx
, src_transfer
);
579 shadow
->writes
= orig
->writes
;
583 vc4_resource_screen_init(struct pipe_screen
*pscreen
)
585 pscreen
->resource_create
= vc4_resource_create
;
586 pscreen
->resource_from_handle
= vc4_resource_from_handle
;
587 pscreen
->resource_get_handle
= u_resource_get_handle_vtbl
;
588 pscreen
->resource_destroy
= u_resource_destroy_vtbl
;
592 vc4_resource_context_init(struct pipe_context
*pctx
)
594 pctx
->transfer_map
= u_transfer_map_vtbl
;
595 pctx
->transfer_flush_region
= u_transfer_flush_region_vtbl
;
596 pctx
->transfer_unmap
= u_transfer_unmap_vtbl
;
597 pctx
->transfer_inline_write
= u_transfer_inline_write_vtbl
;
598 pctx
->create_surface
= vc4_create_surface
;
599 pctx
->surface_destroy
= vc4_surface_destroy
;
600 pctx
->resource_copy_region
= util_resource_copy_region
;
601 pctx
->blit
= vc4_blit
;
602 pctx
->flush_resource
= vc4_flush_resource
;