vc4: Fix mixup of return type in reloc_tex().
[mesa.git] / src / gallium / drivers / vc4 / vc4_resource.c
1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "util/u_memory.h"
26 #include "util/u_format.h"
27 #include "util/u_inlines.h"
28 #include "util/u_surface.h"
29 #include "util/u_blitter.h"
30
31 #include "vc4_screen.h"
32 #include "vc4_context.h"
33 #include "vc4_resource.h"
34 #include "vc4_tiling.h"
35
36 static void
37 vc4_resource_bo_alloc(struct vc4_resource *rsc)
38 {
39 struct pipe_resource *prsc = &rsc->base.b;
40 struct pipe_screen *pscreen = prsc->screen;
41
42 vc4_bo_unreference(&rsc->bo);
43 rsc->bo = vc4_bo_alloc(vc4_screen(pscreen),
44 rsc->slices[0].offset +
45 rsc->slices[0].size +
46 rsc->cube_map_stride * (prsc->array_size - 1),
47 "resource");
48 }
49
50 static void
51 vc4_resource_transfer_unmap(struct pipe_context *pctx,
52 struct pipe_transfer *ptrans)
53 {
54 struct vc4_context *vc4 = vc4_context(pctx);
55 struct vc4_transfer *trans = vc4_transfer(ptrans);
56 struct pipe_resource *prsc = ptrans->resource;
57 struct vc4_resource *rsc = vc4_resource(prsc);
58 struct vc4_resource_slice *slice = &rsc->slices[ptrans->level];
59
60 if (trans->map) {
61 if (ptrans->usage & PIPE_TRANSFER_WRITE) {
62 vc4_store_tiled_image(rsc->bo->map + slice->offset +
63 ptrans->box.z * rsc->cube_map_stride,
64 slice->stride,
65 trans->map, ptrans->stride,
66 slice->tiling, rsc->cpp,
67 &ptrans->box);
68 }
69 free(trans->map);
70 }
71
72 pipe_resource_reference(&ptrans->resource, NULL);
73 util_slab_free(&vc4->transfer_pool, ptrans);
74 }
75
76 static void *
77 vc4_resource_transfer_map(struct pipe_context *pctx,
78 struct pipe_resource *prsc,
79 unsigned level, unsigned usage,
80 const struct pipe_box *box,
81 struct pipe_transfer **pptrans)
82 {
83 struct vc4_context *vc4 = vc4_context(pctx);
84 struct vc4_resource *rsc = vc4_resource(prsc);
85 struct vc4_resource_slice *slice = &rsc->slices[level];
86 struct vc4_transfer *trans;
87 struct pipe_transfer *ptrans;
88 enum pipe_format format = prsc->format;
89 char *buf;
90
91 if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
92 vc4_resource_bo_alloc(rsc);
93 } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
94 if (vc4_cl_references_bo(pctx, rsc->bo)) {
95 if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
96 prsc->last_level == 0 &&
97 prsc->width0 == box->width &&
98 prsc->height0 == box->height &&
99 prsc->depth0 == box->depth) {
100 vc4_resource_bo_alloc(rsc);
101 } else {
102 vc4_flush(pctx);
103 }
104 }
105 }
106
107 if (usage & PIPE_TRANSFER_WRITE)
108 rsc->writes++;
109
110 trans = util_slab_alloc(&vc4->transfer_pool);
111 if (!trans)
112 return NULL;
113
114 /* XXX: Handle DONTBLOCK, DISCARD_RANGE, PERSISTENT, COHERENT. */
115
116 /* util_slab_alloc() doesn't zero: */
117 memset(trans, 0, sizeof(*trans));
118 ptrans = &trans->base;
119
120 pipe_resource_reference(&ptrans->resource, prsc);
121 ptrans->level = level;
122 ptrans->usage = usage;
123 ptrans->box = *box;
124
125 /* Note that the current kernel implementation is synchronous, so no
126 * need to do syncing stuff here yet.
127 */
128
129 buf = vc4_bo_map(rsc->bo);
130 if (!buf) {
131 fprintf(stderr, "Failed to map bo\n");
132 goto fail;
133 }
134
135 *pptrans = ptrans;
136
137 if (rsc->tiled) {
138 uint32_t utile_w = vc4_utile_width(rsc->cpp);
139 uint32_t utile_h = vc4_utile_height(rsc->cpp);
140
141 /* No direct mappings of tiled, since we need to manually
142 * tile/untile.
143 */
144 if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
145 return NULL;
146
147 /* We need to align the box to utile boundaries, since that's
148 * what load/store operate on.
149 */
150 uint32_t box_start_x = ptrans->box.x & (utile_w - 1);
151 uint32_t box_start_y = ptrans->box.y & (utile_h - 1);
152 ptrans->box.width += box_start_x;
153 ptrans->box.x -= box_start_x;
154 ptrans->box.height += box_start_y;
155 ptrans->box.y -= box_start_y;
156 ptrans->box.width = align(ptrans->box.width, utile_w);
157 ptrans->box.height = align(ptrans->box.height, utile_h);
158
159 ptrans->stride = ptrans->box.width * rsc->cpp;
160 ptrans->layer_stride = ptrans->stride;
161
162 trans->map = malloc(ptrans->stride * ptrans->box.height);
163 if (usage & PIPE_TRANSFER_READ) {
164 vc4_load_tiled_image(trans->map, ptrans->stride,
165 buf + slice->offset +
166 box->z * rsc->cube_map_stride,
167 slice->stride,
168 slice->tiling, rsc->cpp,
169 &ptrans->box);
170 }
171 return (trans->map +
172 box_start_x * rsc->cpp +
173 box_start_y * ptrans->stride);
174 } else {
175 ptrans->stride = slice->stride;
176 ptrans->layer_stride = ptrans->stride;
177
178 return buf + slice->offset +
179 box->y / util_format_get_blockheight(format) * ptrans->stride +
180 box->x / util_format_get_blockwidth(format) * rsc->cpp +
181 box->z * rsc->cube_map_stride;
182 }
183
184
185 fail:
186 vc4_resource_transfer_unmap(pctx, ptrans);
187 return NULL;
188 }
189
190 static void
191 vc4_resource_destroy(struct pipe_screen *pscreen,
192 struct pipe_resource *prsc)
193 {
194 struct vc4_resource *rsc = vc4_resource(prsc);
195 pipe_resource_reference(&rsc->shadow_parent, NULL);
196 vc4_bo_unreference(&rsc->bo);
197 free(rsc);
198 }
199
200 static boolean
201 vc4_resource_get_handle(struct pipe_screen *pscreen,
202 struct pipe_resource *prsc,
203 struct winsys_handle *handle)
204 {
205 struct vc4_resource *rsc = vc4_resource(prsc);
206
207 return vc4_screen_bo_get_handle(pscreen, rsc->bo, rsc->slices[0].stride,
208 handle);
209 }
210
211 static const struct u_resource_vtbl vc4_resource_vtbl = {
212 .resource_get_handle = vc4_resource_get_handle,
213 .resource_destroy = vc4_resource_destroy,
214 .transfer_map = vc4_resource_transfer_map,
215 .transfer_flush_region = u_default_transfer_flush_region,
216 .transfer_unmap = vc4_resource_transfer_unmap,
217 .transfer_inline_write = u_default_transfer_inline_write,
218 };
219
220 static void
221 vc4_setup_slices(struct vc4_resource *rsc)
222 {
223 struct pipe_resource *prsc = &rsc->base.b;
224 uint32_t width = prsc->width0;
225 uint32_t height = prsc->height0;
226 uint32_t pot_width = util_next_power_of_two(width);
227 uint32_t pot_height = util_next_power_of_two(height);
228 uint32_t offset = 0;
229 uint32_t utile_w = vc4_utile_width(rsc->cpp);
230 uint32_t utile_h = vc4_utile_height(rsc->cpp);
231
232 for (int i = prsc->last_level; i >= 0; i--) {
233 struct vc4_resource_slice *slice = &rsc->slices[i];
234
235 uint32_t level_width, level_height;
236 if (i == 0) {
237 level_width = width;
238 level_height = height;
239 } else {
240 level_width = u_minify(pot_width, i);
241 level_height = u_minify(pot_height, i);
242 }
243
244 if (rsc->tiled == VC4_TILING_FORMAT_LINEAR) {
245 slice->tiling = VC4_TILING_FORMAT_LINEAR;
246 level_width = align(level_width, 16);
247 } else {
248 if (vc4_size_is_lt(level_width, level_height,
249 rsc->cpp)) {
250 slice->tiling = VC4_TILING_FORMAT_LT;
251 level_width = align(level_width, utile_w);
252 level_height = align(level_height, utile_h);
253 } else {
254 slice->tiling = VC4_TILING_FORMAT_T;
255 level_width = align(level_width,
256 4 * 2 * utile_w);
257 level_height = align(level_height,
258 4 * 2 * utile_h);
259 }
260 }
261
262 slice->offset = offset;
263 slice->stride = level_width * rsc->cpp;
264 slice->size = level_height * slice->stride;
265
266 offset += slice->size;
267 }
268
269 /* The texture base pointer that has to point to level 0 doesn't have
270 * intra-page bits, so we have to align it, and thus shift up all the
271 * smaller slices.
272 */
273 uint32_t page_align_offset = (align(rsc->slices[0].offset, 4096) -
274 rsc->slices[0].offset);
275 if (page_align_offset) {
276 for (int i = 0; i <= prsc->last_level; i++)
277 rsc->slices[i].offset += page_align_offset;
278 }
279
280 /* Cube map faces appear as whole miptrees at a page-aligned offset
281 * from the first face's miptree.
282 */
283 if (prsc->target == PIPE_TEXTURE_CUBE) {
284 rsc->cube_map_stride = align(rsc->slices[0].offset +
285 rsc->slices[0].size, 4096);
286 }
287 }
288
289 static struct vc4_resource *
290 vc4_resource_setup(struct pipe_screen *pscreen,
291 const struct pipe_resource *tmpl)
292 {
293 struct vc4_resource *rsc = CALLOC_STRUCT(vc4_resource);
294 if (!rsc)
295 return NULL;
296 struct pipe_resource *prsc = &rsc->base.b;
297
298 *prsc = *tmpl;
299
300 pipe_reference_init(&prsc->reference, 1);
301 prsc->screen = pscreen;
302
303 rsc->base.vtbl = &vc4_resource_vtbl;
304 rsc->cpp = util_format_get_blocksize(tmpl->format);
305
306 assert(rsc->cpp);
307
308 return rsc;
309 }
310
311 static enum vc4_texture_data_type
312 get_resource_texture_format(struct pipe_resource *prsc)
313 {
314 struct vc4_resource *rsc = vc4_resource(prsc);
315 uint8_t format = vc4_get_tex_format(prsc->format);
316
317 if (!rsc->tiled) {
318 assert(format == VC4_TEXTURE_TYPE_RGBA8888);
319 return VC4_TEXTURE_TYPE_RGBA32R;
320 }
321
322 return format;
323 }
324
325 struct pipe_resource *
326 vc4_resource_create(struct pipe_screen *pscreen,
327 const struct pipe_resource *tmpl)
328 {
329 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
330 struct pipe_resource *prsc = &rsc->base.b;
331
332 /* We have to make shared be untiled, since we don't have any way to
333 * communicate metadata about tiling currently.
334 */
335 if (tmpl->target == PIPE_BUFFER ||
336 (tmpl->bind & (PIPE_BIND_SCANOUT |
337 PIPE_BIND_LINEAR |
338 PIPE_BIND_SHARED |
339 PIPE_BIND_CURSOR))) {
340 rsc->tiled = false;
341 } else {
342 rsc->tiled = true;
343 }
344
345 vc4_setup_slices(rsc);
346 vc4_resource_bo_alloc(rsc);
347 if (!rsc->bo)
348 goto fail;
349
350 if (tmpl->target != PIPE_BUFFER)
351 rsc->vc4_format = get_resource_texture_format(prsc);
352
353 return prsc;
354 fail:
355 vc4_resource_destroy(pscreen, prsc);
356 return NULL;
357 }
358
359 static struct pipe_resource *
360 vc4_resource_from_handle(struct pipe_screen *pscreen,
361 const struct pipe_resource *tmpl,
362 struct winsys_handle *handle)
363 {
364 struct vc4_resource *rsc = vc4_resource_setup(pscreen, tmpl);
365 struct pipe_resource *prsc = &rsc->base.b;
366 struct vc4_resource_slice *slice = &rsc->slices[0];
367
368 if (!rsc)
369 return NULL;
370
371 rsc->tiled = false;
372 rsc->bo = vc4_screen_bo_from_handle(pscreen, handle, &slice->stride);
373 if (!rsc->bo)
374 goto fail;
375
376 #ifdef USE_VC4_SIMULATOR
377 slice->stride = align(prsc->width0 * rsc->cpp, 16);
378 #endif
379 slice->tiling = VC4_TILING_FORMAT_LINEAR;
380
381 rsc->vc4_format = get_resource_texture_format(prsc);
382
383 return prsc;
384
385 fail:
386 vc4_resource_destroy(pscreen, prsc);
387 return NULL;
388 }
389
390 static struct pipe_surface *
391 vc4_create_surface(struct pipe_context *pctx,
392 struct pipe_resource *ptex,
393 const struct pipe_surface *surf_tmpl)
394 {
395 struct vc4_surface *surface = CALLOC_STRUCT(vc4_surface);
396 struct vc4_resource *rsc = vc4_resource(ptex);
397
398 if (!surface)
399 return NULL;
400
401 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
402
403 struct pipe_surface *psurf = &surface->base;
404 unsigned level = surf_tmpl->u.tex.level;
405
406 pipe_reference_init(&psurf->reference, 1);
407 pipe_resource_reference(&psurf->texture, ptex);
408
409 psurf->context = pctx;
410 psurf->format = surf_tmpl->format;
411 psurf->width = u_minify(ptex->width0, level);
412 psurf->height = u_minify(ptex->height0, level);
413 psurf->u.tex.level = level;
414 psurf->u.tex.first_layer = surf_tmpl->u.tex.first_layer;
415 psurf->u.tex.last_layer = surf_tmpl->u.tex.last_layer;
416 surface->offset = rsc->slices[level].offset;
417 surface->tiling = rsc->slices[level].tiling;
418
419 return &surface->base;
420 }
421
422 static void
423 vc4_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
424 {
425 pipe_resource_reference(&psurf->texture, NULL);
426 FREE(psurf);
427 }
428
429 static void
430 vc4_flush_resource(struct pipe_context *pctx, struct pipe_resource *resource)
431 {
432 struct vc4_context *vc4 = vc4_context(pctx);
433
434 /* XXX: Skip this if we don't have any queued drawing to it. */
435 vc4->base.flush(pctx, NULL, 0);
436 }
437 static bool
438 render_blit(struct pipe_context *ctx, struct pipe_blit_info *info)
439 {
440 struct vc4_context *vc4 = vc4_context(ctx);
441
442 if (!util_blitter_is_blit_supported(vc4->blitter, info)) {
443 fprintf(stderr, "blit unsupported %s -> %s",
444 util_format_short_name(info->src.resource->format),
445 util_format_short_name(info->dst.resource->format));
446 return false;
447 }
448
449 util_blitter_save_vertex_buffer_slot(vc4->blitter, vc4->vertexbuf.vb);
450 util_blitter_save_vertex_elements(vc4->blitter, vc4->vtx);
451 util_blitter_save_vertex_shader(vc4->blitter, vc4->prog.bind_vs);
452 util_blitter_save_rasterizer(vc4->blitter, vc4->rasterizer);
453 util_blitter_save_viewport(vc4->blitter, &vc4->viewport);
454 util_blitter_save_scissor(vc4->blitter, &vc4->scissor);
455 util_blitter_save_fragment_shader(vc4->blitter, vc4->prog.bind_fs);
456 util_blitter_save_blend(vc4->blitter, vc4->blend);
457 util_blitter_save_depth_stencil_alpha(vc4->blitter, vc4->zsa);
458 util_blitter_save_stencil_ref(vc4->blitter, &vc4->stencil_ref);
459 util_blitter_save_sample_mask(vc4->blitter, vc4->sample_mask);
460 util_blitter_save_framebuffer(vc4->blitter, &vc4->framebuffer);
461 util_blitter_save_fragment_sampler_states(vc4->blitter,
462 vc4->fragtex.num_samplers,
463 (void **)vc4->fragtex.samplers);
464 util_blitter_save_fragment_sampler_views(vc4->blitter,
465 vc4->fragtex.num_textures, vc4->fragtex.textures);
466
467 util_blitter_blit(vc4->blitter, info);
468
469 return true;
470 }
471
472 /* Optimal hardware path for blitting pixels.
473 * Scaling, format conversion, up- and downsampling (resolve) are allowed.
474 */
475 static void
476 vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
477 {
478 struct pipe_blit_info info = *blit_info;
479
480 if (info.src.resource->nr_samples > 1 &&
481 info.dst.resource->nr_samples <= 1 &&
482 !util_format_is_depth_or_stencil(info.src.resource->format) &&
483 !util_format_is_pure_integer(info.src.resource->format)) {
484 fprintf(stderr, "color resolve unimplemented");
485 return;
486 }
487
488 if (util_try_blit_via_copy_region(pctx, &info)) {
489 return; /* done */
490 }
491
492 if (info.mask & PIPE_MASK_S) {
493 fprintf(stderr, "cannot blit stencil, skipping");
494 info.mask &= ~PIPE_MASK_S;
495 }
496
497 render_blit(pctx, &info);
498 }
499
500 void
501 vc4_update_shadow_baselevel_texture(struct pipe_context *pctx,
502 struct pipe_sampler_view *view)
503 {
504 struct vc4_resource *shadow = vc4_resource(view->texture);
505 struct vc4_resource *orig = vc4_resource(shadow->shadow_parent);
506 assert(orig);
507
508 if (shadow->writes == orig->writes)
509 return;
510
511 for (int i = 0; i <= shadow->base.b.last_level; i++) {
512 struct pipe_box box = {
513 .x = 0,
514 .y = 0,
515 .z = 0,
516 .width = u_minify(shadow->base.b.width0, i),
517 .height = u_minify(shadow->base.b.height0, i),
518 .depth = 1,
519 };
520
521 util_resource_copy_region(pctx,
522 &shadow->base.b, i, 0, 0, 0,
523 &orig->base.b,
524 view->u.tex.first_level + i,
525 &box);
526 }
527
528 shadow->writes = orig->writes;
529 }
530
531 /**
532 * Converts a 4-byte index buffer to 2 bytes.
533 *
534 * Since GLES2 only has support for 1 and 2-byte indices, the hardware doesn't
535 * include 4-byte index support, and we have to shrink it down.
536 *
537 * There's no fallback support for when indices end up being larger than 2^16,
538 * though it will at least assertion fail. Also, if the original index data
539 * was in user memory, it would be nice to not have uploaded it to a VBO
540 * before translating.
541 */
542 void
543 vc4_update_shadow_index_buffer(struct pipe_context *pctx,
544 const struct pipe_index_buffer *ib)
545 {
546 struct vc4_resource *shadow = vc4_resource(ib->buffer);
547 struct vc4_resource *orig = vc4_resource(shadow->shadow_parent);
548 uint32_t count = shadow->base.b.width0 / 2;
549
550 if (shadow->writes == orig->writes)
551 return;
552
553 struct pipe_transfer *src_transfer;
554 uint32_t *src = pipe_buffer_map_range(pctx, &orig->base.b,
555 ib->offset,
556 count * 4,
557 PIPE_TRANSFER_READ, &src_transfer);
558
559 struct pipe_transfer *dst_transfer;
560 uint16_t *dst = pipe_buffer_map_range(pctx, &shadow->base.b,
561 0,
562 count * 2,
563 PIPE_TRANSFER_WRITE, &dst_transfer);
564
565 for (int i = 0; i < count; i++) {
566 uint32_t src_index = src[i];
567 assert(src_index <= 0xffff);
568 dst[i] = src_index;
569 }
570
571 pctx->transfer_unmap(pctx, dst_transfer);
572 pctx->transfer_unmap(pctx, src_transfer);
573
574 shadow->writes = orig->writes;
575 }
576
577 void
578 vc4_resource_screen_init(struct pipe_screen *pscreen)
579 {
580 pscreen->resource_create = vc4_resource_create;
581 pscreen->resource_from_handle = vc4_resource_from_handle;
582 pscreen->resource_get_handle = u_resource_get_handle_vtbl;
583 pscreen->resource_destroy = u_resource_destroy_vtbl;
584 }
585
586 void
587 vc4_resource_context_init(struct pipe_context *pctx)
588 {
589 pctx->transfer_map = u_transfer_map_vtbl;
590 pctx->transfer_flush_region = u_transfer_flush_region_vtbl;
591 pctx->transfer_unmap = u_transfer_unmap_vtbl;
592 pctx->transfer_inline_write = u_transfer_inline_write_vtbl;
593 pctx->create_surface = vc4_create_surface;
594 pctx->surface_destroy = vc4_surface_destroy;
595 pctx->resource_copy_region = util_resource_copy_region;
596 pctx->blit = vc4_blit;
597 pctx->flush_resource = vc4_flush_resource;
598 }