src/gallium/drivers/vc4/vc4_screen.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "os/os_misc.h"
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_screen.h"
  28 #include "pipe/p_state.h"
  29
  30 #include "util/u_debug.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_format.h"
  33 #include "util/u_hash_table.h"
  34 #include "util/ralloc.h"
  35
  36 #include <xf86drm.h>
  37 #include "vc4_drm.h"
  38 #include "vc4_screen.h"
  39 #include "vc4_context.h"
  40 #include "vc4_resource.h"
  41
  42 static const struct debug_named_value debug_options[] = {
  43         { "cl",       VC4_DEBUG_CL,
  44           "Dump command list during creation" },
  45         { "qpu",      VC4_DEBUG_QPU,
  46           "Dump generated QPU instructions" },
  47         { "qir",      VC4_DEBUG_QIR,
  48           "Dump QPU IR during program compile" },
  49         { "nir",      VC4_DEBUG_NIR,
  50           "Dump NIR during program compile" },
  51         { "tgsi",     VC4_DEBUG_TGSI,
  52           "Dump TGSI during program compile" },
  53         { "shaderdb", VC4_DEBUG_SHADERDB,
  54           "Dump program compile information for shader-db analysis" },
  55         { "perf",     VC4_DEBUG_PERF,
  56           "Print during performance-related events" },
  57         { "norast",   VC4_DEBUG_NORAST,
  58           "Skip actual hardware execution of commands" },
  59         { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
  60           "Flush after each draw call" },
  61         { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
  62           "Wait for finish after each flush" },
  63 #if USE_VC4_SIMULATOR
  64         { "dump", VC4_DEBUG_DUMP,
  65           "Write a GPU command stream trace file" },
  66 #endif
  67         { NULL }
  68 };
  69
  70 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
  71 uint32_t vc4_debug;
  72
  73 static const char *
  74 vc4_screen_get_name(struct pipe_screen *pscreen)
  75 {
  76         struct vc4_screen *screen = vc4_screen(pscreen);
  77
  78         if (!screen->name) {
  79                 screen->name = ralloc_asprintf(screen,
  80                                                "VC4 V3D %d.%d",
  81                                                screen->v3d_ver / 10,
  82                                                screen->v3d_ver % 10);
  83         }
  84
  85         return screen->name;
  86 }
  87
  88 static const char *
  89 vc4_screen_get_vendor(struct pipe_screen *pscreen)
  90 {
  91         return "Broadcom";
  92 }
  93
  94 static void
  95 vc4_screen_destroy(struct pipe_screen *pscreen)
  96 {
  97         struct vc4_screen *screen = vc4_screen(pscreen);
  98
  99         util_hash_table_destroy(screen->bo_handles);
 100         vc4_bufmgr_destroy(pscreen);
 101         close(screen->fd);
 102         ralloc_free(pscreen);
 103 }
 104
 105 static int
 106 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 107 {
 108         switch (param) {
 109                 /* Supported features (boolean caps). */
 110         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 111         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 112         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 113         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 114         case PIPE_CAP_NPOT_TEXTURES:
 115         case PIPE_CAP_SHAREABLE_SHADERS:
 116         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 117         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 118         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 119         case PIPE_CAP_TWO_SIDED_STENCIL:
 120         case PIPE_CAP_USER_INDEX_BUFFERS:
 121         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 122         case PIPE_CAP_TEXTURE_SWIZZLE:
 123                 return 1;
 124
 125                 /* lying for GL 2.0 */
 126         case PIPE_CAP_OCCLUSION_QUERY:
 127         case PIPE_CAP_POINT_SPRITE:
 128                 return 1;
 129
 130         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 131                 return 256;
 132
 133         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 134                 return 120;
 135
 136         case PIPE_CAP_MAX_VIEWPORTS:
 137                 return 1;
 138
 139         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 140         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 141                 return 1;
 142
 143         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 144         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 145                 return 1;
 146
 147                 /* Unsupported features. */
 148         case PIPE_CAP_ANISOTROPIC_FILTER:
 149         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 150         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 151         case PIPE_CAP_CUBE_MAP_ARRAY:
 152         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 153         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 154         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 155         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 156         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 157         case PIPE_CAP_TGSI_INSTANCEID:
 158         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 159         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 160         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 161         case PIPE_CAP_COMPUTE:
 162         case PIPE_CAP_START_INSTANCE:
 163         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 164         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 165         case PIPE_CAP_TGSI_TEXCOORD:
 166         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 167         case PIPE_CAP_CONDITIONAL_RENDER:
 168         case PIPE_CAP_PRIMITIVE_RESTART:
 169         case PIPE_CAP_TEXTURE_BARRIER:
 170         case PIPE_CAP_SM3:
 171         case PIPE_CAP_INDEP_BLEND_ENABLE:
 172         case PIPE_CAP_INDEP_BLEND_FUNC:
 173         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 174         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 175         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 176         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 177         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 178         case PIPE_CAP_USER_VERTEX_BUFFERS:
 179         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 180         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 181         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 182         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 183         case PIPE_CAP_TEXTURE_GATHER_SM5:
 184         case PIPE_CAP_FAKE_SW_MSAA:
 185         case PIPE_CAP_TEXTURE_QUERY_LOD:
 186         case PIPE_CAP_SAMPLE_SHADING:
 187         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 188         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 189         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 190         case PIPE_CAP_MAX_TEXEL_OFFSET:
 191         case PIPE_CAP_MAX_VERTEX_STREAMS:
 192         case PIPE_CAP_DRAW_INDIRECT:
 193         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 194         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 195         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 196         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 197         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 198         case PIPE_CAP_CLIP_HALFZ:
 199         case PIPE_CAP_VERTEXID_NOBASE:
 200         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 201         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 202         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 203         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 204         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 205         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 206         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 207         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 208         case PIPE_CAP_TGSI_TXQS:
 209         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 210         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 211         case PIPE_CAP_CLEAR_TEXTURE:
 212         case PIPE_CAP_DRAW_PARAMETERS:
 213         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 214         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 215         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 216         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 217         case PIPE_CAP_INVALIDATE_BUFFER:
 218         case PIPE_CAP_GENERATE_MIPMAP:
 219         case PIPE_CAP_STRING_MARKER:
 220         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 221         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 222         case PIPE_CAP_QUERY_MEMORY_INFO:
 223         case PIPE_CAP_PCI_GROUP:
 224         case PIPE_CAP_PCI_BUS:
 225         case PIPE_CAP_PCI_DEVICE:
 226         case PIPE_CAP_PCI_FUNCTION:
 227         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 228         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 229         case PIPE_CAP_CULL_DISTANCE:
 230         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 231         case PIPE_CAP_TGSI_VOTE:
 232         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 233         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 234         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 235                 return 0;
 236
 237                 /* Stream output. */
 238         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 239         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 240         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 241         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 242                 return 0;
 243
 244                 /* Geometry shader output, unsupported. */
 245         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 246         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 247                 return 0;
 248
 249                 /* Texturing. */
 250         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 251         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 252                 return VC4_MAX_MIP_LEVELS;
 253         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 254                 /* Note: Not supported in hardware, just faking it. */
 255                 return 5;
 256         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 257                 return 0;
 258
 259                 /* Render targets. */
 260         case PIPE_CAP_MAX_RENDER_TARGETS:
 261                 return 1;
 262
 263                 /* Queries. */
 264         case PIPE_CAP_QUERY_TIME_ELAPSED:
 265         case PIPE_CAP_QUERY_TIMESTAMP:
 266                 return 0;
 267
 268         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 269         case PIPE_CAP_MIN_TEXEL_OFFSET:
 270                 return 0;
 271
 272         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 273                 return 2048;
 274
 275         case PIPE_CAP_ENDIANNESS:
 276                 return PIPE_ENDIAN_LITTLE;
 277
 278         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 279                 return 64;
 280
 281         case PIPE_CAP_VENDOR_ID:
 282                 return 0x14E4;
 283         case PIPE_CAP_DEVICE_ID:
 284                 return 0xFFFFFFFF;
 285         case PIPE_CAP_ACCELERATED:
 286                 return 1;
 287         case PIPE_CAP_VIDEO_MEMORY: {
 288                 uint64_t system_memory;
 289
 290                 if (!os_get_total_physical_memory(&system_memory))
 291                         return 0;
 292
 293                 return (int)(system_memory >> 20);
 294         }
 295         case PIPE_CAP_UMA:
 296                 return 1;
 297
 298         default:
 299                 fprintf(stderr, "unknown param %d\n", param);
 300                 return 0;
 301         }
 302 }
 303
 304 static float
 305 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 306 {
 307         switch (param) {
 308         case PIPE_CAPF_MAX_LINE_WIDTH:
 309         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 310                 return 32;
 311
 312         case PIPE_CAPF_MAX_POINT_WIDTH:
 313         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 314                 return 512.0f;
 315
 316         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 317                 return 0.0f;
 318         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 319                 return 0.0f;
 320         case PIPE_CAPF_GUARD_BAND_LEFT:
 321         case PIPE_CAPF_GUARD_BAND_TOP:
 322         case PIPE_CAPF_GUARD_BAND_RIGHT:
 323         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 324                 return 0.0f;
 325         default:
 326                 fprintf(stderr, "unknown paramf %d\n", param);
 327                 return 0;
 328         }
 329 }
 330
 331 static int
 332 vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
 333                            enum pipe_shader_cap param)
 334 {
 335         if (shader != PIPE_SHADER_VERTEX &&
 336             shader != PIPE_SHADER_FRAGMENT) {
 337                 return 0;
 338         }
 339
 340         /* this is probably not totally correct.. but it's a start: */
 341         switch (param) {
 342         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 343         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 344         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 345         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 346                 return 16384;
 347
 348         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 349                 return vc4_screen(pscreen)->has_control_flow;
 350
 351         case PIPE_SHADER_CAP_MAX_INPUTS:
 352                 if (shader == PIPE_SHADER_FRAGMENT)
 353                         return 8;
 354                 else
 355                         return 16;
 356         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 357                 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
 358         case PIPE_SHADER_CAP_MAX_TEMPS:
 359                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 360         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 361                 return 16 * 1024 * sizeof(float);
 362         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 363                 return 1;
 364         case PIPE_SHADER_CAP_MAX_PREDS:
 365                 return 0; /* nothing uses this */
 366         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 367                 return 0;
 368         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 369         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 370         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 371                 return 0;
 372         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 373                 return 1;
 374         case PIPE_SHADER_CAP_SUBROUTINES:
 375                 return 0;
 376         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 377                 return 0;
 378         case PIPE_SHADER_CAP_INTEGERS:
 379                 return 1;
 380         case PIPE_SHADER_CAP_DOUBLES:
 381         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 382         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 383         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 384         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 385                 return 0;
 386         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 387         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 388                 return VC4_MAX_TEXTURE_SAMPLERS;
 389         case PIPE_SHADER_CAP_PREFERRED_IR:
 390                 return PIPE_SHADER_IR_NIR;
 391         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 392                 return 0;
 393         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 394                 return 32;
 395         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 396         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 397                 return 0;
 398         default:
 399                 fprintf(stderr, "unknown shader param %d\n", param);
 400                 return 0;
 401         }
 402         return 0;
 403 }
 404
 405 static boolean
 406 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
 407                                enum pipe_format format,
 408                                enum pipe_texture_target target,
 409                                unsigned sample_count,
 410                                unsigned usage)
 411 {
 412         unsigned retval = 0;
 413
 414         if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
 415                 return FALSE;
 416
 417         if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
 418             !util_format_is_supported(format, usage)) {
 419                 return FALSE;
 420         }
 421
 422         if (usage & PIPE_BIND_VERTEX_BUFFER) {
 423                 switch (format) {
 424                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 425                 case PIPE_FORMAT_R32G32B32_FLOAT:
 426                 case PIPE_FORMAT_R32G32_FLOAT:
 427                 case PIPE_FORMAT_R32_FLOAT:
 428                 case PIPE_FORMAT_R32G32B32A32_SNORM:
 429                 case PIPE_FORMAT_R32G32B32_SNORM:
 430                 case PIPE_FORMAT_R32G32_SNORM:
 431                 case PIPE_FORMAT_R32_SNORM:
 432                 case PIPE_FORMAT_R32G32B32A32_SSCALED:
 433                 case PIPE_FORMAT_R32G32B32_SSCALED:
 434                 case PIPE_FORMAT_R32G32_SSCALED:
 435                 case PIPE_FORMAT_R32_SSCALED:
 436                 case PIPE_FORMAT_R16G16B16A16_UNORM:
 437                 case PIPE_FORMAT_R16G16B16_UNORM:
 438                 case PIPE_FORMAT_R16G16_UNORM:
 439                 case PIPE_FORMAT_R16_UNORM:
 440                 case PIPE_FORMAT_R16G16B16A16_SNORM:
 441                 case PIPE_FORMAT_R16G16B16_SNORM:
 442                 case PIPE_FORMAT_R16G16_SNORM:
 443                 case PIPE_FORMAT_R16_SNORM:
 444                 case PIPE_FORMAT_R16G16B16A16_USCALED:
 445                 case PIPE_FORMAT_R16G16B16_USCALED:
 446                 case PIPE_FORMAT_R16G16_USCALED:
 447                 case PIPE_FORMAT_R16_USCALED:
 448                 case PIPE_FORMAT_R16G16B16A16_SSCALED:
 449                 case PIPE_FORMAT_R16G16B16_SSCALED:
 450                 case PIPE_FORMAT_R16G16_SSCALED:
 451                 case PIPE_FORMAT_R16_SSCALED:
 452                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 453                 case PIPE_FORMAT_R8G8B8_UNORM:
 454                 case PIPE_FORMAT_R8G8_UNORM:
 455                 case PIPE_FORMAT_R8_UNORM:
 456                 case PIPE_FORMAT_R8G8B8A8_SNORM:
 457                 case PIPE_FORMAT_R8G8B8_SNORM:
 458                 case PIPE_FORMAT_R8G8_SNORM:
 459                 case PIPE_FORMAT_R8_SNORM:
 460                 case PIPE_FORMAT_R8G8B8A8_USCALED:
 461                 case PIPE_FORMAT_R8G8B8_USCALED:
 462                 case PIPE_FORMAT_R8G8_USCALED:
 463                 case PIPE_FORMAT_R8_USCALED:
 464                 case PIPE_FORMAT_R8G8B8A8_SSCALED:
 465                 case PIPE_FORMAT_R8G8B8_SSCALED:
 466                 case PIPE_FORMAT_R8G8_SSCALED:
 467                 case PIPE_FORMAT_R8_SSCALED:
 468                         retval |= PIPE_BIND_VERTEX_BUFFER;
 469                         break;
 470                 default:
 471                         break;
 472                 }
 473         }
 474
 475         if ((usage & PIPE_BIND_RENDER_TARGET) &&
 476             vc4_rt_format_supported(format)) {
 477                 retval |= PIPE_BIND_RENDER_TARGET;
 478         }
 479
 480         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 481             vc4_tex_format_supported(format)) {
 482                 retval |= PIPE_BIND_SAMPLER_VIEW;
 483         }
 484
 485         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 486             (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
 487              format == PIPE_FORMAT_X8Z24_UNORM)) {
 488                 retval |= PIPE_BIND_DEPTH_STENCIL;
 489         }
 490
 491         if ((usage & PIPE_BIND_INDEX_BUFFER) &&
 492             (format == PIPE_FORMAT_I8_UINT ||
 493              format == PIPE_FORMAT_I16_UINT)) {
 494                 retval |= PIPE_BIND_INDEX_BUFFER;
 495         }
 496
 497 #if 0
 498         if (retval != usage) {
 499                 fprintf(stderr,
 500                         "not supported: format=%s, target=%d, sample_count=%d, "
 501                         "usage=0x%x, retval=0x%x\n", util_format_name(format),
 502                         target, sample_count, usage, retval);
 503         }
 504 #endif
 505
 506         return retval == usage;
 507 }
 508
 509 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 510
 511 static unsigned handle_hash(void *key)
 512 {
 513     return PTR_TO_UINT(key);
 514 }
 515
 516 static int handle_compare(void *key1, void *key2)
 517 {
 518     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 519 }
 520
 521 static bool
 522 vc4_supports_branches(struct vc4_screen *screen)
 523 {
 524 #if USE_VC4_SIMULATOR
 525         return true;
 526 #endif
 527
 528         struct drm_vc4_get_param p = {
 529                 .param = DRM_VC4_PARAM_SUPPORTS_BRANCHES,
 530         };
 531         int ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
 532
 533         if (ret != 0)
 534                 return false;
 535
 536         return p.value;
 537 }
 538
 539 static bool
 540 vc4_get_chip_info(struct vc4_screen *screen)
 541 {
 542 #if USE_VC4_SIMULATOR
 543         screen->v3d_ver = 21;
 544         return true;
 545 #endif
 546
 547         struct drm_vc4_get_param ident0 = {
 548                 .param = DRM_VC4_PARAM_V3D_IDENT0,
 549         };
 550         struct drm_vc4_get_param ident1 = {
 551                 .param = DRM_VC4_PARAM_V3D_IDENT1,
 552         };
 553         int ret;
 554
 555         ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
 556         if (ret != 0) {
 557                 if (errno == EINVAL) {
 558                         /* Backwards compatibility with 2835 kernels which
 559                          * only do V3D 2.1.
 560                          */
 561                         screen->v3d_ver = 21;
 562                         return true;
 563                 } else {
 564                         fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
 565                                 strerror(errno));
 566                         return false;
 567                 }
 568         }
 569         ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
 570         if (ret != 0) {
 571                 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
 572                         strerror(errno));
 573                 return false;
 574         }
 575
 576         uint32_t major = (ident0.value >> 24) & 0xff;
 577         uint32_t minor = (ident1.value >> 0) & 0xf;
 578         screen->v3d_ver = major * 10 + minor;
 579
 580         if (screen->v3d_ver != 21) {
 581                 fprintf(stderr,
 582                         "V3D %d.%d not supported by this version of Mesa.\n",
 583                         screen->v3d_ver / 10,
 584                         screen->v3d_ver % 10);
 585                 return false;
 586         }
 587
 588         return true;
 589 }
 590
 591 struct pipe_screen *
 592 vc4_screen_create(int fd)
 593 {
 594         struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
 595         struct pipe_screen *pscreen;
 596
 597         pscreen = &screen->base;
 598
 599         pscreen->destroy = vc4_screen_destroy;
 600         pscreen->get_param = vc4_screen_get_param;
 601         pscreen->get_paramf = vc4_screen_get_paramf;
 602         pscreen->get_shader_param = vc4_screen_get_shader_param;
 603         pscreen->context_create = vc4_context_create;
 604         pscreen->is_format_supported = vc4_screen_is_format_supported;
 605
 606         screen->fd = fd;
 607         list_inithead(&screen->bo_cache.time_list);
 608         pipe_mutex_init(screen->bo_handles_mutex);
 609         screen->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 610
 611         if (vc4_supports_branches(screen))
 612                 screen->has_control_flow = true;
 613
 614         if (!vc4_get_chip_info(screen))
 615                 goto fail;
 616
 617         vc4_fence_init(screen);
 618
 619         vc4_debug = debug_get_option_vc4_debug();
 620         if (vc4_debug & VC4_DEBUG_SHADERDB)
 621                 vc4_debug |= VC4_DEBUG_NORAST;
 622
 623 #if USE_VC4_SIMULATOR
 624         vc4_simulator_init(screen);
 625 #endif
 626
 627         vc4_resource_screen_init(pscreen);
 628
 629         pscreen->get_name = vc4_screen_get_name;
 630         pscreen->get_vendor = vc4_screen_get_vendor;
 631         pscreen->get_device_vendor = vc4_screen_get_vendor;
 632         pscreen->get_compiler_options = vc4_screen_get_compiler_options;
 633
 634         return pscreen;
 635
 636 fail:
 637         close(fd);
 638         ralloc_free(pscreen);
 639         return NULL;
 640 }
 641
 642 boolean
 643 vc4_screen_bo_get_handle(struct pipe_screen *pscreen,
 644                          struct vc4_bo *bo,
 645                          unsigned stride,
 646                          struct winsys_handle *whandle)
 647 {
 648         whandle->stride = stride;
 649
 650         /* If we're passing some reference to our BO out to some other part of
 651          * the system, then we can't do any optimizations about only us being
 652          * the ones seeing it (like BO caching or shadow update avoidance).
 653          */
 654         bo->private = false;
 655
 656         switch (whandle->type) {
 657         case DRM_API_HANDLE_TYPE_SHARED:
 658                 return vc4_bo_flink(bo, &whandle->handle);
 659         case DRM_API_HANDLE_TYPE_KMS:
 660                 whandle->handle = bo->handle;
 661                 return TRUE;
 662         case DRM_API_HANDLE_TYPE_FD:
 663                 whandle->handle = vc4_bo_get_dmabuf(bo);
 664                 return whandle->handle != -1;
 665         }
 666
 667         return FALSE;
 668 }
 669
 670 struct vc4_bo *
 671 vc4_screen_bo_from_handle(struct pipe_screen *pscreen,
 672                           struct winsys_handle *whandle)
 673 {
 674         struct vc4_screen *screen = vc4_screen(pscreen);
 675
 676         if (whandle->offset != 0) {
 677                 fprintf(stderr,
 678                         "Attempt to import unsupported winsys offset %u\n",
 679                         whandle->offset);
 680                 return NULL;
 681         }
 682
 683         switch (whandle->type) {
 684         case DRM_API_HANDLE_TYPE_SHARED:
 685                 return vc4_bo_open_name(screen, whandle->handle, whandle->stride);
 686         case DRM_API_HANDLE_TYPE_FD:
 687                 return vc4_bo_open_dmabuf(screen, whandle->handle, whandle->stride);
 688         default:
 689                 fprintf(stderr,
 690                         "Attempt to import unsupported handle type %d\n",
 691                         whandle->type);
 692                 return NULL;
 693         }
 694 }