src/gallium/drivers/vc4/vc4_screen.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "os/os_misc.h"
  26 #include "pipe/p_defines.h"
  27 #include "pipe/p_screen.h"
  28 #include "pipe/p_state.h"
  29
  30 #include "util/u_cpu_detect.h"
  31 #include "util/u_debug.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_format.h"
  34 #include "util/u_hash_table.h"
  35 #include "util/ralloc.h"
  36
  37 #include <xf86drm.h>
  38 #include "vc4_drm.h"
  39 #include "vc4_screen.h"
  40 #include "vc4_context.h"
  41 #include "vc4_resource.h"
  42
  43 static const struct debug_named_value debug_options[] = {
  44         { "cl",       VC4_DEBUG_CL,
  45           "Dump command list during creation" },
  46         { "qpu",      VC4_DEBUG_QPU,
  47           "Dump generated QPU instructions" },
  48         { "qir",      VC4_DEBUG_QIR,
  49           "Dump QPU IR during program compile" },
  50         { "nir",      VC4_DEBUG_NIR,
  51           "Dump NIR during program compile" },
  52         { "tgsi",     VC4_DEBUG_TGSI,
  53           "Dump TGSI during program compile" },
  54         { "shaderdb", VC4_DEBUG_SHADERDB,
  55           "Dump program compile information for shader-db analysis" },
  56         { "perf",     VC4_DEBUG_PERF,
  57           "Print during performance-related events" },
  58         { "norast",   VC4_DEBUG_NORAST,
  59           "Skip actual hardware execution of commands" },
  60         { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
  61           "Flush after each draw call" },
  62         { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
  63           "Wait for finish after each flush" },
  64 #if USE_VC4_SIMULATOR
  65         { "dump", VC4_DEBUG_DUMP,
  66           "Write a GPU command stream trace file" },
  67 #endif
  68         { NULL }
  69 };
  70
  71 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
  72 uint32_t vc4_debug;
  73
  74 static const char *
  75 vc4_screen_get_name(struct pipe_screen *pscreen)
  76 {
  77         struct vc4_screen *screen = vc4_screen(pscreen);
  78
  79         if (!screen->name) {
  80                 screen->name = ralloc_asprintf(screen,
  81                                                "VC4 V3D %d.%d",
  82                                                screen->v3d_ver / 10,
  83                                                screen->v3d_ver % 10);
  84         }
  85
  86         return screen->name;
  87 }
  88
  89 static const char *
  90 vc4_screen_get_vendor(struct pipe_screen *pscreen)
  91 {
  92         return "Broadcom";
  93 }
  94
  95 static void
  96 vc4_screen_destroy(struct pipe_screen *pscreen)
  97 {
  98         struct vc4_screen *screen = vc4_screen(pscreen);
  99
 100         util_hash_table_destroy(screen->bo_handles);
 101         vc4_bufmgr_destroy(pscreen);
 102         slab_destroy_parent(&screen->transfer_pool);
 103         free(screen->ro);
 104
 105 #if USE_VC4_SIMULATOR
 106         vc4_simulator_destroy(screen);
 107 #endif
 108
 109         close(screen->fd);
 110         ralloc_free(pscreen);
 111 }
 112
 113 static int
 114 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
 115 {
 116         switch (param) {
 117                 /* Supported features (boolean caps). */
 118         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 119         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 120         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 121         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 122         case PIPE_CAP_NPOT_TEXTURES:
 123         case PIPE_CAP_SHAREABLE_SHADERS:
 124         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 125         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 126         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 127         case PIPE_CAP_TWO_SIDED_STENCIL:
 128         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 129         case PIPE_CAP_TEXTURE_SWIZZLE:
 130         case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
 131         case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
 132                 return 1;
 133
 134                 /* lying for GL 2.0 */
 135         case PIPE_CAP_OCCLUSION_QUERY:
 136         case PIPE_CAP_POINT_SPRITE:
 137                 return 1;
 138
 139         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 140                 return 256;
 141
 142         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 143                 return 120;
 144
 145         case PIPE_CAP_MAX_VIEWPORTS:
 146                 return 1;
 147
 148         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 149         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 150                 return 1;
 151
 152         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 153         case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
 154                 return 1;
 155
 156                 /* Unsupported features. */
 157         case PIPE_CAP_ANISOTROPIC_FILTER:
 158         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 159         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 160         case PIPE_CAP_CUBE_MAP_ARRAY:
 161         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 162         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 163         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 164         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 165         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 166         case PIPE_CAP_TGSI_INSTANCEID:
 167         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 168         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 169         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 170         case PIPE_CAP_COMPUTE:
 171         case PIPE_CAP_START_INSTANCE:
 172         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 173         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 174         case PIPE_CAP_TGSI_TEXCOORD:
 175         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 176         case PIPE_CAP_CONDITIONAL_RENDER:
 177         case PIPE_CAP_PRIMITIVE_RESTART:
 178         case PIPE_CAP_TEXTURE_BARRIER:
 179         case PIPE_CAP_SM3:
 180         case PIPE_CAP_INDEP_BLEND_ENABLE:
 181         case PIPE_CAP_INDEP_BLEND_FUNC:
 182         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 183         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 184         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 185         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 186         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 187         case PIPE_CAP_USER_VERTEX_BUFFERS:
 188         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 189         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 190         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 191         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 192         case PIPE_CAP_TEXTURE_GATHER_SM5:
 193         case PIPE_CAP_FAKE_SW_MSAA:
 194         case PIPE_CAP_TEXTURE_QUERY_LOD:
 195         case PIPE_CAP_SAMPLE_SHADING:
 196         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 197         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 198         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 199         case PIPE_CAP_MAX_TEXEL_OFFSET:
 200         case PIPE_CAP_MAX_VERTEX_STREAMS:
 201         case PIPE_CAP_DRAW_INDIRECT:
 202         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 203         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 204         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 205         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 206         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 207         case PIPE_CAP_CLIP_HALFZ:
 208         case PIPE_CAP_VERTEXID_NOBASE:
 209         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 210         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 211         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 212         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 213         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 214         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 215         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 216         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 217         case PIPE_CAP_TGSI_TXQS:
 218         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 219         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 220         case PIPE_CAP_CLEAR_TEXTURE:
 221         case PIPE_CAP_DRAW_PARAMETERS:
 222         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 223         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 224         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 225         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 226         case PIPE_CAP_INVALIDATE_BUFFER:
 227         case PIPE_CAP_GENERATE_MIPMAP:
 228         case PIPE_CAP_STRING_MARKER:
 229         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 230         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 231         case PIPE_CAP_QUERY_MEMORY_INFO:
 232         case PIPE_CAP_PCI_GROUP:
 233         case PIPE_CAP_PCI_BUS:
 234         case PIPE_CAP_PCI_DEVICE:
 235         case PIPE_CAP_PCI_FUNCTION:
 236         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 237         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 238         case PIPE_CAP_CULL_DISTANCE:
 239         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 240         case PIPE_CAP_TGSI_VOTE:
 241         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 242         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 243         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 244         case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
 245         case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
 246         case PIPE_CAP_NATIVE_FENCE_FD:
 247         case PIPE_CAP_TGSI_FS_FBFETCH:
 248         case PIPE_CAP_TGSI_MUL_ZERO_WINS:
 249         case PIPE_CAP_DOUBLES:
 250         case PIPE_CAP_INT64:
 251         case PIPE_CAP_INT64_DIVMOD:
 252         case PIPE_CAP_TGSI_TEX_TXF_LZ:
 253         case PIPE_CAP_TGSI_CLOCK:
 254         case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
 255         case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
 256         case PIPE_CAP_TGSI_BALLOT:
 257         case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
 258         case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
 259         case PIPE_CAP_POST_DEPTH_COVERAGE:
 260         case PIPE_CAP_BINDLESS_TEXTURE:
 261                 return 0;
 262
 263                 /* Stream output. */
 264         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 265         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 266         case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
 267         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 268         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 269                 return 0;
 270
 271                 /* Geometry shader output, unsupported. */
 272         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 273         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 274                 return 0;
 275
 276                 /* Texturing. */
 277         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 278         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 279                 return VC4_MAX_MIP_LEVELS;
 280         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 281                 /* Note: Not supported in hardware, just faking it. */
 282                 return 5;
 283         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 284                 return 0;
 285
 286                 /* Render targets. */
 287         case PIPE_CAP_MAX_RENDER_TARGETS:
 288                 return 1;
 289
 290                 /* Queries. */
 291         case PIPE_CAP_QUERY_TIME_ELAPSED:
 292         case PIPE_CAP_QUERY_TIMESTAMP:
 293                 return 0;
 294
 295         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 296         case PIPE_CAP_MIN_TEXEL_OFFSET:
 297                 return 0;
 298
 299         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 300                 return 2048;
 301
 302         case PIPE_CAP_ENDIANNESS:
 303                 return PIPE_ENDIAN_LITTLE;
 304
 305         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 306                 return 64;
 307
 308         case PIPE_CAP_VENDOR_ID:
 309                 return 0x14E4;
 310         case PIPE_CAP_DEVICE_ID:
 311                 return 0xFFFFFFFF;
 312         case PIPE_CAP_ACCELERATED:
 313                 return 1;
 314         case PIPE_CAP_VIDEO_MEMORY: {
 315                 uint64_t system_memory;
 316
 317                 if (!os_get_total_physical_memory(&system_memory))
 318                         return 0;
 319
 320                 return (int)(system_memory >> 20);
 321         }
 322         case PIPE_CAP_UMA:
 323                 return 1;
 324
 325         default:
 326                 fprintf(stderr, "unknown param %d\n", param);
 327                 return 0;
 328         }
 329 }
 330
 331 static float
 332 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 333 {
 334         switch (param) {
 335         case PIPE_CAPF_MAX_LINE_WIDTH:
 336         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 337                 return 32;
 338
 339         case PIPE_CAPF_MAX_POINT_WIDTH:
 340         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 341                 return 512.0f;
 342
 343         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 344                 return 0.0f;
 345         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 346                 return 0.0f;
 347         case PIPE_CAPF_GUARD_BAND_LEFT:
 348         case PIPE_CAPF_GUARD_BAND_TOP:
 349         case PIPE_CAPF_GUARD_BAND_RIGHT:
 350         case PIPE_CAPF_GUARD_BAND_BOTTOM:
 351                 return 0.0f;
 352         default:
 353                 fprintf(stderr, "unknown paramf %d\n", param);
 354                 return 0;
 355         }
 356 }
 357
 358 static int
 359 vc4_screen_get_shader_param(struct pipe_screen *pscreen,
 360                             enum pipe_shader_type shader,
 361                             enum pipe_shader_cap param)
 362 {
 363         if (shader != PIPE_SHADER_VERTEX &&
 364             shader != PIPE_SHADER_FRAGMENT) {
 365                 return 0;
 366         }
 367
 368         /* this is probably not totally correct.. but it's a start: */
 369         switch (param) {
 370         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 371         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 372         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 373         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 374                 return 16384;
 375
 376         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 377                 return vc4_screen(pscreen)->has_control_flow;
 378
 379         case PIPE_SHADER_CAP_MAX_INPUTS:
 380                 return 8;
 381         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 382                 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
 383         case PIPE_SHADER_CAP_MAX_TEMPS:
 384                 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
 385         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 386                 return 16 * 1024 * sizeof(float);
 387         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 388                 return 1;
 389         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 390                 return 0;
 391         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 392         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 393         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 394                 return 0;
 395         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 396                 return 1;
 397         case PIPE_SHADER_CAP_SUBROUTINES:
 398                 return 0;
 399         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 400                 return 0;
 401         case PIPE_SHADER_CAP_INTEGERS:
 402                 return 1;
 403         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 404         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 405         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 406         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 407                 return 0;
 408         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 409         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 410                 return VC4_MAX_TEXTURE_SAMPLERS;
 411         case PIPE_SHADER_CAP_PREFERRED_IR:
 412                 return PIPE_SHADER_IR_NIR;
 413         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 414                 return 0;
 415         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 416                 return 32;
 417         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 418         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 419         case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
 420         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
 421                 return 0;
 422         default:
 423                 fprintf(stderr, "unknown shader param %d\n", param);
 424                 return 0;
 425         }
 426         return 0;
 427 }
 428
 429 static boolean
 430 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
 431                                enum pipe_format format,
 432                                enum pipe_texture_target target,
 433                                unsigned sample_count,
 434                                unsigned usage)
 435 {
 436         struct vc4_screen *screen = vc4_screen(pscreen);
 437         unsigned retval = 0;
 438
 439         if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
 440                 return FALSE;
 441
 442         if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
 443             !util_format_is_supported(format, usage)) {
 444                 return FALSE;
 445         }
 446
 447         if (usage & PIPE_BIND_VERTEX_BUFFER) {
 448                 switch (format) {
 449                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 450                 case PIPE_FORMAT_R32G32B32_FLOAT:
 451                 case PIPE_FORMAT_R32G32_FLOAT:
 452                 case PIPE_FORMAT_R32_FLOAT:
 453                 case PIPE_FORMAT_R32G32B32A32_SNORM:
 454                 case PIPE_FORMAT_R32G32B32_SNORM:
 455                 case PIPE_FORMAT_R32G32_SNORM:
 456                 case PIPE_FORMAT_R32_SNORM:
 457                 case PIPE_FORMAT_R32G32B32A32_SSCALED:
 458                 case PIPE_FORMAT_R32G32B32_SSCALED:
 459                 case PIPE_FORMAT_R32G32_SSCALED:
 460                 case PIPE_FORMAT_R32_SSCALED:
 461                 case PIPE_FORMAT_R16G16B16A16_UNORM:
 462                 case PIPE_FORMAT_R16G16B16_UNORM:
 463                 case PIPE_FORMAT_R16G16_UNORM:
 464                 case PIPE_FORMAT_R16_UNORM:
 465                 case PIPE_FORMAT_R16G16B16A16_SNORM:
 466                 case PIPE_FORMAT_R16G16B16_SNORM:
 467                 case PIPE_FORMAT_R16G16_SNORM:
 468                 case PIPE_FORMAT_R16_SNORM:
 469                 case PIPE_FORMAT_R16G16B16A16_USCALED:
 470                 case PIPE_FORMAT_R16G16B16_USCALED:
 471                 case PIPE_FORMAT_R16G16_USCALED:
 472                 case PIPE_FORMAT_R16_USCALED:
 473                 case PIPE_FORMAT_R16G16B16A16_SSCALED:
 474                 case PIPE_FORMAT_R16G16B16_SSCALED:
 475                 case PIPE_FORMAT_R16G16_SSCALED:
 476                 case PIPE_FORMAT_R16_SSCALED:
 477                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 478                 case PIPE_FORMAT_R8G8B8_UNORM:
 479                 case PIPE_FORMAT_R8G8_UNORM:
 480                 case PIPE_FORMAT_R8_UNORM:
 481                 case PIPE_FORMAT_R8G8B8A8_SNORM:
 482                 case PIPE_FORMAT_R8G8B8_SNORM:
 483                 case PIPE_FORMAT_R8G8_SNORM:
 484                 case PIPE_FORMAT_R8_SNORM:
 485                 case PIPE_FORMAT_R8G8B8A8_USCALED:
 486                 case PIPE_FORMAT_R8G8B8_USCALED:
 487                 case PIPE_FORMAT_R8G8_USCALED:
 488                 case PIPE_FORMAT_R8_USCALED:
 489                 case PIPE_FORMAT_R8G8B8A8_SSCALED:
 490                 case PIPE_FORMAT_R8G8B8_SSCALED:
 491                 case PIPE_FORMAT_R8G8_SSCALED:
 492                 case PIPE_FORMAT_R8_SSCALED:
 493                         retval |= PIPE_BIND_VERTEX_BUFFER;
 494                         break;
 495                 default:
 496                         break;
 497                 }
 498         }
 499
 500         if ((usage & PIPE_BIND_RENDER_TARGET) &&
 501             vc4_rt_format_supported(format)) {
 502                 retval |= PIPE_BIND_RENDER_TARGET;
 503         }
 504
 505         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 506             vc4_tex_format_supported(format) &&
 507             (format != PIPE_FORMAT_ETC1_RGB8 || screen->has_etc1)) {
 508                 retval |= PIPE_BIND_SAMPLER_VIEW;
 509         }
 510
 511         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 512             (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
 513              format == PIPE_FORMAT_X8Z24_UNORM)) {
 514                 retval |= PIPE_BIND_DEPTH_STENCIL;
 515         }
 516
 517         if ((usage & PIPE_BIND_INDEX_BUFFER) &&
 518             (format == PIPE_FORMAT_I8_UINT ||
 519              format == PIPE_FORMAT_I16_UINT)) {
 520                 retval |= PIPE_BIND_INDEX_BUFFER;
 521         }
 522
 523 #if 0
 524         if (retval != usage) {
 525                 fprintf(stderr,
 526                         "not supported: format=%s, target=%d, sample_count=%d, "
 527                         "usage=0x%x, retval=0x%x\n", util_format_name(format),
 528                         target, sample_count, usage, retval);
 529         }
 530 #endif
 531
 532         return retval == usage;
 533 }
 534
 535 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
 536
 537 static unsigned handle_hash(void *key)
 538 {
 539     return PTR_TO_UINT(key);
 540 }
 541
 542 static int handle_compare(void *key1, void *key2)
 543 {
 544     return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
 545 }
 546
 547 static bool
 548 vc4_has_feature(struct vc4_screen *screen, uint32_t feature)
 549 {
 550         struct drm_vc4_get_param p = {
 551                 .param = feature,
 552         };
 553         int ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
 554
 555         if (ret != 0)
 556                 return false;
 557
 558         return p.value;
 559 }
 560
 561 static bool
 562 vc4_get_chip_info(struct vc4_screen *screen)
 563 {
 564         struct drm_vc4_get_param ident0 = {
 565                 .param = DRM_VC4_PARAM_V3D_IDENT0,
 566         };
 567         struct drm_vc4_get_param ident1 = {
 568                 .param = DRM_VC4_PARAM_V3D_IDENT1,
 569         };
 570         int ret;
 571
 572         ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
 573         if (ret != 0) {
 574                 if (errno == EINVAL) {
 575                         /* Backwards compatibility with 2835 kernels which
 576                          * only do V3D 2.1.
 577                          */
 578                         screen->v3d_ver = 21;
 579                         return true;
 580                 } else {
 581                         fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
 582                                 strerror(errno));
 583                         return false;
 584                 }
 585         }
 586         ret = vc4_ioctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
 587         if (ret != 0) {
 588                 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
 589                         strerror(errno));
 590                 return false;
 591         }
 592
 593         uint32_t major = (ident0.value >> 24) & 0xff;
 594         uint32_t minor = (ident1.value >> 0) & 0xf;
 595         screen->v3d_ver = major * 10 + minor;
 596
 597         if (screen->v3d_ver != 21 && screen->v3d_ver != 26) {
 598                 fprintf(stderr,
 599                         "V3D %d.%d not supported by this version of Mesa.\n",
 600                         screen->v3d_ver / 10,
 601                         screen->v3d_ver % 10);
 602                 return false;
 603         }
 604
 605         return true;
 606 }
 607
 608 struct pipe_screen *
 609 vc4_screen_create(int fd, struct renderonly *ro)
 610 {
 611         struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
 612         struct pipe_screen *pscreen;
 613
 614         pscreen = &screen->base;
 615
 616         pscreen->destroy = vc4_screen_destroy;
 617         pscreen->get_param = vc4_screen_get_param;
 618         pscreen->get_paramf = vc4_screen_get_paramf;
 619         pscreen->get_shader_param = vc4_screen_get_shader_param;
 620         pscreen->context_create = vc4_context_create;
 621         pscreen->is_format_supported = vc4_screen_is_format_supported;
 622
 623         screen->fd = fd;
 624         if (ro) {
 625                 screen->ro = renderonly_dup(ro);
 626                 if (!screen->ro) {
 627                         fprintf(stderr, "Failed to dup renderonly object\n");
 628                         ralloc_free(screen);
 629                         return NULL;
 630                 }
 631         }
 632
 633         list_inithead(&screen->bo_cache.time_list);
 634         (void) mtx_init(&screen->bo_handles_mutex, mtx_plain);
 635         screen->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 636
 637         screen->has_control_flow =
 638                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_BRANCHES);
 639         screen->has_etc1 =
 640                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_ETC1);
 641         screen->has_threaded_fs =
 642                 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_THREADED_FS);
 643
 644         if (!vc4_get_chip_info(screen))
 645                 goto fail;
 646
 647         util_cpu_detect();
 648
 649         slab_create_parent(&screen->transfer_pool, sizeof(struct vc4_transfer), 16);
 650
 651         vc4_fence_init(screen);
 652
 653         vc4_debug = debug_get_option_vc4_debug();
 654         if (vc4_debug & VC4_DEBUG_SHADERDB)
 655                 vc4_debug |= VC4_DEBUG_NORAST;
 656
 657 #if USE_VC4_SIMULATOR
 658         vc4_simulator_init(screen);
 659 #endif
 660
 661         vc4_resource_screen_init(pscreen);
 662
 663         pscreen->get_name = vc4_screen_get_name;
 664         pscreen->get_vendor = vc4_screen_get_vendor;
 665         pscreen->get_device_vendor = vc4_screen_get_vendor;
 666         pscreen->get_compiler_options = vc4_screen_get_compiler_options;
 667
 668         return pscreen;
 669
 670 fail:
 671         close(fd);
 672         ralloc_free(pscreen);
 673         return NULL;
 674 }