2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "os/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
30 #include "util/u_cpu_detect.h"
31 #include "util/u_debug.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_hash_table.h"
35 #include "util/ralloc.h"
38 #include "drm_fourcc.h"
40 #include "vc4_screen.h"
41 #include "vc4_context.h"
42 #include "vc4_resource.h"
44 static const struct debug_named_value debug_options
[] = {
46 "Dump command list during creation" },
47 { "surf", VC4_DEBUG_SURFACE
,
48 "Dump surface layouts" },
49 { "qpu", VC4_DEBUG_QPU
,
50 "Dump generated QPU instructions" },
51 { "qir", VC4_DEBUG_QIR
,
52 "Dump QPU IR during program compile" },
53 { "nir", VC4_DEBUG_NIR
,
54 "Dump NIR during program compile" },
55 { "tgsi", VC4_DEBUG_TGSI
,
56 "Dump TGSI during program compile" },
57 { "shaderdb", VC4_DEBUG_SHADERDB
,
58 "Dump program compile information for shader-db analysis" },
59 { "perf", VC4_DEBUG_PERF
,
60 "Print during performance-related events" },
61 { "norast", VC4_DEBUG_NORAST
,
62 "Skip actual hardware execution of commands" },
63 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH
,
64 "Flush after each draw call" },
65 { "always_sync", VC4_DEBUG_ALWAYS_SYNC
,
66 "Wait for finish after each flush" },
67 #ifdef USE_VC4_SIMULATOR
68 { "dump", VC4_DEBUG_DUMP
,
69 "Write a GPU command stream trace file" },
74 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug
, "VC4_DEBUG", debug_options
, 0)
78 vc4_screen_get_name(struct pipe_screen
*pscreen
)
80 struct vc4_screen
*screen
= vc4_screen(pscreen
);
83 screen
->name
= ralloc_asprintf(screen
,
86 screen
->v3d_ver
% 10);
93 vc4_screen_get_vendor(struct pipe_screen
*pscreen
)
99 vc4_screen_destroy(struct pipe_screen
*pscreen
)
101 struct vc4_screen
*screen
= vc4_screen(pscreen
);
103 util_hash_table_destroy(screen
->bo_handles
);
104 vc4_bufmgr_destroy(pscreen
);
105 slab_destroy_parent(&screen
->transfer_pool
);
108 #ifdef USE_VC4_SIMULATOR
109 vc4_simulator_destroy(screen
);
113 ralloc_free(pscreen
);
117 vc4_has_feature(struct vc4_screen
*screen
, uint32_t feature
)
119 struct drm_vc4_get_param p
= {
122 int ret
= vc4_ioctl(screen
->fd
, DRM_IOCTL_VC4_GET_PARAM
, &p
);
131 vc4_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
133 struct vc4_screen
*screen
= vc4_screen(pscreen
);
136 /* Supported features (boolean caps). */
137 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
138 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
139 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
140 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
141 case PIPE_CAP_NPOT_TEXTURES
:
142 case PIPE_CAP_SHAREABLE_SHADERS
:
143 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
144 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
145 case PIPE_CAP_TEXTURE_SWIZZLE
:
146 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
147 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
148 case PIPE_CAP_TEXTURE_BARRIER
:
151 case PIPE_CAP_TILE_RASTER_ORDER
:
152 return vc4_has_feature(screen
,
153 DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER
);
155 /* lying for GL 2.0 */
156 case PIPE_CAP_OCCLUSION_QUERY
:
157 case PIPE_CAP_POINT_SPRITE
:
160 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
163 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
166 case PIPE_CAP_MAX_VIEWPORTS
:
169 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
170 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
173 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
174 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
177 /* Unsupported features. */
178 case PIPE_CAP_ANISOTROPIC_FILTER
:
179 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
180 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
181 case PIPE_CAP_CUBE_MAP_ARRAY
:
182 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
183 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
184 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
185 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
186 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
187 case PIPE_CAP_TGSI_INSTANCEID
:
188 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
189 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
190 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
191 case PIPE_CAP_COMPUTE
:
192 case PIPE_CAP_START_INSTANCE
:
193 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
194 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
195 case PIPE_CAP_TGSI_TEXCOORD
:
196 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
197 case PIPE_CAP_CONDITIONAL_RENDER
:
198 case PIPE_CAP_PRIMITIVE_RESTART
:
200 case PIPE_CAP_INDEP_BLEND_ENABLE
:
201 case PIPE_CAP_INDEP_BLEND_FUNC
:
202 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
203 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
204 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
205 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
206 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
207 case PIPE_CAP_USER_VERTEX_BUFFERS
:
208 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
209 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
210 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
211 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
212 case PIPE_CAP_TEXTURE_GATHER_SM5
:
213 case PIPE_CAP_FAKE_SW_MSAA
:
214 case PIPE_CAP_TEXTURE_QUERY_LOD
:
215 case PIPE_CAP_SAMPLE_SHADING
:
216 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
217 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
218 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
219 case PIPE_CAP_MAX_TEXEL_OFFSET
:
220 case PIPE_CAP_MAX_VERTEX_STREAMS
:
221 case PIPE_CAP_DRAW_INDIRECT
:
222 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
223 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
224 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
225 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
226 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
227 case PIPE_CAP_CLIP_HALFZ
:
228 case PIPE_CAP_VERTEXID_NOBASE
:
229 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
230 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
231 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
232 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
233 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
234 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
235 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
236 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
237 case PIPE_CAP_TGSI_TXQS
:
238 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
239 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
240 case PIPE_CAP_CLEAR_TEXTURE
:
241 case PIPE_CAP_DRAW_PARAMETERS
:
242 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
243 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
244 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
245 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
246 case PIPE_CAP_INVALIDATE_BUFFER
:
247 case PIPE_CAP_GENERATE_MIPMAP
:
248 case PIPE_CAP_STRING_MARKER
:
249 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
250 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
251 case PIPE_CAP_QUERY_MEMORY_INFO
:
252 case PIPE_CAP_PCI_GROUP
:
253 case PIPE_CAP_PCI_BUS
:
254 case PIPE_CAP_PCI_DEVICE
:
255 case PIPE_CAP_PCI_FUNCTION
:
256 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
257 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
258 case PIPE_CAP_CULL_DISTANCE
:
259 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
260 case PIPE_CAP_TGSI_VOTE
:
261 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
262 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
263 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
264 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
265 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
266 case PIPE_CAP_NATIVE_FENCE_FD
:
267 case PIPE_CAP_TGSI_FS_FBFETCH
:
268 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
269 case PIPE_CAP_DOUBLES
:
271 case PIPE_CAP_INT64_DIVMOD
:
272 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
273 case PIPE_CAP_TGSI_CLOCK
:
274 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
275 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
276 case PIPE_CAP_TGSI_BALLOT
:
277 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
278 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
279 case PIPE_CAP_POST_DEPTH_COVERAGE
:
280 case PIPE_CAP_BINDLESS_TEXTURE
:
281 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
282 case PIPE_CAP_QUERY_SO_OVERFLOW
:
283 case PIPE_CAP_MEMOBJ
:
284 case PIPE_CAP_LOAD_CONSTBUF
:
285 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
286 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
287 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
288 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
289 case PIPE_CAP_FENCE_SIGNAL
:
290 case PIPE_CAP_CONSTBUF0_FLAGS
:
294 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
295 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
296 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
297 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
298 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
301 /* Geometry shader output, unsupported. */
302 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
303 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
307 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
308 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
309 return VC4_MAX_MIP_LEVELS
;
310 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
311 /* Note: Not supported in hardware, just faking it. */
313 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
316 /* Render targets. */
317 case PIPE_CAP_MAX_RENDER_TARGETS
:
321 case PIPE_CAP_QUERY_TIME_ELAPSED
:
322 case PIPE_CAP_QUERY_TIMESTAMP
:
325 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
326 case PIPE_CAP_MIN_TEXEL_OFFSET
:
329 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
332 case PIPE_CAP_ENDIANNESS
:
333 return PIPE_ENDIAN_LITTLE
;
335 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
338 case PIPE_CAP_VENDOR_ID
:
340 case PIPE_CAP_DEVICE_ID
:
342 case PIPE_CAP_ACCELERATED
:
344 case PIPE_CAP_VIDEO_MEMORY
: {
345 uint64_t system_memory
;
347 if (!os_get_total_physical_memory(&system_memory
))
350 return (int)(system_memory
>> 20);
356 fprintf(stderr
, "unknown param %d\n", param
);
362 vc4_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
365 case PIPE_CAPF_MAX_LINE_WIDTH
:
366 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
369 case PIPE_CAPF_MAX_POINT_WIDTH
:
370 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
373 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
375 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
378 fprintf(stderr
, "unknown paramf %d\n", param
);
384 vc4_screen_get_shader_param(struct pipe_screen
*pscreen
,
385 enum pipe_shader_type shader
,
386 enum pipe_shader_cap param
)
388 if (shader
!= PIPE_SHADER_VERTEX
&&
389 shader
!= PIPE_SHADER_FRAGMENT
) {
393 /* this is probably not totally correct.. but it's a start: */
395 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
396 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
397 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
398 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
401 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
402 return vc4_screen(pscreen
)->has_control_flow
;
404 case PIPE_SHADER_CAP_MAX_INPUTS
:
406 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
407 return shader
== PIPE_SHADER_FRAGMENT
? 1 : 8;
408 case PIPE_SHADER_CAP_MAX_TEMPS
:
409 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
410 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
411 return 16 * 1024 * sizeof(float);
412 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
414 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
416 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
417 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
418 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
420 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
422 case PIPE_SHADER_CAP_SUBROUTINES
:
424 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
426 case PIPE_SHADER_CAP_INTEGERS
:
428 case PIPE_SHADER_CAP_INT64_ATOMICS
:
429 case PIPE_SHADER_CAP_FP16
:
430 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
431 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
432 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
433 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
434 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
436 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
437 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
438 return VC4_MAX_TEXTURE_SAMPLERS
;
439 case PIPE_SHADER_CAP_PREFERRED_IR
:
440 return PIPE_SHADER_IR_NIR
;
441 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
443 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
445 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
446 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
447 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
448 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
449 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
450 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
453 fprintf(stderr
, "unknown shader param %d\n", param
);
460 vc4_screen_is_format_supported(struct pipe_screen
*pscreen
,
461 enum pipe_format format
,
462 enum pipe_texture_target target
,
463 unsigned sample_count
,
466 struct vc4_screen
*screen
= vc4_screen(pscreen
);
469 if (sample_count
> 1 && sample_count
!= VC4_MAX_SAMPLES
)
472 if ((target
>= PIPE_MAX_TEXTURE_TYPES
) ||
473 !util_format_is_supported(format
, usage
)) {
477 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
479 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
480 case PIPE_FORMAT_R32G32B32_FLOAT
:
481 case PIPE_FORMAT_R32G32_FLOAT
:
482 case PIPE_FORMAT_R32_FLOAT
:
483 case PIPE_FORMAT_R32G32B32A32_SNORM
:
484 case PIPE_FORMAT_R32G32B32_SNORM
:
485 case PIPE_FORMAT_R32G32_SNORM
:
486 case PIPE_FORMAT_R32_SNORM
:
487 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
488 case PIPE_FORMAT_R32G32B32_SSCALED
:
489 case PIPE_FORMAT_R32G32_SSCALED
:
490 case PIPE_FORMAT_R32_SSCALED
:
491 case PIPE_FORMAT_R16G16B16A16_UNORM
:
492 case PIPE_FORMAT_R16G16B16_UNORM
:
493 case PIPE_FORMAT_R16G16_UNORM
:
494 case PIPE_FORMAT_R16_UNORM
:
495 case PIPE_FORMAT_R16G16B16A16_SNORM
:
496 case PIPE_FORMAT_R16G16B16_SNORM
:
497 case PIPE_FORMAT_R16G16_SNORM
:
498 case PIPE_FORMAT_R16_SNORM
:
499 case PIPE_FORMAT_R16G16B16A16_USCALED
:
500 case PIPE_FORMAT_R16G16B16_USCALED
:
501 case PIPE_FORMAT_R16G16_USCALED
:
502 case PIPE_FORMAT_R16_USCALED
:
503 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
504 case PIPE_FORMAT_R16G16B16_SSCALED
:
505 case PIPE_FORMAT_R16G16_SSCALED
:
506 case PIPE_FORMAT_R16_SSCALED
:
507 case PIPE_FORMAT_R8G8B8A8_UNORM
:
508 case PIPE_FORMAT_R8G8B8_UNORM
:
509 case PIPE_FORMAT_R8G8_UNORM
:
510 case PIPE_FORMAT_R8_UNORM
:
511 case PIPE_FORMAT_R8G8B8A8_SNORM
:
512 case PIPE_FORMAT_R8G8B8_SNORM
:
513 case PIPE_FORMAT_R8G8_SNORM
:
514 case PIPE_FORMAT_R8_SNORM
:
515 case PIPE_FORMAT_R8G8B8A8_USCALED
:
516 case PIPE_FORMAT_R8G8B8_USCALED
:
517 case PIPE_FORMAT_R8G8_USCALED
:
518 case PIPE_FORMAT_R8_USCALED
:
519 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
520 case PIPE_FORMAT_R8G8B8_SSCALED
:
521 case PIPE_FORMAT_R8G8_SSCALED
:
522 case PIPE_FORMAT_R8_SSCALED
:
523 retval
|= PIPE_BIND_VERTEX_BUFFER
;
530 if ((usage
& PIPE_BIND_RENDER_TARGET
) &&
531 vc4_rt_format_supported(format
)) {
532 retval
|= PIPE_BIND_RENDER_TARGET
;
535 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
536 vc4_tex_format_supported(format
) &&
537 (format
!= PIPE_FORMAT_ETC1_RGB8
|| screen
->has_etc1
)) {
538 retval
|= PIPE_BIND_SAMPLER_VIEW
;
541 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
542 (format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
||
543 format
== PIPE_FORMAT_X8Z24_UNORM
)) {
544 retval
|= PIPE_BIND_DEPTH_STENCIL
;
547 if ((usage
& PIPE_BIND_INDEX_BUFFER
) &&
548 (format
== PIPE_FORMAT_I8_UINT
||
549 format
== PIPE_FORMAT_I16_UINT
)) {
550 retval
|= PIPE_BIND_INDEX_BUFFER
;
553 retval
|= usage
& PIPE_BIND_DISPLAY_TARGET
;
556 if (retval
!= usage
) {
558 "not supported: format=%s, target=%d, sample_count=%d, "
559 "usage=0x%x, retval=0x%x\n", util_format_name(format
),
560 target
, sample_count
, usage
, retval
);
564 return retval
== usage
;
568 vc4_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
569 enum pipe_format format
, int max
,
571 unsigned int *external_only
,
575 uint64_t available_modifiers
[] = {
576 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED
,
577 DRM_FORMAT_MOD_LINEAR
,
579 struct vc4_screen
*screen
= vc4_screen(pscreen
);
580 int num_modifiers
= screen
->has_tiling_ioctl
? 2 : 1;
583 *count
= num_modifiers
;
587 *count
= MIN2(max
, num_modifiers
);
588 m
= screen
->has_tiling_ioctl
? 0 : 1;
589 /* We support both modifiers (tiled and linear) for all sampler
590 * formats, but if we don't have the DRM_VC4_GET_TILING ioctl
591 * we shouldn't advertise the tiled formats.
593 for (i
= 0; i
< *count
; i
++) {
594 modifiers
[i
] = available_modifiers
[m
++];
596 external_only
[i
] = false;
600 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
602 static unsigned handle_hash(void *key
)
604 return PTR_TO_UINT(key
);
607 static int handle_compare(void *key1
, void *key2
)
609 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
613 vc4_get_chip_info(struct vc4_screen
*screen
)
615 struct drm_vc4_get_param ident0
= {
616 .param
= DRM_VC4_PARAM_V3D_IDENT0
,
618 struct drm_vc4_get_param ident1
= {
619 .param
= DRM_VC4_PARAM_V3D_IDENT1
,
623 ret
= vc4_ioctl(screen
->fd
, DRM_IOCTL_VC4_GET_PARAM
, &ident0
);
625 if (errno
== EINVAL
) {
626 /* Backwards compatibility with 2835 kernels which
629 screen
->v3d_ver
= 21;
632 fprintf(stderr
, "Couldn't get V3D IDENT0: %s\n",
637 ret
= vc4_ioctl(screen
->fd
, DRM_IOCTL_VC4_GET_PARAM
, &ident1
);
639 fprintf(stderr
, "Couldn't get V3D IDENT1: %s\n",
644 uint32_t major
= (ident0
.value
>> 24) & 0xff;
645 uint32_t minor
= (ident1
.value
>> 0) & 0xf;
646 screen
->v3d_ver
= major
* 10 + minor
;
648 if (screen
->v3d_ver
!= 21 && screen
->v3d_ver
!= 26) {
650 "V3D %d.%d not supported by this version of Mesa.\n",
651 screen
->v3d_ver
/ 10,
652 screen
->v3d_ver
% 10);
660 vc4_screen_create(int fd
, struct renderonly
*ro
)
662 struct vc4_screen
*screen
= rzalloc(NULL
, struct vc4_screen
);
663 struct pipe_screen
*pscreen
;
665 pscreen
= &screen
->base
;
667 pscreen
->destroy
= vc4_screen_destroy
;
668 pscreen
->get_param
= vc4_screen_get_param
;
669 pscreen
->get_paramf
= vc4_screen_get_paramf
;
670 pscreen
->get_shader_param
= vc4_screen_get_shader_param
;
671 pscreen
->context_create
= vc4_context_create
;
672 pscreen
->is_format_supported
= vc4_screen_is_format_supported
;
676 screen
->ro
= renderonly_dup(ro
);
678 fprintf(stderr
, "Failed to dup renderonly object\n");
684 list_inithead(&screen
->bo_cache
.time_list
);
685 (void) mtx_init(&screen
->bo_handles_mutex
, mtx_plain
);
686 screen
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
688 screen
->has_control_flow
=
689 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_BRANCHES
);
691 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_ETC1
);
692 screen
->has_threaded_fs
=
693 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_THREADED_FS
);
694 screen
->has_madvise
=
695 vc4_has_feature(screen
, DRM_VC4_PARAM_SUPPORTS_MADVISE
);
697 if (!vc4_get_chip_info(screen
))
702 slab_create_parent(&screen
->transfer_pool
, sizeof(struct vc4_transfer
), 16);
704 vc4_fence_init(screen
);
706 vc4_debug
= debug_get_option_vc4_debug();
707 if (vc4_debug
& VC4_DEBUG_SHADERDB
)
708 vc4_debug
|= VC4_DEBUG_NORAST
;
710 #ifdef USE_VC4_SIMULATOR
711 vc4_simulator_init(screen
);
714 vc4_resource_screen_init(pscreen
);
716 pscreen
->get_name
= vc4_screen_get_name
;
717 pscreen
->get_vendor
= vc4_screen_get_vendor
;
718 pscreen
->get_device_vendor
= vc4_screen_get_vendor
;
719 pscreen
->get_compiler_options
= vc4_screen_get_compiler_options
;
720 pscreen
->query_dmabuf_modifiers
= vc4_screen_query_dmabuf_modifiers
;
726 ralloc_free(pscreen
);