vc4: Check the V3D version reported by the kernel.
[mesa.git] / src / gallium / drivers / vc4 / vc4_screen.c
1 /*
2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "os/os_misc.h"
26 #include "pipe/p_defines.h"
27 #include "pipe/p_screen.h"
28 #include "pipe/p_state.h"
29
30 #include "util/u_debug.h"
31 #include "util/u_memory.h"
32 #include "util/u_format.h"
33 #include "util/ralloc.h"
34
35 #include <xf86drm.h>
36 #include "vc4_drm.h"
37 #include "vc4_screen.h"
38 #include "vc4_context.h"
39 #include "vc4_resource.h"
40
41 static const struct debug_named_value debug_options[] = {
42 { "cl", VC4_DEBUG_CL,
43 "Dump command list during creation" },
44 { "qpu", VC4_DEBUG_QPU,
45 "Dump generated QPU instructions" },
46 { "qir", VC4_DEBUG_QIR,
47 "Dump QPU IR during program compile" },
48 { "nir", VC4_DEBUG_NIR,
49 "Dump NIR during program compile" },
50 { "tgsi", VC4_DEBUG_TGSI,
51 "Dump TGSI during program compile" },
52 { "shaderdb", VC4_DEBUG_SHADERDB,
53 "Dump program compile information for shader-db analysis" },
54 { "perf", VC4_DEBUG_PERF,
55 "Print during performance-related events" },
56 { "norast", VC4_DEBUG_NORAST,
57 "Skip actual hardware execution of commands" },
58 { "always_flush", VC4_DEBUG_ALWAYS_FLUSH,
59 "Flush after each draw call" },
60 { "always_sync", VC4_DEBUG_ALWAYS_SYNC,
61 "Wait for finish after each flush" },
62 #if USE_VC4_SIMULATOR
63 { "dump", VC4_DEBUG_DUMP,
64 "Write a GPU command stream trace file" },
65 #endif
66 { NULL }
67 };
68
69 DEBUG_GET_ONCE_FLAGS_OPTION(vc4_debug, "VC4_DEBUG", debug_options, 0)
70 uint32_t vc4_debug;
71
72 static const char *
73 vc4_screen_get_name(struct pipe_screen *pscreen)
74 {
75 return "VC4";
76 }
77
78 static const char *
79 vc4_screen_get_vendor(struct pipe_screen *pscreen)
80 {
81 return "Broadcom";
82 }
83
84 static void
85 vc4_screen_destroy(struct pipe_screen *pscreen)
86 {
87 struct vc4_screen *screen = vc4_screen(pscreen);
88
89 vc4_bufmgr_destroy(pscreen);
90 close(screen->fd);
91 ralloc_free(pscreen);
92 }
93
94 static int
95 vc4_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
96 {
97 switch (param) {
98 /* Supported features (boolean caps). */
99 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
100 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
101 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
102 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
103 case PIPE_CAP_NPOT_TEXTURES:
104 case PIPE_CAP_SHAREABLE_SHADERS:
105 case PIPE_CAP_USER_CONSTANT_BUFFERS:
106 case PIPE_CAP_TEXTURE_SHADOW_MAP:
107 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
108 case PIPE_CAP_TWO_SIDED_STENCIL:
109 case PIPE_CAP_USER_INDEX_BUFFERS:
110 case PIPE_CAP_TEXTURE_MULTISAMPLE:
111 case PIPE_CAP_TEXTURE_SWIZZLE:
112 return 1;
113
114 /* lying for GL 2.0 */
115 case PIPE_CAP_OCCLUSION_QUERY:
116 case PIPE_CAP_POINT_SPRITE:
117 return 1;
118
119 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
120 return 256;
121
122 case PIPE_CAP_GLSL_FEATURE_LEVEL:
123 return 120;
124
125 case PIPE_CAP_MAX_VIEWPORTS:
126 return 1;
127
128 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
129 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
130 return 1;
131
132 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
133 return 1;
134
135 /* Unsupported features. */
136 case PIPE_CAP_ANISOTROPIC_FILTER:
137 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
138 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
139 case PIPE_CAP_CUBE_MAP_ARRAY:
140 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
141 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
142 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
143 case PIPE_CAP_SEAMLESS_CUBE_MAP:
144 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
145 case PIPE_CAP_TGSI_INSTANCEID:
146 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
147 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
148 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
149 case PIPE_CAP_COMPUTE:
150 case PIPE_CAP_START_INSTANCE:
151 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
152 case PIPE_CAP_SHADER_STENCIL_EXPORT:
153 case PIPE_CAP_TGSI_TEXCOORD:
154 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
155 case PIPE_CAP_CONDITIONAL_RENDER:
156 case PIPE_CAP_PRIMITIVE_RESTART:
157 case PIPE_CAP_TEXTURE_BARRIER:
158 case PIPE_CAP_SM3:
159 case PIPE_CAP_INDEP_BLEND_ENABLE:
160 case PIPE_CAP_INDEP_BLEND_FUNC:
161 case PIPE_CAP_DEPTH_CLIP_DISABLE:
162 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
163 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
164 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
165 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
166 case PIPE_CAP_USER_VERTEX_BUFFERS:
167 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
168 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
169 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
170 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
171 case PIPE_CAP_TEXTURE_GATHER_SM5:
172 case PIPE_CAP_FAKE_SW_MSAA:
173 case PIPE_CAP_TEXTURE_QUERY_LOD:
174 case PIPE_CAP_SAMPLE_SHADING:
175 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
176 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
177 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
178 case PIPE_CAP_MAX_TEXEL_OFFSET:
179 case PIPE_CAP_MAX_VERTEX_STREAMS:
180 case PIPE_CAP_DRAW_INDIRECT:
181 case PIPE_CAP_MULTI_DRAW_INDIRECT:
182 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
183 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
184 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
185 case PIPE_CAP_SAMPLER_VIEW_TARGET:
186 case PIPE_CAP_CLIP_HALFZ:
187 case PIPE_CAP_VERTEXID_NOBASE:
188 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
189 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
190 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
191 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
192 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
193 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
194 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
195 case PIPE_CAP_DEPTH_BOUNDS_TEST:
196 case PIPE_CAP_TGSI_TXQS:
197 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
198 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
199 case PIPE_CAP_CLEAR_TEXTURE:
200 case PIPE_CAP_DRAW_PARAMETERS:
201 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
202 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
203 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
204 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
205 case PIPE_CAP_INVALIDATE_BUFFER:
206 case PIPE_CAP_GENERATE_MIPMAP:
207 case PIPE_CAP_STRING_MARKER:
208 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
209 case PIPE_CAP_QUERY_BUFFER_OBJECT:
210 case PIPE_CAP_QUERY_MEMORY_INFO:
211 case PIPE_CAP_PCI_GROUP:
212 case PIPE_CAP_PCI_BUS:
213 case PIPE_CAP_PCI_DEVICE:
214 case PIPE_CAP_PCI_FUNCTION:
215 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
216 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
217 case PIPE_CAP_CULL_DISTANCE:
218 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
219 case PIPE_CAP_TGSI_VOTE:
220 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
221 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
222 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
223 return 0;
224
225 /* Stream output. */
226 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
227 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
228 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
229 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
230 return 0;
231
232 /* Geometry shader output, unsupported. */
233 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
234 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
235 return 0;
236
237 /* Texturing. */
238 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
239 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
240 return VC4_MAX_MIP_LEVELS;
241 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
242 /* Note: Not supported in hardware, just faking it. */
243 return 5;
244 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
245 return 0;
246
247 /* Render targets. */
248 case PIPE_CAP_MAX_RENDER_TARGETS:
249 return 1;
250
251 /* Queries. */
252 case PIPE_CAP_QUERY_TIME_ELAPSED:
253 case PIPE_CAP_QUERY_TIMESTAMP:
254 return 0;
255
256 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
257 case PIPE_CAP_MIN_TEXEL_OFFSET:
258 return 0;
259
260 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
261 return 2048;
262
263 case PIPE_CAP_ENDIANNESS:
264 return PIPE_ENDIAN_LITTLE;
265
266 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
267 return 64;
268
269 case PIPE_CAP_VENDOR_ID:
270 return 0x14E4;
271 case PIPE_CAP_DEVICE_ID:
272 return 0xFFFFFFFF;
273 case PIPE_CAP_ACCELERATED:
274 return 1;
275 case PIPE_CAP_VIDEO_MEMORY: {
276 uint64_t system_memory;
277
278 if (!os_get_total_physical_memory(&system_memory))
279 return 0;
280
281 return (int)(system_memory >> 20);
282 }
283 case PIPE_CAP_UMA:
284 return 1;
285
286 default:
287 fprintf(stderr, "unknown param %d\n", param);
288 return 0;
289 }
290 }
291
292 static float
293 vc4_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
294 {
295 switch (param) {
296 case PIPE_CAPF_MAX_LINE_WIDTH:
297 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
298 return 32;
299
300 case PIPE_CAPF_MAX_POINT_WIDTH:
301 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
302 return 512.0f;
303
304 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
305 return 0.0f;
306 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
307 return 0.0f;
308 case PIPE_CAPF_GUARD_BAND_LEFT:
309 case PIPE_CAPF_GUARD_BAND_TOP:
310 case PIPE_CAPF_GUARD_BAND_RIGHT:
311 case PIPE_CAPF_GUARD_BAND_BOTTOM:
312 return 0.0f;
313 default:
314 fprintf(stderr, "unknown paramf %d\n", param);
315 return 0;
316 }
317 }
318
319 static int
320 vc4_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
321 enum pipe_shader_cap param)
322 {
323 if (shader != PIPE_SHADER_VERTEX &&
324 shader != PIPE_SHADER_FRAGMENT) {
325 return 0;
326 }
327
328 /* this is probably not totally correct.. but it's a start: */
329 switch (param) {
330 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
331 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
332 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
333 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
334 return 16384;
335
336 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
337 return vc4_screen(pscreen)->has_control_flow;
338
339 case PIPE_SHADER_CAP_MAX_INPUTS:
340 if (shader == PIPE_SHADER_FRAGMENT)
341 return 8;
342 else
343 return 16;
344 case PIPE_SHADER_CAP_MAX_OUTPUTS:
345 return shader == PIPE_SHADER_FRAGMENT ? 1 : 8;
346 case PIPE_SHADER_CAP_MAX_TEMPS:
347 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
348 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
349 return 16 * 1024 * sizeof(float);
350 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
351 return 1;
352 case PIPE_SHADER_CAP_MAX_PREDS:
353 return 0; /* nothing uses this */
354 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
355 return 0;
356 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
357 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
358 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
359 return 0;
360 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
361 return 1;
362 case PIPE_SHADER_CAP_SUBROUTINES:
363 return 0;
364 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
365 return 0;
366 case PIPE_SHADER_CAP_INTEGERS:
367 return 1;
368 case PIPE_SHADER_CAP_DOUBLES:
369 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
370 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
371 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
372 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
373 return 0;
374 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
375 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
376 return VC4_MAX_TEXTURE_SAMPLERS;
377 case PIPE_SHADER_CAP_PREFERRED_IR:
378 return PIPE_SHADER_IR_TGSI;
379 case PIPE_SHADER_CAP_SUPPORTED_IRS:
380 return 0;
381 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
382 return 32;
383 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
384 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
385 return 0;
386 default:
387 fprintf(stderr, "unknown shader param %d\n", param);
388 return 0;
389 }
390 return 0;
391 }
392
393 static boolean
394 vc4_screen_is_format_supported(struct pipe_screen *pscreen,
395 enum pipe_format format,
396 enum pipe_texture_target target,
397 unsigned sample_count,
398 unsigned usage)
399 {
400 unsigned retval = 0;
401
402 if (sample_count > 1 && sample_count != VC4_MAX_SAMPLES)
403 return FALSE;
404
405 if ((target >= PIPE_MAX_TEXTURE_TYPES) ||
406 !util_format_is_supported(format, usage)) {
407 return FALSE;
408 }
409
410 if (usage & PIPE_BIND_VERTEX_BUFFER) {
411 switch (format) {
412 case PIPE_FORMAT_R32G32B32A32_FLOAT:
413 case PIPE_FORMAT_R32G32B32_FLOAT:
414 case PIPE_FORMAT_R32G32_FLOAT:
415 case PIPE_FORMAT_R32_FLOAT:
416 case PIPE_FORMAT_R32G32B32A32_SNORM:
417 case PIPE_FORMAT_R32G32B32_SNORM:
418 case PIPE_FORMAT_R32G32_SNORM:
419 case PIPE_FORMAT_R32_SNORM:
420 case PIPE_FORMAT_R32G32B32A32_SSCALED:
421 case PIPE_FORMAT_R32G32B32_SSCALED:
422 case PIPE_FORMAT_R32G32_SSCALED:
423 case PIPE_FORMAT_R32_SSCALED:
424 case PIPE_FORMAT_R16G16B16A16_UNORM:
425 case PIPE_FORMAT_R16G16B16_UNORM:
426 case PIPE_FORMAT_R16G16_UNORM:
427 case PIPE_FORMAT_R16_UNORM:
428 case PIPE_FORMAT_R16G16B16A16_SNORM:
429 case PIPE_FORMAT_R16G16B16_SNORM:
430 case PIPE_FORMAT_R16G16_SNORM:
431 case PIPE_FORMAT_R16_SNORM:
432 case PIPE_FORMAT_R16G16B16A16_USCALED:
433 case PIPE_FORMAT_R16G16B16_USCALED:
434 case PIPE_FORMAT_R16G16_USCALED:
435 case PIPE_FORMAT_R16_USCALED:
436 case PIPE_FORMAT_R16G16B16A16_SSCALED:
437 case PIPE_FORMAT_R16G16B16_SSCALED:
438 case PIPE_FORMAT_R16G16_SSCALED:
439 case PIPE_FORMAT_R16_SSCALED:
440 case PIPE_FORMAT_R8G8B8A8_UNORM:
441 case PIPE_FORMAT_R8G8B8_UNORM:
442 case PIPE_FORMAT_R8G8_UNORM:
443 case PIPE_FORMAT_R8_UNORM:
444 case PIPE_FORMAT_R8G8B8A8_SNORM:
445 case PIPE_FORMAT_R8G8B8_SNORM:
446 case PIPE_FORMAT_R8G8_SNORM:
447 case PIPE_FORMAT_R8_SNORM:
448 case PIPE_FORMAT_R8G8B8A8_USCALED:
449 case PIPE_FORMAT_R8G8B8_USCALED:
450 case PIPE_FORMAT_R8G8_USCALED:
451 case PIPE_FORMAT_R8_USCALED:
452 case PIPE_FORMAT_R8G8B8A8_SSCALED:
453 case PIPE_FORMAT_R8G8B8_SSCALED:
454 case PIPE_FORMAT_R8G8_SSCALED:
455 case PIPE_FORMAT_R8_SSCALED:
456 retval |= PIPE_BIND_VERTEX_BUFFER;
457 break;
458 default:
459 break;
460 }
461 }
462
463 if ((usage & PIPE_BIND_RENDER_TARGET) &&
464 vc4_rt_format_supported(format)) {
465 retval |= PIPE_BIND_RENDER_TARGET;
466 }
467
468 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
469 vc4_tex_format_supported(format)) {
470 retval |= PIPE_BIND_SAMPLER_VIEW;
471 }
472
473 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
474 (format == PIPE_FORMAT_S8_UINT_Z24_UNORM ||
475 format == PIPE_FORMAT_X8Z24_UNORM)) {
476 retval |= PIPE_BIND_DEPTH_STENCIL;
477 }
478
479 if ((usage & PIPE_BIND_INDEX_BUFFER) &&
480 (format == PIPE_FORMAT_I8_UINT ||
481 format == PIPE_FORMAT_I16_UINT)) {
482 retval |= PIPE_BIND_INDEX_BUFFER;
483 }
484
485 if (usage & PIPE_BIND_TRANSFER_READ)
486 retval |= PIPE_BIND_TRANSFER_READ;
487 if (usage & PIPE_BIND_TRANSFER_WRITE)
488 retval |= PIPE_BIND_TRANSFER_WRITE;
489
490 #if 0
491 if (retval != usage) {
492 fprintf(stderr,
493 "not supported: format=%s, target=%d, sample_count=%d, "
494 "usage=0x%x, retval=0x%x\n", util_format_name(format),
495 target, sample_count, usage, retval);
496 }
497 #endif
498
499 return retval == usage;
500 }
501
502 static bool
503 vc4_supports_branches(struct vc4_screen *screen)
504 {
505 #if USE_VC4_SIMULATOR
506 return true;
507 #endif
508
509 struct drm_vc4_get_param p = {
510 .param = DRM_VC4_PARAM_SUPPORTS_BRANCHES,
511 };
512 int ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &p);
513
514 if (ret != 0)
515 return false;
516
517 return p.value;
518 }
519
520 static bool
521 vc4_get_chip_info(struct vc4_screen *screen)
522 {
523 #if USE_VC4_SIMULATOR
524 screen->v3d_ver = 21;
525 return true;
526 #endif
527
528 struct drm_vc4_get_param ident0 = {
529 .param = DRM_VC4_PARAM_V3D_IDENT0,
530 };
531 struct drm_vc4_get_param ident1 = {
532 .param = DRM_VC4_PARAM_V3D_IDENT1,
533 };
534 int ret;
535
536 ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident0);
537 if (ret != 0) {
538 if (errno == EINVAL) {
539 /* Backwards compatibility with 2835 kernels which
540 * only do V3D 2.1.
541 */
542 screen->v3d_ver = 21;
543 return true;
544 } else {
545 fprintf(stderr, "Couldn't get V3D IDENT0: %s\n",
546 strerror(errno));
547 return false;
548 }
549 }
550 ret = drmIoctl(screen->fd, DRM_IOCTL_VC4_GET_PARAM, &ident1);
551 if (ret != 0) {
552 fprintf(stderr, "Couldn't get V3D IDENT1: %s\n",
553 strerror(errno));
554 return false;
555 }
556
557 uint32_t major = (ident0.value >> 24) & 0xff;
558 uint32_t minor = (ident1.value >> 0) & 0xf;
559 screen->v3d_ver = major * 10 + minor;
560
561 if (screen->v3d_ver != 21) {
562 fprintf(stderr,
563 "V3D %d.%d not supported by this version of Mesa.\n",
564 screen->v3d_ver / 10,
565 screen->v3d_ver % 10);
566 return false;
567 }
568
569 return true;
570 }
571
572 struct pipe_screen *
573 vc4_screen_create(int fd)
574 {
575 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
576 struct pipe_screen *pscreen;
577
578 pscreen = &screen->base;
579
580 pscreen->destroy = vc4_screen_destroy;
581 pscreen->get_param = vc4_screen_get_param;
582 pscreen->get_paramf = vc4_screen_get_paramf;
583 pscreen->get_shader_param = vc4_screen_get_shader_param;
584 pscreen->context_create = vc4_context_create;
585 pscreen->is_format_supported = vc4_screen_is_format_supported;
586
587 screen->fd = fd;
588 list_inithead(&screen->bo_cache.time_list);
589
590 if (vc4_supports_branches(screen))
591 screen->has_control_flow = true;
592
593 if (!vc4_get_chip_info(screen))
594 goto fail;
595
596 vc4_fence_init(screen);
597
598 vc4_debug = debug_get_option_vc4_debug();
599 if (vc4_debug & VC4_DEBUG_SHADERDB)
600 vc4_debug |= VC4_DEBUG_NORAST;
601
602 #if USE_VC4_SIMULATOR
603 vc4_simulator_init(screen);
604 #endif
605
606 vc4_resource_screen_init(pscreen);
607
608 pscreen->get_name = vc4_screen_get_name;
609 pscreen->get_vendor = vc4_screen_get_vendor;
610 pscreen->get_device_vendor = vc4_screen_get_vendor;
611
612 return pscreen;
613
614 fail:
615 close(fd);
616 ralloc_free(pscreen);
617 return NULL;
618 }
619
620 boolean
621 vc4_screen_bo_get_handle(struct pipe_screen *pscreen,
622 struct vc4_bo *bo,
623 unsigned stride,
624 struct winsys_handle *whandle)
625 {
626 whandle->stride = stride;
627
628 /* If we're passing some reference to our BO out to some other part of
629 * the system, then we can't do any optimizations about only us being
630 * the ones seeing it (like BO caching or shadow update avoidance).
631 */
632 bo->private = false;
633
634 switch (whandle->type) {
635 case DRM_API_HANDLE_TYPE_SHARED:
636 return vc4_bo_flink(bo, &whandle->handle);
637 case DRM_API_HANDLE_TYPE_KMS:
638 whandle->handle = bo->handle;
639 return TRUE;
640 case DRM_API_HANDLE_TYPE_FD:
641 whandle->handle = vc4_bo_get_dmabuf(bo);
642 return whandle->handle != -1;
643 }
644
645 return FALSE;
646 }
647
648 struct vc4_bo *
649 vc4_screen_bo_from_handle(struct pipe_screen *pscreen,
650 struct winsys_handle *whandle)
651 {
652 struct vc4_screen *screen = vc4_screen(pscreen);
653
654 if (whandle->offset != 0) {
655 fprintf(stderr,
656 "Attempt to import unsupported winsys offset %u\n",
657 whandle->offset);
658 return NULL;
659 }
660
661 switch (whandle->type) {
662 case DRM_API_HANDLE_TYPE_SHARED:
663 return vc4_bo_open_name(screen, whandle->handle, whandle->stride);
664 case DRM_API_HANDLE_TYPE_FD:
665 return vc4_bo_open_dmabuf(screen, whandle->handle, whandle->stride);
666 default:
667 fprintf(stderr,
668 "Attempt to import unsupported handle type %d\n",
669 whandle->type);
670 return NULL;
671 }
672 }