2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "pipe/p_state.h"
26 #include "util/u_inlines.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/u_helpers.h"
31 #include "vc4_context.h"
34 vc4_generic_cso_state_create(const void *src
, uint32_t size
)
36 void *dst
= calloc(1, size
);
39 memcpy(dst
, src
, size
);
44 vc4_generic_cso_state_delete(struct pipe_context
*pctx
, void *hwcso
)
50 vc4_set_blend_color(struct pipe_context
*pctx
,
51 const struct pipe_blend_color
*blend_color
)
53 struct vc4_context
*vc4
= vc4_context(pctx
);
54 vc4
->blend_color
= *blend_color
;
55 vc4
->dirty
|= VC4_DIRTY_BLEND_COLOR
;
59 vc4_set_stencil_ref(struct pipe_context
*pctx
,
60 const struct pipe_stencil_ref
*stencil_ref
)
62 struct vc4_context
*vc4
= vc4_context(pctx
);
63 vc4
->stencil_ref
=* stencil_ref
;
64 vc4
->dirty
|= VC4_DIRTY_STENCIL_REF
;
68 vc4_set_clip_state(struct pipe_context
*pctx
,
69 const struct pipe_clip_state
*clip
)
71 struct vc4_context
*vc4
= vc4_context(pctx
);
73 vc4
->dirty
|= VC4_DIRTY_CLIP
;
77 vc4_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
79 struct vc4_context
*vc4
= vc4_context(pctx
);
80 vc4
->sample_mask
= (uint16_t)sample_mask
;
81 vc4
->dirty
|= VC4_DIRTY_SAMPLE_MASK
;
85 float_to_187_half(float f
)
91 vc4_create_rasterizer_state(struct pipe_context
*pctx
,
92 const struct pipe_rasterizer_state
*cso
)
94 struct vc4_rasterizer_state
*so
;
96 so
= CALLOC_STRUCT(vc4_rasterizer_state
);
102 if (!(cso
->cull_face
& PIPE_FACE_FRONT
))
103 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT
;
104 if (!(cso
->cull_face
& PIPE_FACE_BACK
))
105 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK
;
107 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
110 so
->point_size
= MAX2(cso
->point_size
, .125f
);
113 so
->config_bits
[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES
;
115 if (cso
->offset_tri
) {
116 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET
;
118 so
->offset_units
= float_to_187_half(cso
->offset_units
);
119 so
->offset_factor
= float_to_187_half(cso
->offset_scale
);
125 /* Blend state is baked into shaders. */
127 vc4_create_blend_state(struct pipe_context
*pctx
,
128 const struct pipe_blend_state
*cso
)
130 return vc4_generic_cso_state_create(cso
, sizeof(*cso
));
134 * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
135 * values, so you don't have to do a separate writemask setup.
138 tlb_stencil_setup_writemask(uint8_t mask
)
145 default: return 0xff;
150 tlb_stencil_setup_bits(const struct pipe_stencil_state
*state
,
151 uint8_t writemask_bits
)
153 static const uint8_t op_map
[] = {
154 [PIPE_STENCIL_OP_ZERO
] = 0,
155 [PIPE_STENCIL_OP_KEEP
] = 1,
156 [PIPE_STENCIL_OP_REPLACE
] = 2,
157 [PIPE_STENCIL_OP_INCR
] = 3,
158 [PIPE_STENCIL_OP_DECR
] = 4,
159 [PIPE_STENCIL_OP_INVERT
] = 5,
160 [PIPE_STENCIL_OP_INCR_WRAP
] = 6,
161 [PIPE_STENCIL_OP_DECR_WRAP
] = 7,
165 if (writemask_bits
!= 0xff)
166 bits
|= writemask_bits
<< 28;
167 bits
|= op_map
[state
->zfail_op
] << 25;
168 bits
|= op_map
[state
->zpass_op
] << 22;
169 bits
|= op_map
[state
->fail_op
] << 19;
170 bits
|= state
->func
<< 16;
171 /* Ref is filled in at uniform upload time */
172 bits
|= state
->valuemask
<< 0;
178 vc4_create_depth_stencil_alpha_state(struct pipe_context
*pctx
,
179 const struct pipe_depth_stencil_alpha_state
*cso
)
181 struct vc4_depth_stencil_alpha_state
*so
;
183 so
= CALLOC_STRUCT(vc4_depth_stencil_alpha_state
);
189 /* We always keep the early Z state correct, since a later state using
190 * early Z may want it.
192 so
->config_bits
[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE
;
194 if (cso
->depth
.enabled
) {
195 if (cso
->depth
.writemask
) {
196 so
->config_bits
[1] |= VC4_CONFIG_BITS_Z_UPDATE
;
198 so
->config_bits
[1] |= (cso
->depth
.func
<<
199 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
201 /* We only handle early Z in the < direction because otherwise
202 * we'd have to runtime guess which direction to set in the
205 if ((cso
->depth
.func
== PIPE_FUNC_LESS
||
206 cso
->depth
.func
== PIPE_FUNC_LEQUAL
) &&
207 (!cso
->stencil
[0].enabled
||
208 (cso
->stencil
[0].zfail_op
== PIPE_STENCIL_OP_KEEP
&&
209 (!cso
->stencil
[1].enabled
||
210 cso
->stencil
[1].zfail_op
== PIPE_STENCIL_OP_KEEP
)))) {
211 so
->config_bits
[2] |= VC4_CONFIG_BITS_EARLY_Z
;
214 so
->config_bits
[1] |= (PIPE_FUNC_ALWAYS
<<
215 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
218 if (cso
->stencil
[0].enabled
) {
219 const struct pipe_stencil_state
*front
= &cso
->stencil
[0];
220 const struct pipe_stencil_state
*back
= &cso
->stencil
[1];
222 uint8_t front_writemask_bits
=
223 tlb_stencil_setup_writemask(front
->writemask
);
224 uint8_t back_writemask
= front
->writemask
;
225 uint8_t back_writemask_bits
= front_writemask_bits
;
227 so
->stencil_uniforms
[0] =
228 tlb_stencil_setup_bits(front
, front_writemask_bits
);
230 back_writemask
= back
->writemask
;
231 back_writemask_bits
=
232 tlb_stencil_setup_writemask(back
->writemask
);
234 so
->stencil_uniforms
[0] |= (1 << 30);
235 so
->stencil_uniforms
[1] =
236 tlb_stencil_setup_bits(back
, back_writemask_bits
);
237 so
->stencil_uniforms
[1] |= (2 << 30);
239 so
->stencil_uniforms
[0] |= (3 << 30);
242 if (front_writemask_bits
== 0xff ||
243 back_writemask_bits
== 0xff) {
244 so
->stencil_uniforms
[2] = (front
->writemask
|
245 (back_writemask
<< 8));
253 vc4_set_polygon_stipple(struct pipe_context
*pctx
,
254 const struct pipe_poly_stipple
*stipple
)
256 struct vc4_context
*vc4
= vc4_context(pctx
);
257 vc4
->stipple
= *stipple
;
258 vc4
->dirty
|= VC4_DIRTY_STIPPLE
;
262 vc4_set_scissor_states(struct pipe_context
*pctx
,
264 unsigned num_scissors
,
265 const struct pipe_scissor_state
*scissor
)
267 struct vc4_context
*vc4
= vc4_context(pctx
);
269 vc4
->scissor
= *scissor
;
270 vc4
->dirty
|= VC4_DIRTY_SCISSOR
;
274 vc4_set_viewport_states(struct pipe_context
*pctx
,
276 unsigned num_viewports
,
277 const struct pipe_viewport_state
*viewport
)
279 struct vc4_context
*vc4
= vc4_context(pctx
);
280 vc4
->viewport
= *viewport
;
281 vc4
->dirty
|= VC4_DIRTY_VIEWPORT
;
285 vc4_set_vertex_buffers(struct pipe_context
*pctx
,
286 unsigned start_slot
, unsigned count
,
287 const struct pipe_vertex_buffer
*vb
)
289 struct vc4_context
*vc4
= vc4_context(pctx
);
290 struct vc4_vertexbuf_stateobj
*so
= &vc4
->vertexbuf
;
292 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
,
294 so
->count
= util_last_bit(so
->enabled_mask
);
296 vc4
->dirty
|= VC4_DIRTY_VTXBUF
;
300 vc4_set_index_buffer(struct pipe_context
*pctx
,
301 const struct pipe_index_buffer
*ib
)
303 struct vc4_context
*vc4
= vc4_context(pctx
);
306 assert(!ib
->user_buffer
);
307 pipe_resource_reference(&vc4
->indexbuf
.buffer
, ib
->buffer
);
308 vc4
->indexbuf
.index_size
= ib
->index_size
;
309 vc4
->indexbuf
.offset
= ib
->offset
;
311 pipe_resource_reference(&vc4
->indexbuf
.buffer
, NULL
);
314 vc4
->dirty
|= VC4_DIRTY_INDEXBUF
;
318 vc4_blend_state_bind(struct pipe_context
*pctx
, void *hwcso
)
320 struct vc4_context
*vc4
= vc4_context(pctx
);
322 vc4
->dirty
|= VC4_DIRTY_BLEND
;
326 vc4_rasterizer_state_bind(struct pipe_context
*pctx
, void *hwcso
)
328 struct vc4_context
*vc4
= vc4_context(pctx
);
329 struct vc4_rasterizer_state
*rast
= hwcso
;
331 if (vc4
->rasterizer
&& rast
&&
332 vc4
->rasterizer
->base
.flatshade
!= rast
->base
.flatshade
) {
333 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
336 vc4
->rasterizer
= hwcso
;
337 vc4
->dirty
|= VC4_DIRTY_RASTERIZER
;
341 vc4_zsa_state_bind(struct pipe_context
*pctx
, void *hwcso
)
343 struct vc4_context
*vc4
= vc4_context(pctx
);
345 vc4
->dirty
|= VC4_DIRTY_ZSA
;
349 vc4_vertex_state_create(struct pipe_context
*pctx
, unsigned num_elements
,
350 const struct pipe_vertex_element
*elements
)
352 struct vc4_vertex_stateobj
*so
= CALLOC_STRUCT(vc4_vertex_stateobj
);
357 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
358 so
->num_elements
= num_elements
;
364 vc4_vertex_state_bind(struct pipe_context
*pctx
, void *hwcso
)
366 struct vc4_context
*vc4
= vc4_context(pctx
);
368 vc4
->dirty
|= VC4_DIRTY_VTXSTATE
;
372 vc4_set_constant_buffer(struct pipe_context
*pctx
, uint shader
, uint index
,
373 struct pipe_constant_buffer
*cb
)
375 struct vc4_context
*vc4
= vc4_context(pctx
);
376 struct vc4_constbuf_stateobj
*so
= &vc4
->constbuf
[shader
];
380 /* Note that the state tracker can unbind constant buffers by
384 so
->enabled_mask
&= ~(1 << index
);
385 so
->dirty_mask
&= ~(1 << index
);
390 so
->cb
[index
].buffer_offset
= cb
->buffer_offset
;
391 so
->cb
[index
].buffer_size
= cb
->buffer_size
;
392 so
->cb
[index
].user_buffer
= cb
->user_buffer
;
394 so
->enabled_mask
|= 1 << index
;
395 so
->dirty_mask
|= 1 << index
;
396 vc4
->dirty
|= VC4_DIRTY_CONSTBUF
;
400 vc4_set_framebuffer_state(struct pipe_context
*pctx
,
401 const struct pipe_framebuffer_state
*framebuffer
)
403 struct vc4_context
*vc4
= vc4_context(pctx
);
404 struct pipe_framebuffer_state
*cso
= &vc4
->framebuffer
;
409 for (i
= 0; i
< framebuffer
->nr_cbufs
; i
++)
410 pipe_surface_reference(&cso
->cbufs
[i
], framebuffer
->cbufs
[i
]);
411 for (; i
< vc4
->framebuffer
.nr_cbufs
; i
++)
412 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
414 cso
->nr_cbufs
= framebuffer
->nr_cbufs
;
416 pipe_surface_reference(&cso
->zsbuf
, framebuffer
->zsbuf
);
418 cso
->width
= framebuffer
->width
;
419 cso
->height
= framebuffer
->height
;
421 /* Nonzero texture mipmap levels are laid out as if they were in
422 * power-of-two-sized spaces. The renderbuffer config infers its
423 * stride from the width parameter, so we need to configure our
424 * framebuffer. Note that if the z/color buffers were mismatched
425 * sizes, we wouldn't be able to do this.
427 if (cso
->cbufs
[0] && cso
->cbufs
[0]->u
.tex
.level
) {
428 struct vc4_resource
*rsc
=
429 vc4_resource(cso
->cbufs
[0]->texture
);
431 (rsc
->slices
[cso
->cbufs
[0]->u
.tex
.level
].stride
/
433 } else if (cso
->zsbuf
&& cso
->zsbuf
->u
.tex
.level
){
434 struct vc4_resource
*rsc
=
435 vc4_resource(cso
->zsbuf
->texture
);
437 (rsc
->slices
[cso
->zsbuf
->u
.tex
.level
].stride
/
441 vc4
->dirty
|= VC4_DIRTY_FRAMEBUFFER
;
444 static struct vc4_texture_stateobj
*
445 vc4_get_stage_tex(struct vc4_context
*vc4
, unsigned shader
)
447 vc4
->dirty
|= VC4_DIRTY_TEXSTATE
;
450 case PIPE_SHADER_FRAGMENT
:
451 vc4
->dirty
|= VC4_DIRTY_FRAGTEX
;
452 return &vc4
->fragtex
;
454 case PIPE_SHADER_VERTEX
:
455 vc4
->dirty
|= VC4_DIRTY_VERTTEX
;
456 return &vc4
->verttex
;
459 fprintf(stderr
, "Unknown shader target %d\n", shader
);
464 static uint32_t translate_wrap(uint32_t p_wrap
, bool using_nearest
)
467 case PIPE_TEX_WRAP_REPEAT
:
469 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
471 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
473 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
475 case PIPE_TEX_WRAP_CLAMP
:
476 return (using_nearest
? 1 : 3);
478 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
479 assert(!"not reached");
485 vc4_create_sampler_state(struct pipe_context
*pctx
,
486 const struct pipe_sampler_state
*cso
)
488 static const uint8_t minfilter_map
[6] = {
489 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR
,
490 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR
,
491 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN
,
492 VC4_TEX_P1_MINFILT_LIN_MIP_LIN
,
493 VC4_TEX_P1_MINFILT_NEAREST
,
494 VC4_TEX_P1_MINFILT_LINEAR
,
496 static const uint32_t magfilter_map
[] = {
497 [PIPE_TEX_FILTER_NEAREST
] = VC4_TEX_P1_MAGFILT_NEAREST
,
498 [PIPE_TEX_FILTER_LINEAR
] = VC4_TEX_P1_MAGFILT_LINEAR
,
500 bool either_nearest
=
501 (cso
->mag_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
||
502 cso
->min_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
);
503 struct vc4_sampler_state
*so
= CALLOC_STRUCT(vc4_sampler_state
);
508 memcpy(so
, cso
, sizeof(*cso
));
511 (VC4_SET_FIELD(magfilter_map
[cso
->mag_img_filter
],
512 VC4_TEX_P1_MAGFILT
) |
513 VC4_SET_FIELD(minfilter_map
[cso
->min_mip_filter
* 2 +
514 cso
->min_img_filter
],
515 VC4_TEX_P1_MINFILT
) |
516 VC4_SET_FIELD(translate_wrap(cso
->wrap_s
, either_nearest
),
518 VC4_SET_FIELD(translate_wrap(cso
->wrap_t
, either_nearest
),
525 vc4_sampler_states_bind(struct pipe_context
*pctx
,
526 unsigned shader
, unsigned start
,
527 unsigned nr
, void **hwcso
)
529 struct vc4_context
*vc4
= vc4_context(pctx
);
530 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
536 for (i
= 0; i
< nr
; i
++) {
539 stage_tex
->samplers
[i
] = hwcso
[i
];
540 stage_tex
->dirty_samplers
|= (1 << i
);
543 for (; i
< stage_tex
->num_samplers
; i
++) {
544 stage_tex
->samplers
[i
] = NULL
;
545 stage_tex
->dirty_samplers
|= (1 << i
);
548 stage_tex
->num_samplers
= new_nr
;
551 static struct pipe_sampler_view
*
552 vc4_create_sampler_view(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
553 const struct pipe_sampler_view
*cso
)
555 struct vc4_sampler_view
*so
= malloc(sizeof(*so
));
556 struct vc4_resource
*rsc
= vc4_resource(prsc
);
563 pipe_reference(NULL
, &prsc
->reference
);
565 /* There is no hardware level clamping, and the start address of a
566 * texture may be misaligned, so in that case we have to copy to a
569 * Also, Raspberry Pi doesn't support sampling from raster textures,
570 * so we also have to copy to a temporary then.
572 if (cso
->u
.tex
.first_level
||
573 rsc
->vc4_format
== VC4_TEXTURE_TYPE_RGBA32R
) {
574 struct vc4_resource
*shadow_parent
= vc4_resource(prsc
);
575 struct pipe_resource tmpl
= shadow_parent
->base
.b
;
576 struct vc4_resource
*clone
;
578 tmpl
.bind
= PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_RENDER_TARGET
;
579 tmpl
.width0
= u_minify(tmpl
.width0
, cso
->u
.tex
.first_level
);
580 tmpl
.height0
= u_minify(tmpl
.height0
, cso
->u
.tex
.first_level
);
581 tmpl
.last_level
= cso
->u
.tex
.last_level
- cso
->u
.tex
.first_level
;
583 prsc
= vc4_resource_create(pctx
->screen
, &tmpl
);
584 rsc
= vc4_resource(prsc
);
585 clone
= vc4_resource(prsc
);
586 clone
->shadow_parent
= &shadow_parent
->base
.b
;
587 /* Flag it as needing update of the contents from the parent. */
588 clone
->writes
= shadow_parent
->writes
- 1;
590 assert(clone
->vc4_format
!= VC4_TEXTURE_TYPE_RGBA32R
);
592 so
->base
.texture
= prsc
;
593 so
->base
.reference
.count
= 1;
594 so
->base
.context
= pctx
;
597 (VC4_SET_FIELD(rsc
->slices
[0].offset
>> 12, VC4_TEX_P0_OFFSET
) |
598 VC4_SET_FIELD(rsc
->vc4_format
& 15, VC4_TEX_P0_TYPE
) |
599 VC4_SET_FIELD(cso
->u
.tex
.last_level
-
600 cso
->u
.tex
.first_level
, VC4_TEX_P0_MIPLVLS
) |
601 VC4_SET_FIELD(cso
->target
== PIPE_TEXTURE_CUBE
,
604 (VC4_SET_FIELD(rsc
->vc4_format
>> 4, VC4_TEX_P1_TYPE4
) |
605 VC4_SET_FIELD(prsc
->height0
& 2047, VC4_TEX_P1_HEIGHT
) |
606 VC4_SET_FIELD(prsc
->width0
& 2047, VC4_TEX_P1_WIDTH
));
612 vc4_sampler_view_destroy(struct pipe_context
*pctx
,
613 struct pipe_sampler_view
*view
)
615 pipe_resource_reference(&view
->texture
, NULL
);
620 vc4_set_sampler_views(struct pipe_context
*pctx
, unsigned shader
,
621 unsigned start
, unsigned nr
,
622 struct pipe_sampler_view
**views
)
624 struct vc4_context
*vc4
= vc4_context(pctx
);
625 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
631 vc4
->dirty
|= VC4_DIRTY_TEXSTATE
;
633 for (i
= 0; i
< nr
; i
++) {
636 pipe_sampler_view_reference(&stage_tex
->textures
[i
], views
[i
]);
637 stage_tex
->dirty_samplers
|= (1 << i
);
640 for (; i
< stage_tex
->num_textures
; i
++) {
641 pipe_sampler_view_reference(&stage_tex
->textures
[i
], NULL
);
642 stage_tex
->dirty_samplers
|= (1 << i
);
645 stage_tex
->num_textures
= new_nr
;
649 vc4_state_init(struct pipe_context
*pctx
)
651 pctx
->set_blend_color
= vc4_set_blend_color
;
652 pctx
->set_stencil_ref
= vc4_set_stencil_ref
;
653 pctx
->set_clip_state
= vc4_set_clip_state
;
654 pctx
->set_sample_mask
= vc4_set_sample_mask
;
655 pctx
->set_constant_buffer
= vc4_set_constant_buffer
;
656 pctx
->set_framebuffer_state
= vc4_set_framebuffer_state
;
657 pctx
->set_polygon_stipple
= vc4_set_polygon_stipple
;
658 pctx
->set_scissor_states
= vc4_set_scissor_states
;
659 pctx
->set_viewport_states
= vc4_set_viewport_states
;
661 pctx
->set_vertex_buffers
= vc4_set_vertex_buffers
;
662 pctx
->set_index_buffer
= vc4_set_index_buffer
;
664 pctx
->create_blend_state
= vc4_create_blend_state
;
665 pctx
->bind_blend_state
= vc4_blend_state_bind
;
666 pctx
->delete_blend_state
= vc4_generic_cso_state_delete
;
668 pctx
->create_rasterizer_state
= vc4_create_rasterizer_state
;
669 pctx
->bind_rasterizer_state
= vc4_rasterizer_state_bind
;
670 pctx
->delete_rasterizer_state
= vc4_generic_cso_state_delete
;
672 pctx
->create_depth_stencil_alpha_state
= vc4_create_depth_stencil_alpha_state
;
673 pctx
->bind_depth_stencil_alpha_state
= vc4_zsa_state_bind
;
674 pctx
->delete_depth_stencil_alpha_state
= vc4_generic_cso_state_delete
;
676 pctx
->create_vertex_elements_state
= vc4_vertex_state_create
;
677 pctx
->delete_vertex_elements_state
= vc4_generic_cso_state_delete
;
678 pctx
->bind_vertex_elements_state
= vc4_vertex_state_bind
;
680 pctx
->create_sampler_state
= vc4_create_sampler_state
;
681 pctx
->delete_sampler_state
= vc4_generic_cso_state_delete
;
682 pctx
->bind_sampler_states
= vc4_sampler_states_bind
;
684 pctx
->create_sampler_view
= vc4_create_sampler_view
;
685 pctx
->sampler_view_destroy
= vc4_sampler_view_destroy
;
686 pctx
->set_sampler_views
= vc4_set_sampler_views
;