2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "pipe/p_state.h"
26 #include "util/u_inlines.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/u_helpers.h"
31 #include "vc4_context.h"
34 vc4_generic_cso_state_create(const void *src
, uint32_t size
)
36 void *dst
= calloc(1, size
);
39 memcpy(dst
, src
, size
);
44 vc4_generic_cso_state_delete(struct pipe_context
*pctx
, void *hwcso
)
50 vc4_set_blend_color(struct pipe_context
*pctx
,
51 const struct pipe_blend_color
*blend_color
)
53 struct vc4_context
*vc4
= vc4_context(pctx
);
54 vc4
->blend_color
.f
= *blend_color
;
55 for (int i
= 0; i
< 4; i
++)
56 vc4
->blend_color
.ub
[i
] = float_to_ubyte(blend_color
->color
[i
]);
57 vc4
->dirty
|= VC4_DIRTY_BLEND_COLOR
;
61 vc4_set_stencil_ref(struct pipe_context
*pctx
,
62 const struct pipe_stencil_ref
*stencil_ref
)
64 struct vc4_context
*vc4
= vc4_context(pctx
);
65 vc4
->stencil_ref
=* stencil_ref
;
66 vc4
->dirty
|= VC4_DIRTY_STENCIL_REF
;
70 vc4_set_clip_state(struct pipe_context
*pctx
,
71 const struct pipe_clip_state
*clip
)
73 struct vc4_context
*vc4
= vc4_context(pctx
);
75 vc4
->dirty
|= VC4_DIRTY_CLIP
;
79 vc4_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
81 struct vc4_context
*vc4
= vc4_context(pctx
);
82 vc4
->sample_mask
= sample_mask
& ((1 << VC4_MAX_SAMPLES
) - 1);
83 vc4
->dirty
|= VC4_DIRTY_SAMPLE_MASK
;
87 float_to_187_half(float f
)
93 vc4_create_rasterizer_state(struct pipe_context
*pctx
,
94 const struct pipe_rasterizer_state
*cso
)
96 struct vc4_rasterizer_state
*so
;
97 struct V3D21_DEPTH_OFFSET depth_offset
= { V3D21_DEPTH_OFFSET_header
};
98 struct V3D21_POINT_SIZE point_size
= { V3D21_POINT_SIZE_header
};
99 struct V3D21_LINE_WIDTH line_width
= { V3D21_LINE_WIDTH_header
};
101 so
= CALLOC_STRUCT(vc4_rasterizer_state
);
107 if (!(cso
->cull_face
& PIPE_FACE_FRONT
))
108 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT
;
109 if (!(cso
->cull_face
& PIPE_FACE_BACK
))
110 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK
;
112 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
115 point_size
.point_size
= MAX2(cso
->point_size
, .125f
);
117 line_width
.line_width
= cso
->line_width
;
120 so
->config_bits
[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES
;
122 if (cso
->offset_tri
) {
123 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET
;
125 depth_offset
.depth_offset_units
=
126 float_to_187_half(cso
->offset_units
);
127 depth_offset
.depth_offset_factor
=
128 float_to_187_half(cso
->offset_scale
);
131 if (cso
->multisample
)
132 so
->config_bits
[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X
;
134 V3D21_DEPTH_OFFSET_pack(NULL
, so
->packed
.depth_offset
, &depth_offset
);
135 V3D21_POINT_SIZE_pack(NULL
, so
->packed
.point_size
, &point_size
);
136 V3D21_LINE_WIDTH_pack(NULL
, so
->packed
.line_width
, &line_width
);
138 if (cso
->tile_raster_order_fixed
) {
139 so
->tile_raster_order_flags
|= VC4_SUBMIT_CL_FIXED_RCL_ORDER
;
140 if (cso
->tile_raster_order_increasing_x
) {
141 so
->tile_raster_order_flags
|=
142 VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X
;
144 if (cso
->tile_raster_order_increasing_y
) {
145 so
->tile_raster_order_flags
|=
146 VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y
;
153 /* Blend state is baked into shaders. */
155 vc4_create_blend_state(struct pipe_context
*pctx
,
156 const struct pipe_blend_state
*cso
)
158 return vc4_generic_cso_state_create(cso
, sizeof(*cso
));
162 * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
163 * values, so you don't have to do a separate writemask setup.
166 tlb_stencil_setup_writemask(uint8_t mask
)
173 default: return 0xff;
178 tlb_stencil_setup_bits(const struct pipe_stencil_state
*state
,
179 uint8_t writemask_bits
)
181 static const uint8_t op_map
[] = {
182 [PIPE_STENCIL_OP_ZERO
] = 0,
183 [PIPE_STENCIL_OP_KEEP
] = 1,
184 [PIPE_STENCIL_OP_REPLACE
] = 2,
185 [PIPE_STENCIL_OP_INCR
] = 3,
186 [PIPE_STENCIL_OP_DECR
] = 4,
187 [PIPE_STENCIL_OP_INVERT
] = 5,
188 [PIPE_STENCIL_OP_INCR_WRAP
] = 6,
189 [PIPE_STENCIL_OP_DECR_WRAP
] = 7,
193 if (writemask_bits
!= 0xff)
194 bits
|= writemask_bits
<< 28;
195 bits
|= op_map
[state
->zfail_op
] << 25;
196 bits
|= op_map
[state
->zpass_op
] << 22;
197 bits
|= op_map
[state
->fail_op
] << 19;
198 bits
|= state
->func
<< 16;
199 /* Ref is filled in at uniform upload time */
200 bits
|= state
->valuemask
<< 0;
206 vc4_create_depth_stencil_alpha_state(struct pipe_context
*pctx
,
207 const struct pipe_depth_stencil_alpha_state
*cso
)
209 struct vc4_depth_stencil_alpha_state
*so
;
211 so
= CALLOC_STRUCT(vc4_depth_stencil_alpha_state
);
217 /* We always keep the early Z state correct, since a later state using
218 * early Z may want it.
220 so
->config_bits
[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE
;
222 if (cso
->depth
.enabled
) {
223 if (cso
->depth
.writemask
) {
224 so
->config_bits
[1] |= VC4_CONFIG_BITS_Z_UPDATE
;
226 so
->config_bits
[1] |= (cso
->depth
.func
<<
227 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
229 /* We only handle early Z in the < direction because otherwise
230 * we'd have to runtime guess which direction to set in the
233 if ((cso
->depth
.func
== PIPE_FUNC_LESS
||
234 cso
->depth
.func
== PIPE_FUNC_LEQUAL
) &&
235 (!cso
->stencil
[0].enabled
||
236 (cso
->stencil
[0].zfail_op
== PIPE_STENCIL_OP_KEEP
&&
237 (!cso
->stencil
[1].enabled
||
238 cso
->stencil
[1].zfail_op
== PIPE_STENCIL_OP_KEEP
)))) {
239 so
->config_bits
[2] |= VC4_CONFIG_BITS_EARLY_Z
;
242 so
->config_bits
[1] |= (PIPE_FUNC_ALWAYS
<<
243 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
246 if (cso
->stencil
[0].enabled
) {
247 const struct pipe_stencil_state
*front
= &cso
->stencil
[0];
248 const struct pipe_stencil_state
*back
= &cso
->stencil
[1];
250 uint8_t front_writemask_bits
=
251 tlb_stencil_setup_writemask(front
->writemask
);
252 uint8_t back_writemask
= front
->writemask
;
253 uint8_t back_writemask_bits
= front_writemask_bits
;
255 so
->stencil_uniforms
[0] =
256 tlb_stencil_setup_bits(front
, front_writemask_bits
);
258 back_writemask
= back
->writemask
;
259 back_writemask_bits
=
260 tlb_stencil_setup_writemask(back
->writemask
);
262 so
->stencil_uniforms
[0] |= (1 << 30);
263 so
->stencil_uniforms
[1] =
264 tlb_stencil_setup_bits(back
, back_writemask_bits
);
265 so
->stencil_uniforms
[1] |= (2 << 30);
267 so
->stencil_uniforms
[0] |= (3 << 30);
270 if (front_writemask_bits
== 0xff ||
271 back_writemask_bits
== 0xff) {
272 so
->stencil_uniforms
[2] = (front
->writemask
|
273 (back_writemask
<< 8));
281 vc4_set_polygon_stipple(struct pipe_context
*pctx
,
282 const struct pipe_poly_stipple
*stipple
)
284 struct vc4_context
*vc4
= vc4_context(pctx
);
285 vc4
->stipple
= *stipple
;
286 vc4
->dirty
|= VC4_DIRTY_STIPPLE
;
290 vc4_set_scissor_states(struct pipe_context
*pctx
,
292 unsigned num_scissors
,
293 const struct pipe_scissor_state
*scissor
)
295 struct vc4_context
*vc4
= vc4_context(pctx
);
297 vc4
->scissor
= *scissor
;
298 vc4
->dirty
|= VC4_DIRTY_SCISSOR
;
302 vc4_set_viewport_states(struct pipe_context
*pctx
,
304 unsigned num_viewports
,
305 const struct pipe_viewport_state
*viewport
)
307 struct vc4_context
*vc4
= vc4_context(pctx
);
308 vc4
->viewport
= *viewport
;
309 vc4
->dirty
|= VC4_DIRTY_VIEWPORT
;
313 vc4_set_vertex_buffers(struct pipe_context
*pctx
,
314 unsigned start_slot
, unsigned count
,
315 const struct pipe_vertex_buffer
*vb
)
317 struct vc4_context
*vc4
= vc4_context(pctx
);
318 struct vc4_vertexbuf_stateobj
*so
= &vc4
->vertexbuf
;
320 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
,
322 so
->count
= util_last_bit(so
->enabled_mask
);
324 vc4
->dirty
|= VC4_DIRTY_VTXBUF
;
328 vc4_blend_state_bind(struct pipe_context
*pctx
, void *hwcso
)
330 struct vc4_context
*vc4
= vc4_context(pctx
);
332 vc4
->dirty
|= VC4_DIRTY_BLEND
;
336 vc4_rasterizer_state_bind(struct pipe_context
*pctx
, void *hwcso
)
338 struct vc4_context
*vc4
= vc4_context(pctx
);
339 struct vc4_rasterizer_state
*rast
= hwcso
;
341 if (vc4
->rasterizer
&& rast
&&
342 vc4
->rasterizer
->base
.flatshade
!= rast
->base
.flatshade
) {
343 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
346 vc4
->rasterizer
= hwcso
;
347 vc4
->dirty
|= VC4_DIRTY_RASTERIZER
;
351 vc4_zsa_state_bind(struct pipe_context
*pctx
, void *hwcso
)
353 struct vc4_context
*vc4
= vc4_context(pctx
);
355 vc4
->dirty
|= VC4_DIRTY_ZSA
;
359 vc4_vertex_state_create(struct pipe_context
*pctx
, unsigned num_elements
,
360 const struct pipe_vertex_element
*elements
)
362 struct vc4_vertex_stateobj
*so
= CALLOC_STRUCT(vc4_vertex_stateobj
);
367 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
368 so
->num_elements
= num_elements
;
374 vc4_vertex_state_bind(struct pipe_context
*pctx
, void *hwcso
)
376 struct vc4_context
*vc4
= vc4_context(pctx
);
378 vc4
->dirty
|= VC4_DIRTY_VTXSTATE
;
382 vc4_set_constant_buffer(struct pipe_context
*pctx
,
383 enum pipe_shader_type shader
, uint index
,
384 const struct pipe_constant_buffer
*cb
)
386 struct vc4_context
*vc4
= vc4_context(pctx
);
387 struct vc4_constbuf_stateobj
*so
= &vc4
->constbuf
[shader
];
391 /* Note that the state tracker can unbind constant buffers by
395 so
->enabled_mask
&= ~(1 << index
);
396 so
->dirty_mask
&= ~(1 << index
);
401 so
->cb
[index
].buffer_offset
= cb
->buffer_offset
;
402 so
->cb
[index
].buffer_size
= cb
->buffer_size
;
403 so
->cb
[index
].user_buffer
= cb
->user_buffer
;
405 so
->enabled_mask
|= 1 << index
;
406 so
->dirty_mask
|= 1 << index
;
407 vc4
->dirty
|= VC4_DIRTY_CONSTBUF
;
411 vc4_set_framebuffer_state(struct pipe_context
*pctx
,
412 const struct pipe_framebuffer_state
*framebuffer
)
414 struct vc4_context
*vc4
= vc4_context(pctx
);
415 struct pipe_framebuffer_state
*cso
= &vc4
->framebuffer
;
420 for (i
= 0; i
< framebuffer
->nr_cbufs
; i
++)
421 pipe_surface_reference(&cso
->cbufs
[i
], framebuffer
->cbufs
[i
]);
422 for (; i
< vc4
->framebuffer
.nr_cbufs
; i
++)
423 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
425 cso
->nr_cbufs
= framebuffer
->nr_cbufs
;
427 pipe_surface_reference(&cso
->zsbuf
, framebuffer
->zsbuf
);
429 cso
->width
= framebuffer
->width
;
430 cso
->height
= framebuffer
->height
;
432 /* Nonzero texture mipmap levels are laid out as if they were in
433 * power-of-two-sized spaces. The renderbuffer config infers its
434 * stride from the width parameter, so we need to configure our
435 * framebuffer. Note that if the z/color buffers were mismatched
436 * sizes, we wouldn't be able to do this.
438 if (cso
->cbufs
[0] && cso
->cbufs
[0]->u
.tex
.level
) {
439 struct vc4_resource
*rsc
=
440 vc4_resource(cso
->cbufs
[0]->texture
);
442 (rsc
->slices
[cso
->cbufs
[0]->u
.tex
.level
].stride
/
444 } else if (cso
->zsbuf
&& cso
->zsbuf
->u
.tex
.level
){
445 struct vc4_resource
*rsc
=
446 vc4_resource(cso
->zsbuf
->texture
);
448 (rsc
->slices
[cso
->zsbuf
->u
.tex
.level
].stride
/
452 vc4
->dirty
|= VC4_DIRTY_FRAMEBUFFER
;
455 static struct vc4_texture_stateobj
*
456 vc4_get_stage_tex(struct vc4_context
*vc4
, enum pipe_shader_type shader
)
459 case PIPE_SHADER_FRAGMENT
:
460 vc4
->dirty
|= VC4_DIRTY_FRAGTEX
;
461 return &vc4
->fragtex
;
463 case PIPE_SHADER_VERTEX
:
464 vc4
->dirty
|= VC4_DIRTY_VERTTEX
;
465 return &vc4
->verttex
;
468 fprintf(stderr
, "Unknown shader target %d\n", shader
);
473 static uint32_t translate_wrap(uint32_t p_wrap
, bool using_nearest
)
476 case PIPE_TEX_WRAP_REPEAT
:
478 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
480 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
482 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
484 case PIPE_TEX_WRAP_CLAMP
:
485 return (using_nearest
? 1 : 3);
487 fprintf(stderr
, "Unknown wrap mode %d\n", p_wrap
);
488 assert(!"not reached");
494 vc4_create_sampler_state(struct pipe_context
*pctx
,
495 const struct pipe_sampler_state
*cso
)
497 static const uint8_t minfilter_map
[6] = {
498 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR
,
499 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR
,
500 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN
,
501 VC4_TEX_P1_MINFILT_LIN_MIP_LIN
,
502 VC4_TEX_P1_MINFILT_NEAREST
,
503 VC4_TEX_P1_MINFILT_LINEAR
,
505 static const uint32_t magfilter_map
[] = {
506 [PIPE_TEX_FILTER_NEAREST
] = VC4_TEX_P1_MAGFILT_NEAREST
,
507 [PIPE_TEX_FILTER_LINEAR
] = VC4_TEX_P1_MAGFILT_LINEAR
,
509 bool either_nearest
=
510 (cso
->mag_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
||
511 cso
->min_img_filter
== PIPE_TEX_MIPFILTER_NEAREST
);
512 struct vc4_sampler_state
*so
= CALLOC_STRUCT(vc4_sampler_state
);
517 memcpy(so
, cso
, sizeof(*cso
));
520 (VC4_SET_FIELD(magfilter_map
[cso
->mag_img_filter
],
521 VC4_TEX_P1_MAGFILT
) |
522 VC4_SET_FIELD(minfilter_map
[cso
->min_mip_filter
* 2 +
523 cso
->min_img_filter
],
524 VC4_TEX_P1_MINFILT
) |
525 VC4_SET_FIELD(translate_wrap(cso
->wrap_s
, either_nearest
),
527 VC4_SET_FIELD(translate_wrap(cso
->wrap_t
, either_nearest
),
534 vc4_sampler_states_bind(struct pipe_context
*pctx
,
535 enum pipe_shader_type shader
, unsigned start
,
536 unsigned nr
, void **hwcso
)
538 struct vc4_context
*vc4
= vc4_context(pctx
);
539 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
545 for (i
= 0; i
< nr
; i
++) {
548 stage_tex
->samplers
[i
] = hwcso
[i
];
551 for (; i
< stage_tex
->num_samplers
; i
++) {
552 stage_tex
->samplers
[i
] = NULL
;
555 stage_tex
->num_samplers
= new_nr
;
558 static struct pipe_sampler_view
*
559 vc4_create_sampler_view(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
560 const struct pipe_sampler_view
*cso
)
562 struct vc4_sampler_view
*so
= CALLOC_STRUCT(vc4_sampler_view
);
563 struct vc4_resource
*rsc
= vc4_resource(prsc
);
570 so
->base
.texture
= NULL
;
571 pipe_resource_reference(&so
->base
.texture
, prsc
);
572 so
->base
.reference
.count
= 1;
573 so
->base
.context
= pctx
;
575 /* There is no hardware level clamping, and the start address of a
576 * texture may be misaligned, so in that case we have to copy to a
579 * Also, Raspberry Pi doesn't support sampling from raster textures,
580 * so we also have to copy to a temporary then.
582 if ((cso
->u
.tex
.first_level
&&
583 (cso
->u
.tex
.first_level
!= cso
->u
.tex
.last_level
)) ||
584 rsc
->vc4_format
== VC4_TEXTURE_TYPE_RGBA32R
) {
585 struct vc4_resource
*shadow_parent
= rsc
;
586 struct pipe_resource tmpl
= *prsc
;
588 tmpl
.bind
= PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_RENDER_TARGET
;
589 tmpl
.width0
= u_minify(tmpl
.width0
, cso
->u
.tex
.first_level
);
590 tmpl
.height0
= u_minify(tmpl
.height0
, cso
->u
.tex
.first_level
);
591 tmpl
.last_level
= cso
->u
.tex
.last_level
- cso
->u
.tex
.first_level
;
593 /* Create the shadow texture. The rest of the texture
594 * parameter setup will use the shadow.
596 prsc
= vc4_resource_create(pctx
->screen
, &tmpl
);
601 rsc
= vc4_resource(prsc
);
602 vc4_bo_label(vc4_screen(pctx
->screen
), rsc
->bo
,
603 "tiling shadow %dx%d",
604 tmpl
.width0
, tmpl
.height0
);
606 /* Flag it as needing update of the contents from the parent. */
607 rsc
->writes
= shadow_parent
->writes
- 1;
608 assert(rsc
->vc4_format
!= VC4_TEXTURE_TYPE_RGBA32R
);
612 pipe_resource_reference(&so
->texture
, prsc
);
614 if (cso
->u
.tex
.first_level
) {
615 so
->force_first_level
= true;
620 (VC4_SET_FIELD(rsc
->slices
[0].offset
>> 12, VC4_TEX_P0_OFFSET
) |
621 VC4_SET_FIELD(rsc
->vc4_format
& 15, VC4_TEX_P0_TYPE
) |
622 VC4_SET_FIELD(so
->force_first_level
?
623 cso
->u
.tex
.last_level
:
624 cso
->u
.tex
.last_level
-
625 cso
->u
.tex
.first_level
, VC4_TEX_P0_MIPLVLS
) |
626 VC4_SET_FIELD(cso
->target
== PIPE_TEXTURE_CUBE
,
629 (VC4_SET_FIELD(rsc
->vc4_format
>> 4, VC4_TEX_P1_TYPE4
) |
630 VC4_SET_FIELD(prsc
->height0
& 2047, VC4_TEX_P1_HEIGHT
) |
631 VC4_SET_FIELD(prsc
->width0
& 2047, VC4_TEX_P1_WIDTH
));
633 if (prsc
->format
== PIPE_FORMAT_ETC1_RGB8
)
634 so
->texture_p1
|= VC4_TEX_P1_ETCFLIP_MASK
;
640 vc4_sampler_view_destroy(struct pipe_context
*pctx
,
641 struct pipe_sampler_view
*pview
)
643 struct vc4_sampler_view
*view
= vc4_sampler_view(pview
);
644 pipe_resource_reference(&pview
->texture
, NULL
);
645 pipe_resource_reference(&view
->texture
, NULL
);
650 vc4_set_sampler_views(struct pipe_context
*pctx
,
651 enum pipe_shader_type shader
,
652 unsigned start
, unsigned nr
,
653 struct pipe_sampler_view
**views
)
655 struct vc4_context
*vc4
= vc4_context(pctx
);
656 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
662 for (i
= 0; i
< nr
; i
++) {
665 pipe_sampler_view_reference(&stage_tex
->textures
[i
], views
[i
]);
668 for (; i
< stage_tex
->num_textures
; i
++) {
669 pipe_sampler_view_reference(&stage_tex
->textures
[i
], NULL
);
672 stage_tex
->num_textures
= new_nr
;
676 vc4_state_init(struct pipe_context
*pctx
)
678 pctx
->set_blend_color
= vc4_set_blend_color
;
679 pctx
->set_stencil_ref
= vc4_set_stencil_ref
;
680 pctx
->set_clip_state
= vc4_set_clip_state
;
681 pctx
->set_sample_mask
= vc4_set_sample_mask
;
682 pctx
->set_constant_buffer
= vc4_set_constant_buffer
;
683 pctx
->set_framebuffer_state
= vc4_set_framebuffer_state
;
684 pctx
->set_polygon_stipple
= vc4_set_polygon_stipple
;
685 pctx
->set_scissor_states
= vc4_set_scissor_states
;
686 pctx
->set_viewport_states
= vc4_set_viewport_states
;
688 pctx
->set_vertex_buffers
= vc4_set_vertex_buffers
;
690 pctx
->create_blend_state
= vc4_create_blend_state
;
691 pctx
->bind_blend_state
= vc4_blend_state_bind
;
692 pctx
->delete_blend_state
= vc4_generic_cso_state_delete
;
694 pctx
->create_rasterizer_state
= vc4_create_rasterizer_state
;
695 pctx
->bind_rasterizer_state
= vc4_rasterizer_state_bind
;
696 pctx
->delete_rasterizer_state
= vc4_generic_cso_state_delete
;
698 pctx
->create_depth_stencil_alpha_state
= vc4_create_depth_stencil_alpha_state
;
699 pctx
->bind_depth_stencil_alpha_state
= vc4_zsa_state_bind
;
700 pctx
->delete_depth_stencil_alpha_state
= vc4_generic_cso_state_delete
;
702 pctx
->create_vertex_elements_state
= vc4_vertex_state_create
;
703 pctx
->delete_vertex_elements_state
= vc4_generic_cso_state_delete
;
704 pctx
->bind_vertex_elements_state
= vc4_vertex_state_bind
;
706 pctx
->create_sampler_state
= vc4_create_sampler_state
;
707 pctx
->delete_sampler_state
= vc4_generic_cso_state_delete
;
708 pctx
->bind_sampler_states
= vc4_sampler_states_bind
;
710 pctx
->create_sampler_view
= vc4_create_sampler_view
;
711 pctx
->sampler_view_destroy
= vc4_sampler_view_destroy
;
712 pctx
->set_sampler_views
= vc4_set_sampler_views
;