src/gallium/drivers/vc4/vc4_state.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "pipe/p_state.h"
  26 #include "util/u_inlines.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_helpers.h"
  30
  31 #include "vc4_context.h"
  32
  33 static void *
  34 vc4_generic_cso_state_create(const void *src, uint32_t size)
  35 {
  36         void *dst = calloc(1, size);
  37         if (!dst)
  38                 return NULL;
  39         memcpy(dst, src, size);
  40         return dst;
  41 }
  42
  43 static void
  44 vc4_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
  45 {
  46         free(hwcso);
  47 }
  48
  49 static void
  50 vc4_set_blend_color(struct pipe_context *pctx,
  51                     const struct pipe_blend_color *blend_color)
  52 {
  53         struct vc4_context *vc4 = vc4_context(pctx);
  54         vc4->blend_color.f = *blend_color;
  55         for (int i = 0; i < 4; i++)
  56                 vc4->blend_color.ub[i] = float_to_ubyte(blend_color->color[i]);
  57         vc4->dirty |= VC4_DIRTY_BLEND_COLOR;
  58 }
  59
  60 static void
  61 vc4_set_stencil_ref(struct pipe_context *pctx,
  62                     const struct pipe_stencil_ref *stencil_ref)
  63 {
  64         struct vc4_context *vc4 = vc4_context(pctx);
  65         vc4->stencil_ref =* stencil_ref;
  66         vc4->dirty |= VC4_DIRTY_STENCIL_REF;
  67 }
  68
  69 static void
  70 vc4_set_clip_state(struct pipe_context *pctx,
  71                    const struct pipe_clip_state *clip)
  72 {
  73         struct vc4_context *vc4 = vc4_context(pctx);
  74         vc4->clip = *clip;
  75         vc4->dirty |= VC4_DIRTY_CLIP;
  76 }
  77
  78 static void
  79 vc4_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  80 {
  81         struct vc4_context *vc4 = vc4_context(pctx);
  82         vc4->sample_mask = sample_mask & ((1 << VC4_MAX_SAMPLES) - 1);
  83         vc4->dirty |= VC4_DIRTY_SAMPLE_MASK;
  84 }
  85
  86 static uint16_t
  87 float_to_187_half(float f)
  88 {
  89         return fui(f) >> 16;
  90 }
  91
  92 static void *
  93 vc4_create_rasterizer_state(struct pipe_context *pctx,
  94                             const struct pipe_rasterizer_state *cso)
  95 {
  96         struct vc4_rasterizer_state *so;
  97         struct V3D21_DEPTH_OFFSET depth_offset = { V3D21_DEPTH_OFFSET_header };
  98         struct V3D21_POINT_SIZE point_size = { V3D21_POINT_SIZE_header };
  99         struct V3D21_LINE_WIDTH line_width = { V3D21_LINE_WIDTH_header };
 100
 101         so = CALLOC_STRUCT(vc4_rasterizer_state);
 102         if (!so)
 103                 return NULL;
 104
 105         so->base = *cso;
 106
 107         if (!(cso->cull_face & PIPE_FACE_FRONT))
 108                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT;
 109         if (!(cso->cull_face & PIPE_FACE_BACK))
 110                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK;
 111
 112         /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
 113          * BCM21553).
 114          */
 115         point_size.point_size = MAX2(cso->point_size, .125f);
 116
 117         line_width.line_width = cso->line_width;
 118
 119         if (cso->front_ccw)
 120                 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES;
 121
 122         if (cso->offset_tri) {
 123                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET;
 124
 125                 depth_offset.depth_offset_units =
 126                         float_to_187_half(cso->offset_units);
 127                 depth_offset.depth_offset_factor =
 128                         float_to_187_half(cso->offset_scale);
 129         }
 130
 131         if (cso->multisample)
 132                 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X;
 133
 134         V3D21_DEPTH_OFFSET_pack(NULL, so->packed.depth_offset, &depth_offset);
 135         V3D21_POINT_SIZE_pack(NULL, so->packed.point_size, &point_size);
 136         V3D21_LINE_WIDTH_pack(NULL, so->packed.line_width, &line_width);
 137
 138         return so;
 139 }
 140
 141 /* Blend state is baked into shaders. */
 142 static void *
 143 vc4_create_blend_state(struct pipe_context *pctx,
 144                        const struct pipe_blend_state *cso)
 145 {
 146         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 147 }
 148
 149 /**
 150  * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
 151  * values, so you don't have to do a separate writemask setup.
 152  */
 153 static uint8_t
 154 tlb_stencil_setup_writemask(uint8_t mask)
 155 {
 156         switch (mask) {
 157         case 0x1: return 0;
 158         case 0x3: return 1;
 159         case 0xf: return 2;
 160         case 0xff: return 3;
 161         default: return 0xff;
 162         }
 163 }
 164
 165 static uint32_t
 166 tlb_stencil_setup_bits(const struct pipe_stencil_state *state,
 167                        uint8_t writemask_bits)
 168 {
 169         static const uint8_t op_map[] = {
 170                 [PIPE_STENCIL_OP_ZERO] = 0,
 171                 [PIPE_STENCIL_OP_KEEP] = 1,
 172                 [PIPE_STENCIL_OP_REPLACE] = 2,
 173                 [PIPE_STENCIL_OP_INCR] = 3,
 174                 [PIPE_STENCIL_OP_DECR] = 4,
 175                 [PIPE_STENCIL_OP_INVERT] = 5,
 176                 [PIPE_STENCIL_OP_INCR_WRAP] = 6,
 177                 [PIPE_STENCIL_OP_DECR_WRAP] = 7,
 178         };
 179         uint32_t bits = 0;
 180
 181         if (writemask_bits != 0xff)
 182                 bits |= writemask_bits << 28;
 183         bits |= op_map[state->zfail_op] << 25;
 184         bits |= op_map[state->zpass_op] << 22;
 185         bits |= op_map[state->fail_op] << 19;
 186         bits |= state->func << 16;
 187         /* Ref is filled in at uniform upload time */
 188         bits |= state->valuemask << 0;
 189
 190         return bits;
 191 }
 192
 193 static void *
 194 vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx,
 195                                      const struct pipe_depth_stencil_alpha_state *cso)
 196 {
 197         struct vc4_depth_stencil_alpha_state *so;
 198
 199         so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state);
 200         if (!so)
 201                 return NULL;
 202
 203         so->base = *cso;
 204
 205         /* We always keep the early Z state correct, since a later state using
 206          * early Z may want it.
 207          */
 208         so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE;
 209
 210         if (cso->depth.enabled) {
 211                 if (cso->depth.writemask) {
 212                         so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE;
 213                 }
 214                 so->config_bits[1] |= (cso->depth.func <<
 215                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 216
 217                 /* We only handle early Z in the < direction because otherwise
 218                  * we'd have to runtime guess which direction to set in the
 219                  * render config.
 220                  */
 221                 if ((cso->depth.func == PIPE_FUNC_LESS ||
 222                      cso->depth.func == PIPE_FUNC_LEQUAL) &&
 223                     (!cso->stencil[0].enabled ||
 224                      (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
 225                       (!cso->stencil[1].enabled ||
 226                        cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP)))) {
 227                         so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z;
 228                 }
 229         } else {
 230                 so->config_bits[1] |= (PIPE_FUNC_ALWAYS <<
 231                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 232         }
 233
 234         if (cso->stencil[0].enabled) {
 235                 const struct pipe_stencil_state *front = &cso->stencil[0];
 236                 const struct pipe_stencil_state *back = &cso->stencil[1];
 237
 238                 uint8_t front_writemask_bits =
 239                         tlb_stencil_setup_writemask(front->writemask);
 240                 uint8_t back_writemask = front->writemask;
 241                 uint8_t back_writemask_bits = front_writemask_bits;
 242
 243                 so->stencil_uniforms[0] =
 244                         tlb_stencil_setup_bits(front, front_writemask_bits);
 245                 if (back->enabled) {
 246                         back_writemask = back->writemask;
 247                         back_writemask_bits =
 248                                 tlb_stencil_setup_writemask(back->writemask);
 249
 250                         so->stencil_uniforms[0] |= (1 << 30);
 251                         so->stencil_uniforms[1] =
 252                                 tlb_stencil_setup_bits(back, back_writemask_bits);
 253                         so->stencil_uniforms[1] |= (2 << 30);
 254                 } else {
 255                         so->stencil_uniforms[0] |= (3 << 30);
 256                 }
 257
 258                 if (front_writemask_bits == 0xff ||
 259                     back_writemask_bits == 0xff) {
 260                         so->stencil_uniforms[2] = (front->writemask |
 261                                                    (back_writemask << 8));
 262                 }
 263         }
 264
 265         return so;
 266 }
 267
 268 static void
 269 vc4_set_polygon_stipple(struct pipe_context *pctx,
 270                         const struct pipe_poly_stipple *stipple)
 271 {
 272         struct vc4_context *vc4 = vc4_context(pctx);
 273         vc4->stipple = *stipple;
 274         vc4->dirty |= VC4_DIRTY_STIPPLE;
 275 }
 276
 277 static void
 278 vc4_set_scissor_states(struct pipe_context *pctx,
 279                        unsigned start_slot,
 280                        unsigned num_scissors,
 281                        const struct pipe_scissor_state *scissor)
 282 {
 283         struct vc4_context *vc4 = vc4_context(pctx);
 284
 285         vc4->scissor = *scissor;
 286         vc4->dirty |= VC4_DIRTY_SCISSOR;
 287 }
 288
 289 static void
 290 vc4_set_viewport_states(struct pipe_context *pctx,
 291                         unsigned start_slot,
 292                         unsigned num_viewports,
 293                         const struct pipe_viewport_state *viewport)
 294 {
 295         struct vc4_context *vc4 = vc4_context(pctx);
 296         vc4->viewport = *viewport;
 297         vc4->dirty |= VC4_DIRTY_VIEWPORT;
 298 }
 299
 300 static void
 301 vc4_set_vertex_buffers(struct pipe_context *pctx,
 302                        unsigned start_slot, unsigned count,
 303                        const struct pipe_vertex_buffer *vb)
 304 {
 305         struct vc4_context *vc4 = vc4_context(pctx);
 306         struct vc4_vertexbuf_stateobj *so = &vc4->vertexbuf;
 307
 308         util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
 309                                      start_slot, count);
 310         so->count = util_last_bit(so->enabled_mask);
 311
 312         vc4->dirty |= VC4_DIRTY_VTXBUF;
 313 }
 314
 315 static void
 316 vc4_blend_state_bind(struct pipe_context *pctx, void *hwcso)
 317 {
 318         struct vc4_context *vc4 = vc4_context(pctx);
 319         vc4->blend = hwcso;
 320         vc4->dirty |= VC4_DIRTY_BLEND;
 321 }
 322
 323 static void
 324 vc4_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
 325 {
 326         struct vc4_context *vc4 = vc4_context(pctx);
 327         struct vc4_rasterizer_state *rast = hwcso;
 328
 329         if (vc4->rasterizer && rast &&
 330             vc4->rasterizer->base.flatshade != rast->base.flatshade) {
 331                 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
 332         }
 333
 334         vc4->rasterizer = hwcso;
 335         vc4->dirty |= VC4_DIRTY_RASTERIZER;
 336 }
 337
 338 static void
 339 vc4_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
 340 {
 341         struct vc4_context *vc4 = vc4_context(pctx);
 342         vc4->zsa = hwcso;
 343         vc4->dirty |= VC4_DIRTY_ZSA;
 344 }
 345
 346 static void *
 347 vc4_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
 348                         const struct pipe_vertex_element *elements)
 349 {
 350         struct vc4_vertex_stateobj *so = CALLOC_STRUCT(vc4_vertex_stateobj);
 351
 352         if (!so)
 353                 return NULL;
 354
 355         memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
 356         so->num_elements = num_elements;
 357
 358         return so;
 359 }
 360
 361 static void
 362 vc4_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
 363 {
 364         struct vc4_context *vc4 = vc4_context(pctx);
 365         vc4->vtx = hwcso;
 366         vc4->dirty |= VC4_DIRTY_VTXSTATE;
 367 }
 368
 369 static void
 370 vc4_set_constant_buffer(struct pipe_context *pctx,
 371                         enum pipe_shader_type shader, uint index,
 372                         const struct pipe_constant_buffer *cb)
 373 {
 374         struct vc4_context *vc4 = vc4_context(pctx);
 375         struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader];
 376
 377         assert(index == 0);
 378
 379         /* Note that the state tracker can unbind constant buffers by
 380          * passing NULL here.
 381          */
 382         if (unlikely(!cb)) {
 383                 so->enabled_mask &= ~(1 << index);
 384                 so->dirty_mask &= ~(1 << index);
 385                 return;
 386         }
 387
 388         assert(!cb->buffer);
 389         so->cb[index].buffer_offset = cb->buffer_offset;
 390         so->cb[index].buffer_size   = cb->buffer_size;
 391         so->cb[index].user_buffer   = cb->user_buffer;
 392
 393         so->enabled_mask |= 1 << index;
 394         so->dirty_mask |= 1 << index;
 395         vc4->dirty |= VC4_DIRTY_CONSTBUF;
 396 }
 397
 398 static void
 399 vc4_set_framebuffer_state(struct pipe_context *pctx,
 400                           const struct pipe_framebuffer_state *framebuffer)
 401 {
 402         struct vc4_context *vc4 = vc4_context(pctx);
 403         struct pipe_framebuffer_state *cso = &vc4->framebuffer;
 404         unsigned i;
 405
 406         vc4->job = NULL;
 407
 408         for (i = 0; i < framebuffer->nr_cbufs; i++)
 409                 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
 410         for (; i < vc4->framebuffer.nr_cbufs; i++)
 411                 pipe_surface_reference(&cso->cbufs[i], NULL);
 412
 413         cso->nr_cbufs = framebuffer->nr_cbufs;
 414
 415         pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
 416
 417         cso->width = framebuffer->width;
 418         cso->height = framebuffer->height;
 419
 420         /* Nonzero texture mipmap levels are laid out as if they were in
 421          * power-of-two-sized spaces.  The renderbuffer config infers its
 422          * stride from the width parameter, so we need to configure our
 423          * framebuffer.  Note that if the z/color buffers were mismatched
 424          * sizes, we wouldn't be able to do this.
 425          */
 426         if (cso->cbufs[0] && cso->cbufs[0]->u.tex.level) {
 427                 struct vc4_resource *rsc =
 428                         vc4_resource(cso->cbufs[0]->texture);
 429                 cso->width =
 430                         (rsc->slices[cso->cbufs[0]->u.tex.level].stride /
 431                          rsc->cpp);
 432         } else if (cso->zsbuf && cso->zsbuf->u.tex.level){
 433                 struct vc4_resource *rsc =
 434                         vc4_resource(cso->zsbuf->texture);
 435                 cso->width =
 436                         (rsc->slices[cso->zsbuf->u.tex.level].stride /
 437                          rsc->cpp);
 438         }
 439
 440         vc4->dirty |= VC4_DIRTY_FRAMEBUFFER;
 441 }
 442
 443 static struct vc4_texture_stateobj *
 444 vc4_get_stage_tex(struct vc4_context *vc4, enum pipe_shader_type shader)
 445 {
 446         switch (shader) {
 447         case PIPE_SHADER_FRAGMENT:
 448                 vc4->dirty |= VC4_DIRTY_FRAGTEX;
 449                 return &vc4->fragtex;
 450                 break;
 451         case PIPE_SHADER_VERTEX:
 452                 vc4->dirty |= VC4_DIRTY_VERTTEX;
 453                 return &vc4->verttex;
 454                 break;
 455         default:
 456                 fprintf(stderr, "Unknown shader target %d\n", shader);
 457                 abort();
 458         }
 459 }
 460
 461 static uint32_t translate_wrap(uint32_t p_wrap, bool using_nearest)
 462 {
 463         switch (p_wrap) {
 464         case PIPE_TEX_WRAP_REPEAT:
 465                 return 0;
 466         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 467                 return 1;
 468         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 469                 return 2;
 470         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 471                 return 3;
 472         case PIPE_TEX_WRAP_CLAMP:
 473                 return (using_nearest ? 1 : 3);
 474         default:
 475                 fprintf(stderr, "Unknown wrap mode %d\n", p_wrap);
 476                 assert(!"not reached");
 477                 return 0;
 478         }
 479 }
 480
 481 static void *
 482 vc4_create_sampler_state(struct pipe_context *pctx,
 483                          const struct pipe_sampler_state *cso)
 484 {
 485         static const uint8_t minfilter_map[6] = {
 486                 VC4_TEX_P1_MINFILT_NEAR_MIP_NEAR,
 487                 VC4_TEX_P1_MINFILT_LIN_MIP_NEAR,
 488                 VC4_TEX_P1_MINFILT_NEAR_MIP_LIN,
 489                 VC4_TEX_P1_MINFILT_LIN_MIP_LIN,
 490                 VC4_TEX_P1_MINFILT_NEAREST,
 491                 VC4_TEX_P1_MINFILT_LINEAR,
 492         };
 493         static const uint32_t magfilter_map[] = {
 494                 [PIPE_TEX_FILTER_NEAREST] = VC4_TEX_P1_MAGFILT_NEAREST,
 495                 [PIPE_TEX_FILTER_LINEAR] = VC4_TEX_P1_MAGFILT_LINEAR,
 496         };
 497         bool either_nearest =
 498                 (cso->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
 499                  cso->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
 500         struct vc4_sampler_state *so = CALLOC_STRUCT(vc4_sampler_state);
 501
 502         if (!so)
 503                 return NULL;
 504
 505         memcpy(so, cso, sizeof(*cso));
 506
 507         so->texture_p1 =
 508                 (VC4_SET_FIELD(magfilter_map[cso->mag_img_filter],
 509                                VC4_TEX_P1_MAGFILT) |
 510                  VC4_SET_FIELD(minfilter_map[cso->min_mip_filter * 2 +
 511                                              cso->min_img_filter],
 512                                VC4_TEX_P1_MINFILT) |
 513                  VC4_SET_FIELD(translate_wrap(cso->wrap_s, either_nearest),
 514                                VC4_TEX_P1_WRAP_S) |
 515                  VC4_SET_FIELD(translate_wrap(cso->wrap_t, either_nearest),
 516                                VC4_TEX_P1_WRAP_T));
 517
 518         return so;
 519 }
 520
 521 static void
 522 vc4_sampler_states_bind(struct pipe_context *pctx,
 523                         enum pipe_shader_type shader, unsigned start,
 524                         unsigned nr, void **hwcso)
 525 {
 526         struct vc4_context *vc4 = vc4_context(pctx);
 527         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 528
 529         assert(start == 0);
 530         unsigned i;
 531         unsigned new_nr = 0;
 532
 533         for (i = 0; i < nr; i++) {
 534                 if (hwcso[i])
 535                         new_nr = i + 1;
 536                 stage_tex->samplers[i] = hwcso[i];
 537         }
 538
 539         for (; i < stage_tex->num_samplers; i++) {
 540                 stage_tex->samplers[i] = NULL;
 541         }
 542
 543         stage_tex->num_samplers = new_nr;
 544 }
 545
 546 static struct pipe_sampler_view *
 547 vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
 548                         const struct pipe_sampler_view *cso)
 549 {
 550         struct vc4_sampler_view *so = CALLOC_STRUCT(vc4_sampler_view);
 551         struct vc4_resource *rsc = vc4_resource(prsc);
 552
 553         if (!so)
 554                 return NULL;
 555
 556         so->base = *cso;
 557
 558         pipe_reference(NULL, &prsc->reference);
 559         so->base.texture = prsc;
 560         so->base.reference.count = 1;
 561         so->base.context = pctx;
 562
 563         /* There is no hardware level clamping, and the start address of a
 564          * texture may be misaligned, so in that case we have to copy to a
 565          * temporary.
 566          *
 567          * Also, Raspberry Pi doesn't support sampling from raster textures,
 568          * so we also have to copy to a temporary then.
 569          */
 570         if ((cso->u.tex.first_level &&
 571              (cso->u.tex.first_level != cso->u.tex.last_level)) ||
 572             rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R) {
 573                 struct vc4_resource *shadow_parent = rsc;
 574                 struct pipe_resource tmpl = *prsc;
 575
 576                 tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET;
 577                 tmpl.width0 = u_minify(tmpl.width0, cso->u.tex.first_level);
 578                 tmpl.height0 = u_minify(tmpl.height0, cso->u.tex.first_level);
 579                 tmpl.last_level = cso->u.tex.last_level - cso->u.tex.first_level;
 580
 581                 /* Create the shadow texture.  The rest of the texture
 582                  * parameter setup will use the shadow.
 583                  */
 584                 prsc = vc4_resource_create(pctx->screen, &tmpl);
 585                 if (!prsc) {
 586                         free(so);
 587                         return NULL;
 588                 }
 589                 rsc = vc4_resource(prsc);
 590
 591                 /* Flag it as needing update of the contents from the parent. */
 592                 rsc->writes = shadow_parent->writes - 1;
 593                 assert(rsc->vc4_format != VC4_TEXTURE_TYPE_RGBA32R);
 594
 595                 so->texture = prsc;
 596         } else {
 597                 pipe_resource_reference(&so->texture, prsc);
 598
 599                 if (cso->u.tex.first_level) {
 600                         so->force_first_level = true;
 601                 }
 602         }
 603
 604         so->texture_p0 =
 605                 (VC4_SET_FIELD(rsc->slices[0].offset >> 12, VC4_TEX_P0_OFFSET) |
 606                  VC4_SET_FIELD(rsc->vc4_format & 15, VC4_TEX_P0_TYPE) |
 607                  VC4_SET_FIELD(so->force_first_level ?
 608                                cso->u.tex.last_level :
 609                                cso->u.tex.last_level -
 610                                cso->u.tex.first_level, VC4_TEX_P0_MIPLVLS) |
 611                  VC4_SET_FIELD(cso->target == PIPE_TEXTURE_CUBE,
 612                                VC4_TEX_P0_CMMODE));
 613         so->texture_p1 =
 614                 (VC4_SET_FIELD(rsc->vc4_format >> 4, VC4_TEX_P1_TYPE4) |
 615                  VC4_SET_FIELD(prsc->height0 & 2047, VC4_TEX_P1_HEIGHT) |
 616                  VC4_SET_FIELD(prsc->width0 & 2047, VC4_TEX_P1_WIDTH));
 617
 618         if (prsc->format == PIPE_FORMAT_ETC1_RGB8)
 619                 so->texture_p1 |= VC4_TEX_P1_ETCFLIP_MASK;
 620
 621         return &so->base;
 622 }
 623
 624 static void
 625 vc4_sampler_view_destroy(struct pipe_context *pctx,
 626                          struct pipe_sampler_view *pview)
 627 {
 628         struct vc4_sampler_view *view = vc4_sampler_view(pview);
 629         pipe_resource_reference(&pview->texture, NULL);
 630         pipe_resource_reference(&view->texture, NULL);
 631         free(view);
 632 }
 633
 634 static void
 635 vc4_set_sampler_views(struct pipe_context *pctx,
 636                       enum pipe_shader_type shader,
 637                       unsigned start, unsigned nr,
 638                       struct pipe_sampler_view **views)
 639 {
 640         struct vc4_context *vc4 = vc4_context(pctx);
 641         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 642         unsigned i;
 643         unsigned new_nr = 0;
 644
 645         assert(start == 0);
 646
 647         for (i = 0; i < nr; i++) {
 648                 if (views[i])
 649                         new_nr = i + 1;
 650                 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
 651         }
 652
 653         for (; i < stage_tex->num_textures; i++) {
 654                 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
 655         }
 656
 657         stage_tex->num_textures = new_nr;
 658 }
 659
 660 void
 661 vc4_state_init(struct pipe_context *pctx)
 662 {
 663         pctx->set_blend_color = vc4_set_blend_color;
 664         pctx->set_stencil_ref = vc4_set_stencil_ref;
 665         pctx->set_clip_state = vc4_set_clip_state;
 666         pctx->set_sample_mask = vc4_set_sample_mask;
 667         pctx->set_constant_buffer = vc4_set_constant_buffer;
 668         pctx->set_framebuffer_state = vc4_set_framebuffer_state;
 669         pctx->set_polygon_stipple = vc4_set_polygon_stipple;
 670         pctx->set_scissor_states = vc4_set_scissor_states;
 671         pctx->set_viewport_states = vc4_set_viewport_states;
 672
 673         pctx->set_vertex_buffers = vc4_set_vertex_buffers;
 674
 675         pctx->create_blend_state = vc4_create_blend_state;
 676         pctx->bind_blend_state = vc4_blend_state_bind;
 677         pctx->delete_blend_state = vc4_generic_cso_state_delete;
 678
 679         pctx->create_rasterizer_state = vc4_create_rasterizer_state;
 680         pctx->bind_rasterizer_state = vc4_rasterizer_state_bind;
 681         pctx->delete_rasterizer_state = vc4_generic_cso_state_delete;
 682
 683         pctx->create_depth_stencil_alpha_state = vc4_create_depth_stencil_alpha_state;
 684         pctx->bind_depth_stencil_alpha_state = vc4_zsa_state_bind;
 685         pctx->delete_depth_stencil_alpha_state = vc4_generic_cso_state_delete;
 686
 687         pctx->create_vertex_elements_state = vc4_vertex_state_create;
 688         pctx->delete_vertex_elements_state = vc4_generic_cso_state_delete;
 689         pctx->bind_vertex_elements_state = vc4_vertex_state_bind;
 690
 691         pctx->create_sampler_state = vc4_create_sampler_state;
 692         pctx->delete_sampler_state = vc4_generic_cso_state_delete;
 693         pctx->bind_sampler_states = vc4_sampler_states_bind;
 694
 695         pctx->create_sampler_view = vc4_create_sampler_view;
 696         pctx->sampler_view_destroy = vc4_sampler_view_destroy;
 697         pctx->set_sampler_views = vc4_set_sampler_views;
 698 }