2 * Copyright © 2014 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "pipe/p_state.h"
26 #include "util/u_inlines.h"
27 #include "util/u_math.h"
28 #include "util/u_memory.h"
29 #include "util/u_helpers.h"
31 #include "vc4_context.h"
34 vc4_generic_cso_state_create(const void *src
, uint32_t size
)
36 void *dst
= calloc(1, size
);
39 memcpy(dst
, src
, size
);
44 vc4_generic_cso_state_delete(struct pipe_context
*pctx
, void *hwcso
)
50 vc4_set_blend_color(struct pipe_context
*pctx
,
51 const struct pipe_blend_color
*blend_color
)
53 struct vc4_context
*vc4
= vc4_context(pctx
);
54 vc4
->blend_color
= *blend_color
;
55 vc4
->dirty
|= VC4_DIRTY_BLEND_COLOR
;
59 vc4_set_stencil_ref(struct pipe_context
*pctx
,
60 const struct pipe_stencil_ref
*stencil_ref
)
62 struct vc4_context
*vc4
= vc4_context(pctx
);
63 vc4
->stencil_ref
=* stencil_ref
;
64 vc4
->dirty
|= VC4_DIRTY_STENCIL_REF
;
68 vc4_set_clip_state(struct pipe_context
*pctx
,
69 const struct pipe_clip_state
*clip
)
71 struct vc4_context
*vc4
= vc4_context(pctx
);
73 vc4
->dirty
|= VC4_DIRTY_CLIP
;
77 vc4_set_sample_mask(struct pipe_context
*pctx
, unsigned sample_mask
)
79 struct vc4_context
*vc4
= vc4_context(pctx
);
80 vc4
->sample_mask
= (uint16_t)sample_mask
;
81 vc4
->dirty
|= VC4_DIRTY_SAMPLE_MASK
;
85 float_to_187_half(float f
)
91 vc4_create_rasterizer_state(struct pipe_context
*pctx
,
92 const struct pipe_rasterizer_state
*cso
)
94 struct vc4_rasterizer_state
*so
;
96 so
= CALLOC_STRUCT(vc4_rasterizer_state
);
102 if (!(cso
->cull_face
& PIPE_FACE_FRONT
))
103 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT
;
104 if (!(cso
->cull_face
& PIPE_FACE_BACK
))
105 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK
;
107 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
110 so
->point_size
= MAX2(cso
->point_size
, .125);
113 so
->config_bits
[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES
;
115 if (cso
->offset_tri
) {
116 so
->config_bits
[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET
;
118 so
->offset_units
= float_to_187_half(cso
->offset_units
);
119 so
->offset_factor
= float_to_187_half(cso
->offset_scale
);
125 /* Blend state is baked into shaders. */
127 vc4_create_blend_state(struct pipe_context
*pctx
,
128 const struct pipe_blend_state
*cso
)
130 return vc4_generic_cso_state_create(cso
, sizeof(*cso
));
134 * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
135 * values, so you don't have to do a separate writemask setup.
138 tlb_stencil_setup_writemask(uint8_t mask
)
145 default: return 0xff;
150 tlb_stencil_setup_bits(const struct pipe_stencil_state
*state
,
151 uint8_t writemask_bits
)
153 static const uint8_t op_map
[] = {
154 [PIPE_STENCIL_OP_ZERO
] = 0,
155 [PIPE_STENCIL_OP_KEEP
] = 1,
156 [PIPE_STENCIL_OP_REPLACE
] = 2,
157 [PIPE_STENCIL_OP_INCR
] = 3,
158 [PIPE_STENCIL_OP_DECR
] = 4,
159 [PIPE_STENCIL_OP_INVERT
] = 5,
160 [PIPE_STENCIL_OP_INCR_WRAP
] = 6,
161 [PIPE_STENCIL_OP_DECR_WRAP
] = 7,
165 if (writemask_bits
!= 0xff)
166 bits
|= writemask_bits
<< 28;
167 bits
|= op_map
[state
->zfail_op
] << 25;
168 bits
|= op_map
[state
->zpass_op
] << 22;
169 bits
|= op_map
[state
->fail_op
] << 19;
170 bits
|= state
->func
<< 16;
171 /* Ref is filled in at uniform upload time */
172 bits
|= state
->valuemask
<< 0;
178 vc4_create_depth_stencil_alpha_state(struct pipe_context
*pctx
,
179 const struct pipe_depth_stencil_alpha_state
*cso
)
181 struct vc4_depth_stencil_alpha_state
*so
;
183 so
= CALLOC_STRUCT(vc4_depth_stencil_alpha_state
);
189 if (cso
->depth
.enabled
) {
190 if (cso
->depth
.writemask
) {
191 so
->config_bits
[1] |= VC4_CONFIG_BITS_Z_UPDATE
;
193 so
->config_bits
[1] |= (cso
->depth
.func
<<
194 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
196 so
->config_bits
[1] |= (PIPE_FUNC_ALWAYS
<<
197 VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT
);
200 if (cso
->stencil
[0].enabled
) {
201 const struct pipe_stencil_state
*front
= &cso
->stencil
[0];
202 const struct pipe_stencil_state
*back
= &cso
->stencil
[1];
204 uint8_t front_writemask_bits
=
205 tlb_stencil_setup_writemask(front
->writemask
);
206 uint8_t back_writemask
= front
->writemask
;
207 uint8_t back_writemask_bits
= front_writemask_bits
;
209 so
->stencil_uniforms
[0] =
210 tlb_stencil_setup_bits(front
, front_writemask_bits
);
212 back_writemask
= back
->writemask
;
213 back_writemask_bits
=
214 tlb_stencil_setup_writemask(back
->writemask
);
216 so
->stencil_uniforms
[0] |= (1 << 30);
217 so
->stencil_uniforms
[1] =
218 tlb_stencil_setup_bits(back
, back_writemask_bits
);
219 so
->stencil_uniforms
[1] |= (2 << 30);
221 so
->stencil_uniforms
[0] |= (3 << 30);
224 if (front_writemask_bits
== 0xff ||
225 back_writemask_bits
== 0xff) {
226 so
->stencil_uniforms
[2] = (front_writemask_bits
|
227 (back_writemask_bits
<< 8));
235 vc4_set_polygon_stipple(struct pipe_context
*pctx
,
236 const struct pipe_poly_stipple
*stipple
)
238 struct vc4_context
*vc4
= vc4_context(pctx
);
239 vc4
->stipple
= *stipple
;
240 vc4
->dirty
|= VC4_DIRTY_STIPPLE
;
244 vc4_set_scissor_states(struct pipe_context
*pctx
,
246 unsigned num_scissors
,
247 const struct pipe_scissor_state
*scissor
)
249 struct vc4_context
*vc4
= vc4_context(pctx
);
251 vc4
->scissor
= *scissor
;
252 vc4
->dirty
|= VC4_DIRTY_SCISSOR
;
256 vc4_set_viewport_states(struct pipe_context
*pctx
,
258 unsigned num_viewports
,
259 const struct pipe_viewport_state
*viewport
)
261 struct vc4_context
*vc4
= vc4_context(pctx
);
262 vc4
->viewport
= *viewport
;
263 vc4
->dirty
|= VC4_DIRTY_VIEWPORT
;
267 vc4_set_vertex_buffers(struct pipe_context
*pctx
,
268 unsigned start_slot
, unsigned count
,
269 const struct pipe_vertex_buffer
*vb
)
271 struct vc4_context
*vc4
= vc4_context(pctx
);
272 struct vc4_vertexbuf_stateobj
*so
= &vc4
->vertexbuf
;
274 util_set_vertex_buffers_mask(so
->vb
, &so
->enabled_mask
, vb
,
276 so
->count
= util_last_bit(so
->enabled_mask
);
278 vc4
->dirty
|= VC4_DIRTY_VTXBUF
;
282 vc4_set_index_buffer(struct pipe_context
*pctx
,
283 const struct pipe_index_buffer
*ib
)
285 struct vc4_context
*vc4
= vc4_context(pctx
);
288 assert(!ib
->user_buffer
);
290 if (ib
->index_size
== 4) {
291 struct pipe_resource tmpl
= *ib
->buffer
;
292 assert(tmpl
.format
== PIPE_FORMAT_R8_UNORM
);
293 assert(tmpl
.height0
== 1);
294 tmpl
.width0
= (tmpl
.width0
- ib
->offset
) / 2;
295 struct pipe_resource
*pshadow
=
296 vc4_resource_create(&vc4
->screen
->base
, &tmpl
);
297 struct vc4_resource
*shadow
= vc4_resource(pshadow
);
298 pipe_resource_reference(&shadow
->shadow_parent
, ib
->buffer
);
300 pipe_resource_reference(&vc4
->indexbuf
.buffer
, NULL
);
301 vc4
->indexbuf
.buffer
= pshadow
;
302 vc4
->indexbuf
.index_size
= 2;
303 vc4
->indexbuf
.offset
= 0;
305 pipe_resource_reference(&vc4
->indexbuf
.buffer
, ib
->buffer
);
306 vc4
->indexbuf
.index_size
= ib
->index_size
;
307 vc4
->indexbuf
.offset
= ib
->offset
;
310 pipe_resource_reference(&vc4
->indexbuf
.buffer
, NULL
);
313 vc4
->dirty
|= VC4_DIRTY_INDEXBUF
;
317 vc4_blend_state_bind(struct pipe_context
*pctx
, void *hwcso
)
319 struct vc4_context
*vc4
= vc4_context(pctx
);
321 vc4
->dirty
|= VC4_DIRTY_BLEND
;
325 vc4_rasterizer_state_bind(struct pipe_context
*pctx
, void *hwcso
)
327 struct vc4_context
*vc4
= vc4_context(pctx
);
328 struct vc4_rasterizer_state
*rast
= hwcso
;
330 if (vc4
->rasterizer
&& rast
&&
331 vc4
->rasterizer
->base
.flatshade
!= rast
->base
.flatshade
) {
332 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
335 vc4
->rasterizer
= hwcso
;
336 vc4
->dirty
|= VC4_DIRTY_RASTERIZER
;
340 vc4_zsa_state_bind(struct pipe_context
*pctx
, void *hwcso
)
342 struct vc4_context
*vc4
= vc4_context(pctx
);
344 vc4
->dirty
|= VC4_DIRTY_ZSA
;
348 vc4_vertex_state_create(struct pipe_context
*pctx
, unsigned num_elements
,
349 const struct pipe_vertex_element
*elements
)
351 struct vc4_vertex_stateobj
*so
= CALLOC_STRUCT(vc4_vertex_stateobj
);
356 memcpy(so
->pipe
, elements
, sizeof(*elements
) * num_elements
);
357 so
->num_elements
= num_elements
;
363 vc4_vertex_state_bind(struct pipe_context
*pctx
, void *hwcso
)
365 struct vc4_context
*vc4
= vc4_context(pctx
);
367 vc4
->dirty
|= VC4_DIRTY_VTXSTATE
;
371 vc4_set_constant_buffer(struct pipe_context
*pctx
, uint shader
, uint index
,
372 struct pipe_constant_buffer
*cb
)
374 struct vc4_context
*vc4
= vc4_context(pctx
);
375 struct vc4_constbuf_stateobj
*so
= &vc4
->constbuf
[shader
];
379 /* Note that the state tracker can unbind constant buffers by
383 so
->enabled_mask
&= ~(1 << index
);
384 so
->dirty_mask
&= ~(1 << index
);
389 so
->cb
[index
].buffer_offset
= cb
->buffer_offset
;
390 so
->cb
[index
].buffer_size
= cb
->buffer_size
;
391 so
->cb
[index
].user_buffer
= cb
->user_buffer
;
393 so
->enabled_mask
|= 1 << index
;
394 so
->dirty_mask
|= 1 << index
;
395 vc4
->dirty
|= VC4_DIRTY_CONSTBUF
;
399 vc4_set_framebuffer_state(struct pipe_context
*pctx
,
400 const struct pipe_framebuffer_state
*framebuffer
)
402 struct vc4_context
*vc4
= vc4_context(pctx
);
403 struct pipe_framebuffer_state
*cso
= &vc4
->framebuffer
;
408 for (i
= 0; i
< framebuffer
->nr_cbufs
; i
++)
409 pipe_surface_reference(&cso
->cbufs
[i
], framebuffer
->cbufs
[i
]);
410 for (; i
< vc4
->framebuffer
.nr_cbufs
; i
++)
411 pipe_surface_reference(&cso
->cbufs
[i
], NULL
);
413 cso
->nr_cbufs
= framebuffer
->nr_cbufs
;
415 pipe_surface_reference(&cso
->zsbuf
, framebuffer
->zsbuf
);
417 cso
->width
= framebuffer
->width
;
418 cso
->height
= framebuffer
->height
;
420 /* Nonzero texture mipmap levels are laid out as if they were in
421 * power-of-two-sized spaces. The renderbuffer config infers its
422 * stride from the width parameter, so we need to configure our
423 * framebuffer. Note that if the z/color buffers were mismatched
424 * sizes, we wouldn't be able to do this.
426 if (cso
->cbufs
[0] && cso
->cbufs
[0]->u
.tex
.level
) {
427 struct vc4_resource
*rsc
=
428 vc4_resource(cso
->cbufs
[0]->texture
);
430 (rsc
->slices
[cso
->cbufs
[0]->u
.tex
.level
].stride
/
432 } else if (cso
->zsbuf
&& cso
->zsbuf
->u
.tex
.level
){
433 struct vc4_resource
*rsc
=
434 vc4_resource(cso
->zsbuf
->texture
);
436 (rsc
->slices
[cso
->zsbuf
->u
.tex
.level
].stride
/
440 vc4
->dirty
|= VC4_DIRTY_FRAMEBUFFER
;
443 static struct vc4_texture_stateobj
*
444 vc4_get_stage_tex(struct vc4_context
*vc4
, unsigned shader
)
446 vc4
->dirty
|= VC4_DIRTY_TEXSTATE
;
449 case PIPE_SHADER_FRAGMENT
:
450 vc4
->dirty
|= VC4_DIRTY_FRAGTEX
;
451 return &vc4
->fragtex
;
453 case PIPE_SHADER_VERTEX
:
454 vc4
->dirty
|= VC4_DIRTY_VERTTEX
;
455 return &vc4
->verttex
;
458 fprintf(stderr
, "Unknown shader target %d\n", shader
);
464 vc4_create_sampler_state(struct pipe_context
*pctx
,
465 const struct pipe_sampler_state
*cso
)
467 return vc4_generic_cso_state_create(cso
, sizeof(*cso
));
471 vc4_sampler_states_bind(struct pipe_context
*pctx
,
472 unsigned shader
, unsigned start
,
473 unsigned nr
, void **hwcso
)
475 struct vc4_context
*vc4
= vc4_context(pctx
);
476 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
482 for (i
= 0; i
< nr
; i
++) {
485 stage_tex
->samplers
[i
] = hwcso
[i
];
486 stage_tex
->dirty_samplers
|= (1 << i
);
489 for (; i
< stage_tex
->num_samplers
; i
++) {
490 stage_tex
->samplers
[i
] = NULL
;
491 stage_tex
->dirty_samplers
|= (1 << i
);
494 stage_tex
->num_samplers
= new_nr
;
497 static struct pipe_sampler_view
*
498 vc4_create_sampler_view(struct pipe_context
*pctx
, struct pipe_resource
*prsc
,
499 const struct pipe_sampler_view
*cso
)
501 struct pipe_sampler_view
*so
= malloc(sizeof(*so
));
508 pipe_reference(NULL
, &prsc
->reference
);
510 /* There is no hardware level clamping, and the start address of a
511 * texture may be misaligned, so in that case we have to copy to a
514 if (so
->u
.tex
.first_level
) {
515 struct vc4_resource
*shadow_parent
= vc4_resource(prsc
);
516 struct pipe_resource tmpl
= shadow_parent
->base
.b
;
517 struct vc4_resource
*clone
;
519 tmpl
.width0
= u_minify(tmpl
.width0
, so
->u
.tex
.first_level
);
520 tmpl
.height0
= u_minify(tmpl
.height0
, so
->u
.tex
.first_level
);
521 tmpl
.last_level
= so
->u
.tex
.last_level
- so
->u
.tex
.first_level
;
523 prsc
= vc4_resource_create(pctx
->screen
, &tmpl
);
524 clone
= vc4_resource(prsc
);
525 clone
->shadow_parent
= &shadow_parent
->base
.b
;
526 /* Flag it as needing update of the contents from the parent. */
527 clone
->writes
= shadow_parent
->writes
- 1;
530 so
->reference
.count
= 1;
537 vc4_sampler_view_destroy(struct pipe_context
*pctx
,
538 struct pipe_sampler_view
*view
)
540 pipe_resource_reference(&view
->texture
, NULL
);
545 vc4_set_sampler_views(struct pipe_context
*pctx
, unsigned shader
,
546 unsigned start
, unsigned nr
,
547 struct pipe_sampler_view
**views
)
549 struct vc4_context
*vc4
= vc4_context(pctx
);
550 struct vc4_texture_stateobj
*stage_tex
= vc4_get_stage_tex(vc4
, shader
);
556 vc4
->dirty
|= VC4_DIRTY_TEXSTATE
;
558 for (i
= 0; i
< nr
; i
++) {
561 if (views
[i
]->u
.tex
.first_level
!= 0)
562 vc4_update_shadow_baselevel_texture(pctx
, views
[i
]);
564 pipe_sampler_view_reference(&stage_tex
->textures
[i
], views
[i
]);
565 stage_tex
->dirty_samplers
|= (1 << i
);
568 for (; i
< stage_tex
->num_textures
; i
++) {
569 pipe_sampler_view_reference(&stage_tex
->textures
[i
], NULL
);
570 stage_tex
->dirty_samplers
|= (1 << i
);
573 stage_tex
->num_textures
= new_nr
;
577 vc4_state_init(struct pipe_context
*pctx
)
579 pctx
->set_blend_color
= vc4_set_blend_color
;
580 pctx
->set_stencil_ref
= vc4_set_stencil_ref
;
581 pctx
->set_clip_state
= vc4_set_clip_state
;
582 pctx
->set_sample_mask
= vc4_set_sample_mask
;
583 pctx
->set_constant_buffer
= vc4_set_constant_buffer
;
584 pctx
->set_framebuffer_state
= vc4_set_framebuffer_state
;
585 pctx
->set_polygon_stipple
= vc4_set_polygon_stipple
;
586 pctx
->set_scissor_states
= vc4_set_scissor_states
;
587 pctx
->set_viewport_states
= vc4_set_viewport_states
;
589 pctx
->set_vertex_buffers
= vc4_set_vertex_buffers
;
590 pctx
->set_index_buffer
= vc4_set_index_buffer
;
592 pctx
->create_blend_state
= vc4_create_blend_state
;
593 pctx
->bind_blend_state
= vc4_blend_state_bind
;
594 pctx
->delete_blend_state
= vc4_generic_cso_state_delete
;
596 pctx
->create_rasterizer_state
= vc4_create_rasterizer_state
;
597 pctx
->bind_rasterizer_state
= vc4_rasterizer_state_bind
;
598 pctx
->delete_rasterizer_state
= vc4_generic_cso_state_delete
;
600 pctx
->create_depth_stencil_alpha_state
= vc4_create_depth_stencil_alpha_state
;
601 pctx
->bind_depth_stencil_alpha_state
= vc4_zsa_state_bind
;
602 pctx
->delete_depth_stencil_alpha_state
= vc4_generic_cso_state_delete
;
604 pctx
->create_vertex_elements_state
= vc4_vertex_state_create
;
605 pctx
->delete_vertex_elements_state
= vc4_generic_cso_state_delete
;
606 pctx
->bind_vertex_elements_state
= vc4_vertex_state_bind
;
608 pctx
->create_sampler_state
= vc4_create_sampler_state
;
609 pctx
->delete_sampler_state
= vc4_generic_cso_state_delete
;
610 pctx
->bind_sampler_states
= vc4_sampler_states_bind
;
612 pctx
->create_sampler_view
= vc4_create_sampler_view
;
613 pctx
->sampler_view_destroy
= vc4_sampler_view_destroy
;
614 pctx
->set_sampler_views
= vc4_set_sampler_views
;