src/gallium/drivers/vc4/vc4_state.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "pipe/p_state.h"
  26 #include "util/u_inlines.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_helpers.h"
  30
  31 #include "vc4_context.h"
  32
  33 static void *
  34 vc4_generic_cso_state_create(const void *src, uint32_t size)
  35 {
  36         void *dst = calloc(1, size);
  37         if (!dst)
  38                 return NULL;
  39         memcpy(dst, src, size);
  40         return dst;
  41 }
  42
  43 static void
  44 vc4_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
  45 {
  46         free(hwcso);
  47 }
  48
  49 static void
  50 vc4_set_blend_color(struct pipe_context *pctx,
  51                     const struct pipe_blend_color *blend_color)
  52 {
  53         struct vc4_context *vc4 = vc4_context(pctx);
  54         vc4->blend_color = *blend_color;
  55         vc4->dirty |= VC4_DIRTY_BLEND_COLOR;
  56 }
  57
  58 static void
  59 vc4_set_stencil_ref(struct pipe_context *pctx,
  60                     const struct pipe_stencil_ref *stencil_ref)
  61 {
  62         struct vc4_context *vc4 = vc4_context(pctx);
  63         vc4->stencil_ref =* stencil_ref;
  64         vc4->dirty |= VC4_DIRTY_STENCIL_REF;
  65 }
  66
  67 static void
  68 vc4_set_clip_state(struct pipe_context *pctx,
  69                    const struct pipe_clip_state *clip)
  70 {
  71         fprintf(stderr, "clip todo\n");
  72 }
  73
  74 static void
  75 vc4_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  76 {
  77         struct vc4_context *vc4 = vc4_context(pctx);
  78         vc4->sample_mask = (uint16_t)sample_mask;
  79         vc4->dirty |= VC4_DIRTY_SAMPLE_MASK;
  80 }
  81
  82 static uint16_t
  83 float_to_187_half(float f)
  84 {
  85         return fui(f) >> 16;
  86 }
  87
  88 static void *
  89 vc4_create_rasterizer_state(struct pipe_context *pctx,
  90                             const struct pipe_rasterizer_state *cso)
  91 {
  92         struct vc4_rasterizer_state *so;
  93
  94         so = CALLOC_STRUCT(vc4_rasterizer_state);
  95         if (!so)
  96                 return NULL;
  97
  98         so->base = *cso;
  99
 100         if (!(cso->cull_face & PIPE_FACE_FRONT))
 101                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT;
 102         if (!(cso->cull_face & PIPE_FACE_BACK))
 103                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK;
 104
 105         /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
 106          * BCM21553).
 107          */
 108         so->point_size = MAX2(cso->point_size, .125);
 109
 110         if (cso->front_ccw)
 111                 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES;
 112
 113         if (cso->offset_tri) {
 114                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET;
 115
 116                 so->offset_units = float_to_187_half(cso->offset_units);
 117                 so->offset_factor = float_to_187_half(cso->offset_scale);
 118         }
 119
 120         return so;
 121 }
 122
 123 /* Blend state is baked into shaders. */
 124 static void *
 125 vc4_create_blend_state(struct pipe_context *pctx,
 126                        const struct pipe_blend_state *cso)
 127 {
 128         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 129 }
 130
 131 /**
 132  * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
 133  * values, so you don't have to do a separate writemask setup.
 134  */
 135 static uint8_t
 136 tlb_stencil_setup_writemask(uint8_t mask)
 137 {
 138         switch (mask) {
 139         case 0x1: return 0;
 140         case 0x3: return 1;
 141         case 0xf: return 2;
 142         case 0xff: return 3;
 143         default: return 0xff;
 144         }
 145 }
 146
 147 static uint32_t
 148 tlb_stencil_setup_bits(const struct pipe_stencil_state *state,
 149                        uint8_t writemask_bits)
 150 {
 151         static const uint8_t op_map[] = {
 152                 [PIPE_STENCIL_OP_ZERO] = 0,
 153                 [PIPE_STENCIL_OP_KEEP] = 1,
 154                 [PIPE_STENCIL_OP_REPLACE] = 2,
 155                 [PIPE_STENCIL_OP_INCR] = 3,
 156                 [PIPE_STENCIL_OP_DECR] = 4,
 157                 [PIPE_STENCIL_OP_INVERT] = 5,
 158                 [PIPE_STENCIL_OP_INCR_WRAP] = 6,
 159                 [PIPE_STENCIL_OP_DECR_WRAP] = 7,
 160         };
 161         uint32_t bits = 0;
 162
 163         if (writemask_bits != 0xff)
 164                 bits |= writemask_bits << 28;
 165         bits |= op_map[state->zfail_op] << 25;
 166         bits |= op_map[state->zpass_op] << 22;
 167         bits |= op_map[state->fail_op] << 19;
 168         bits |= state->func << 16;
 169         /* Ref is filled in at uniform upload time */
 170         bits |= state->valuemask << 0;
 171
 172         return bits;
 173 }
 174
 175 static void *
 176 vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx,
 177                                      const struct pipe_depth_stencil_alpha_state *cso)
 178 {
 179         struct vc4_depth_stencil_alpha_state *so;
 180
 181         so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state);
 182         if (!so)
 183                 return NULL;
 184
 185         so->base = *cso;
 186
 187         if (cso->depth.enabled) {
 188                 if (cso->depth.writemask) {
 189                         so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE;
 190                 }
 191                 so->config_bits[1] |= (cso->depth.func <<
 192                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 193         } else {
 194                 so->config_bits[1] |= (PIPE_FUNC_ALWAYS <<
 195                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 196         }
 197
 198         if (cso->stencil[0].enabled) {
 199                 const struct pipe_stencil_state *front = &cso->stencil[0];
 200                 const struct pipe_stencil_state *back = &cso->stencil[1];
 201
 202                 uint8_t front_writemask_bits =
 203                         tlb_stencil_setup_writemask(front->writemask);
 204                 uint8_t back_writemask_bits =
 205                         tlb_stencil_setup_writemask(back->writemask);
 206
 207                 so->stencil_uniforms[0] =
 208                         tlb_stencil_setup_bits(front, front_writemask_bits);
 209                 if (back->enabled) {
 210                         so->stencil_uniforms[0] |= (1 << 30);
 211                         so->stencil_uniforms[1] =
 212                                 tlb_stencil_setup_bits(back, back_writemask_bits);
 213                         so->stencil_uniforms[1] |= (2 << 30);
 214                 } else {
 215                         so->stencil_uniforms[0] |= (3 << 30);
 216                 }
 217
 218                 if (front_writemask_bits == 0xff ||
 219                     back_writemask_bits == 0xff) {
 220                         so->stencil_uniforms[2] = (front_writemask_bits |
 221                                                    (back_writemask_bits << 8));
 222                 }
 223         }
 224
 225         return so;
 226 }
 227
 228 static void
 229 vc4_set_polygon_stipple(struct pipe_context *pctx,
 230                         const struct pipe_poly_stipple *stipple)
 231 {
 232         struct vc4_context *vc4 = vc4_context(pctx);
 233         vc4->stipple = *stipple;
 234         vc4->dirty |= VC4_DIRTY_STIPPLE;
 235 }
 236
 237 static void
 238 vc4_set_scissor_states(struct pipe_context *pctx,
 239                        unsigned start_slot,
 240                        unsigned num_scissors,
 241                        const struct pipe_scissor_state *scissor)
 242 {
 243         struct vc4_context *vc4 = vc4_context(pctx);
 244
 245         vc4->scissor = *scissor;
 246         vc4->dirty |= VC4_DIRTY_SCISSOR;
 247 }
 248
 249 static void
 250 vc4_set_viewport_states(struct pipe_context *pctx,
 251                         unsigned start_slot,
 252                         unsigned num_viewports,
 253                         const struct pipe_viewport_state *viewport)
 254 {
 255         struct vc4_context *vc4 = vc4_context(pctx);
 256         vc4->viewport = *viewport;
 257         vc4->dirty |= VC4_DIRTY_VIEWPORT;
 258 }
 259
 260 static void
 261 vc4_set_vertex_buffers(struct pipe_context *pctx,
 262                        unsigned start_slot, unsigned count,
 263                        const struct pipe_vertex_buffer *vb)
 264 {
 265         struct vc4_context *vc4 = vc4_context(pctx);
 266         struct vc4_vertexbuf_stateobj *so = &vc4->vertexbuf;
 267
 268         util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
 269                                      start_slot, count);
 270         so->count = util_last_bit(so->enabled_mask);
 271
 272         vc4->dirty |= VC4_DIRTY_VTXBUF;
 273 }
 274
 275 static void
 276 vc4_set_index_buffer(struct pipe_context *pctx,
 277                      const struct pipe_index_buffer *ib)
 278 {
 279         struct vc4_context *vc4 = vc4_context(pctx);
 280
 281         if (ib) {
 282                 pipe_resource_reference(&vc4->indexbuf.buffer, ib->buffer);
 283                 vc4->indexbuf.index_size = ib->index_size;
 284                 vc4->indexbuf.offset = ib->offset;
 285                 vc4->indexbuf.user_buffer = ib->user_buffer;
 286         } else {
 287                 pipe_resource_reference(&vc4->indexbuf.buffer, NULL);
 288         }
 289
 290         vc4->dirty |= VC4_DIRTY_INDEXBUF;
 291 }
 292
 293 static void
 294 vc4_blend_state_bind(struct pipe_context *pctx, void *hwcso)
 295 {
 296         struct vc4_context *vc4 = vc4_context(pctx);
 297         vc4->blend = hwcso;
 298         vc4->dirty |= VC4_DIRTY_BLEND;
 299 }
 300
 301 static void
 302 vc4_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
 303 {
 304         struct vc4_context *vc4 = vc4_context(pctx);
 305         struct vc4_rasterizer_state *rast = hwcso;
 306
 307         if (vc4->rasterizer && rast &&
 308             vc4->rasterizer->base.flatshade != rast->base.flatshade) {
 309                 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
 310         }
 311
 312         vc4->rasterizer = hwcso;
 313         vc4->dirty |= VC4_DIRTY_RASTERIZER;
 314 }
 315
 316 static void
 317 vc4_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
 318 {
 319         struct vc4_context *vc4 = vc4_context(pctx);
 320         vc4->zsa = hwcso;
 321         vc4->dirty |= VC4_DIRTY_ZSA;
 322 }
 323
 324 static void *
 325 vc4_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
 326                         const struct pipe_vertex_element *elements)
 327 {
 328         struct vc4_vertex_stateobj *so = CALLOC_STRUCT(vc4_vertex_stateobj);
 329
 330         if (!so)
 331                 return NULL;
 332
 333         memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
 334         so->num_elements = num_elements;
 335
 336         return so;
 337 }
 338
 339 static void
 340 vc4_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
 341 {
 342         struct vc4_context *vc4 = vc4_context(pctx);
 343         vc4->vtx = hwcso;
 344         vc4->dirty |= VC4_DIRTY_VTXSTATE;
 345 }
 346
 347 static void
 348 vc4_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
 349                         struct pipe_constant_buffer *cb)
 350 {
 351         struct vc4_context *vc4 = vc4_context(pctx);
 352         struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader];
 353
 354         assert(index == 0);
 355
 356         /* Note that the state tracker can unbind constant buffers by
 357          * passing NULL here.
 358          */
 359         if (unlikely(!cb)) {
 360                 so->enabled_mask &= ~(1 << index);
 361                 so->dirty_mask &= ~(1 << index);
 362                 return;
 363         }
 364
 365         assert(!cb->buffer);
 366         so->cb[index].buffer_offset = cb->buffer_offset;
 367         so->cb[index].buffer_size   = cb->buffer_size;
 368         so->cb[index].user_buffer   = cb->user_buffer;
 369
 370         so->enabled_mask |= 1 << index;
 371         so->dirty_mask |= 1 << index;
 372         vc4->dirty |= VC4_DIRTY_CONSTBUF;
 373 }
 374
 375 static void
 376 vc4_set_framebuffer_state(struct pipe_context *pctx,
 377                           const struct pipe_framebuffer_state *framebuffer)
 378 {
 379         struct vc4_context *vc4 = vc4_context(pctx);
 380         struct pipe_framebuffer_state *cso = &vc4->framebuffer;
 381         unsigned i;
 382
 383         vc4_flush(pctx);
 384
 385         for (i = 0; i < framebuffer->nr_cbufs; i++)
 386                 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
 387         for (; i < vc4->framebuffer.nr_cbufs; i++)
 388                 pipe_surface_reference(&cso->cbufs[i], NULL);
 389
 390         cso->nr_cbufs = framebuffer->nr_cbufs;
 391
 392         pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
 393
 394         cso->width = framebuffer->width;
 395         cso->height = framebuffer->height;
 396
 397         /* Nonzero texture mipmap levels are laid out as if they were in
 398          * power-of-two-sized spaces.  The renderbuffer config infers its
 399          * stride from the width parameter, so we need to configure our
 400          * framebuffer.  Note that if the z/color buffers were mismatched
 401          * sizes, we wouldn't be able to do this.
 402          */
 403         if (cso->cbufs[0] && cso->cbufs[0]->u.tex.level) {
 404                 struct vc4_resource *rsc =
 405                         vc4_resource(cso->cbufs[0]->texture);
 406                 cso->width =
 407                         (rsc->slices[cso->cbufs[0]->u.tex.level].stride /
 408                          rsc->cpp);
 409         } else if (cso->zsbuf && cso->zsbuf->u.tex.level){
 410                 struct vc4_resource *rsc =
 411                         vc4_resource(cso->zsbuf->texture);
 412                 cso->width =
 413                         (rsc->slices[cso->zsbuf->u.tex.level].stride /
 414                          rsc->cpp);
 415         }
 416
 417         vc4->dirty |= VC4_DIRTY_FRAMEBUFFER;
 418 }
 419
 420 static struct vc4_texture_stateobj *
 421 vc4_get_stage_tex(struct vc4_context *vc4, unsigned shader)
 422 {
 423         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 424
 425         switch (shader) {
 426         case PIPE_SHADER_FRAGMENT:
 427                 vc4->dirty |= VC4_DIRTY_FRAGTEX;
 428                 return &vc4->fragtex;
 429                 break;
 430         case PIPE_SHADER_VERTEX:
 431                 vc4->dirty |= VC4_DIRTY_VERTTEX;
 432                 return &vc4->verttex;
 433                 break;
 434         default:
 435                 fprintf(stderr, "Unknown shader target %d\n", shader);
 436                 abort();
 437         }
 438 }
 439
 440 static void *
 441 vc4_create_sampler_state(struct pipe_context *pctx,
 442                          const struct pipe_sampler_state *cso)
 443 {
 444         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 445 }
 446
 447 static void
 448 vc4_sampler_states_bind(struct pipe_context *pctx,
 449                         unsigned shader, unsigned start,
 450                         unsigned nr, void **hwcso)
 451 {
 452         struct vc4_context *vc4 = vc4_context(pctx);
 453         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 454
 455         assert(start == 0);
 456         unsigned i;
 457         unsigned new_nr = 0;
 458
 459         for (i = 0; i < nr; i++) {
 460                 if (hwcso[i])
 461                         new_nr = i + 1;
 462                 stage_tex->samplers[i] = hwcso[i];
 463                 stage_tex->dirty_samplers |= (1 << i);
 464         }
 465
 466         for (; i < stage_tex->num_samplers; i++) {
 467                 stage_tex->samplers[i] = NULL;
 468                 stage_tex->dirty_samplers |= (1 << i);
 469         }
 470
 471         stage_tex->num_samplers = new_nr;
 472 }
 473
 474 static struct pipe_sampler_view *
 475 vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
 476                         const struct pipe_sampler_view *cso)
 477 {
 478         struct pipe_sampler_view *so = malloc(sizeof(*so));
 479
 480         if (!so)
 481                 return NULL;
 482
 483         *so = *cso;
 484         pipe_reference(NULL, &prsc->reference);
 485         so->texture = prsc;
 486         so->reference.count = 1;
 487         so->context = pctx;
 488
 489         return so;
 490 }
 491
 492 static void
 493 vc4_sampler_view_destroy(struct pipe_context *pctx,
 494                          struct pipe_sampler_view *view)
 495 {
 496         pipe_resource_reference(&view->texture, NULL);
 497         free(view);
 498 }
 499
 500 static void
 501 vc4_set_sampler_views(struct pipe_context *pctx, unsigned shader,
 502                       unsigned start, unsigned nr,
 503                       struct pipe_sampler_view **views)
 504 {
 505         struct vc4_context *vc4 = vc4_context(pctx);
 506         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 507         unsigned i;
 508         unsigned new_nr = 0;
 509
 510         assert(start == 0);
 511
 512         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 513
 514         for (i = 0; i < nr; i++) {
 515                 if (views[i])
 516                         new_nr = i + 1;
 517                 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
 518                 stage_tex->dirty_samplers |= (1 << i);
 519         }
 520
 521         for (; i < stage_tex->num_textures; i++) {
 522                 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
 523                 stage_tex->dirty_samplers |= (1 << i);
 524         }
 525
 526         stage_tex->num_textures = new_nr;
 527 }
 528
 529 void
 530 vc4_state_init(struct pipe_context *pctx)
 531 {
 532         pctx->set_blend_color = vc4_set_blend_color;
 533         pctx->set_stencil_ref = vc4_set_stencil_ref;
 534         pctx->set_clip_state = vc4_set_clip_state;
 535         pctx->set_sample_mask = vc4_set_sample_mask;
 536         pctx->set_constant_buffer = vc4_set_constant_buffer;
 537         pctx->set_framebuffer_state = vc4_set_framebuffer_state;
 538         pctx->set_polygon_stipple = vc4_set_polygon_stipple;
 539         pctx->set_scissor_states = vc4_set_scissor_states;
 540         pctx->set_viewport_states = vc4_set_viewport_states;
 541
 542         pctx->set_vertex_buffers = vc4_set_vertex_buffers;
 543         pctx->set_index_buffer = vc4_set_index_buffer;
 544
 545         pctx->create_blend_state = vc4_create_blend_state;
 546         pctx->bind_blend_state = vc4_blend_state_bind;
 547         pctx->delete_blend_state = vc4_generic_cso_state_delete;
 548
 549         pctx->create_rasterizer_state = vc4_create_rasterizer_state;
 550         pctx->bind_rasterizer_state = vc4_rasterizer_state_bind;
 551         pctx->delete_rasterizer_state = vc4_generic_cso_state_delete;
 552
 553         pctx->create_depth_stencil_alpha_state = vc4_create_depth_stencil_alpha_state;
 554         pctx->bind_depth_stencil_alpha_state = vc4_zsa_state_bind;
 555         pctx->delete_depth_stencil_alpha_state = vc4_generic_cso_state_delete;
 556
 557         pctx->create_vertex_elements_state = vc4_vertex_state_create;
 558         pctx->delete_vertex_elements_state = vc4_generic_cso_state_delete;
 559         pctx->bind_vertex_elements_state = vc4_vertex_state_bind;
 560
 561         pctx->create_sampler_state = vc4_create_sampler_state;
 562         pctx->delete_sampler_state = vc4_generic_cso_state_delete;
 563         pctx->bind_sampler_states = vc4_sampler_states_bind;
 564
 565         pctx->create_sampler_view = vc4_create_sampler_view;
 566         pctx->sampler_view_destroy = vc4_sampler_view_destroy;
 567         pctx->set_sampler_views = vc4_set_sampler_views;
 568 }