src/gallium/drivers/vc4/vc4_state.c

   1 /*
   2  * Copyright © 2014 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "pipe/p_state.h"
  26 #include "util/u_inlines.h"
  27 #include "util/u_math.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_helpers.h"
  30
  31 #include "vc4_context.h"
  32
  33 static void *
  34 vc4_generic_cso_state_create(const void *src, uint32_t size)
  35 {
  36         void *dst = calloc(1, size);
  37         if (!dst)
  38                 return NULL;
  39         memcpy(dst, src, size);
  40         return dst;
  41 }
  42
  43 static void
  44 vc4_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
  45 {
  46         free(hwcso);
  47 }
  48
  49 static void
  50 vc4_set_blend_color(struct pipe_context *pctx,
  51                     const struct pipe_blend_color *blend_color)
  52 {
  53         struct vc4_context *vc4 = vc4_context(pctx);
  54         vc4->blend_color = *blend_color;
  55         vc4->dirty |= VC4_DIRTY_BLEND_COLOR;
  56 }
  57
  58 static void
  59 vc4_set_stencil_ref(struct pipe_context *pctx,
  60                     const struct pipe_stencil_ref *stencil_ref)
  61 {
  62         struct vc4_context *vc4 = vc4_context(pctx);
  63         vc4->stencil_ref =* stencil_ref;
  64         vc4->dirty |= VC4_DIRTY_STENCIL_REF;
  65 }
  66
  67 static void
  68 vc4_set_clip_state(struct pipe_context *pctx,
  69                    const struct pipe_clip_state *clip)
  70 {
  71         struct vc4_context *vc4 = vc4_context(pctx);
  72         vc4->clip = *clip;
  73         vc4->dirty |= VC4_DIRTY_CLIP;
  74 }
  75
  76 static void
  77 vc4_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
  78 {
  79         struct vc4_context *vc4 = vc4_context(pctx);
  80         vc4->sample_mask = (uint16_t)sample_mask;
  81         vc4->dirty |= VC4_DIRTY_SAMPLE_MASK;
  82 }
  83
  84 static uint16_t
  85 float_to_187_half(float f)
  86 {
  87         return fui(f) >> 16;
  88 }
  89
  90 static void *
  91 vc4_create_rasterizer_state(struct pipe_context *pctx,
  92                             const struct pipe_rasterizer_state *cso)
  93 {
  94         struct vc4_rasterizer_state *so;
  95
  96         so = CALLOC_STRUCT(vc4_rasterizer_state);
  97         if (!so)
  98                 return NULL;
  99
 100         so->base = *cso;
 101
 102         if (!(cso->cull_face & PIPE_FACE_FRONT))
 103                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT;
 104         if (!(cso->cull_face & PIPE_FACE_BACK))
 105                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK;
 106
 107         /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
 108          * BCM21553).
 109          */
 110         so->point_size = MAX2(cso->point_size, .125);
 111
 112         if (cso->front_ccw)
 113                 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES;
 114
 115         if (cso->offset_tri) {
 116                 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET;
 117
 118                 so->offset_units = float_to_187_half(cso->offset_units);
 119                 so->offset_factor = float_to_187_half(cso->offset_scale);
 120         }
 121
 122         return so;
 123 }
 124
 125 /* Blend state is baked into shaders. */
 126 static void *
 127 vc4_create_blend_state(struct pipe_context *pctx,
 128                        const struct pipe_blend_state *cso)
 129 {
 130         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 131 }
 132
 133 /**
 134  * The TLB_STENCIL_SETUP data has a little bitfield for common writemask
 135  * values, so you don't have to do a separate writemask setup.
 136  */
 137 static uint8_t
 138 tlb_stencil_setup_writemask(uint8_t mask)
 139 {
 140         switch (mask) {
 141         case 0x1: return 0;
 142         case 0x3: return 1;
 143         case 0xf: return 2;
 144         case 0xff: return 3;
 145         default: return 0xff;
 146         }
 147 }
 148
 149 static uint32_t
 150 tlb_stencil_setup_bits(const struct pipe_stencil_state *state,
 151                        uint8_t writemask_bits)
 152 {
 153         static const uint8_t op_map[] = {
 154                 [PIPE_STENCIL_OP_ZERO] = 0,
 155                 [PIPE_STENCIL_OP_KEEP] = 1,
 156                 [PIPE_STENCIL_OP_REPLACE] = 2,
 157                 [PIPE_STENCIL_OP_INCR] = 3,
 158                 [PIPE_STENCIL_OP_DECR] = 4,
 159                 [PIPE_STENCIL_OP_INVERT] = 5,
 160                 [PIPE_STENCIL_OP_INCR_WRAP] = 6,
 161                 [PIPE_STENCIL_OP_DECR_WRAP] = 7,
 162         };
 163         uint32_t bits = 0;
 164
 165         if (writemask_bits != 0xff)
 166                 bits |= writemask_bits << 28;
 167         bits |= op_map[state->zfail_op] << 25;
 168         bits |= op_map[state->zpass_op] << 22;
 169         bits |= op_map[state->fail_op] << 19;
 170         bits |= state->func << 16;
 171         /* Ref is filled in at uniform upload time */
 172         bits |= state->valuemask << 0;
 173
 174         return bits;
 175 }
 176
 177 static void *
 178 vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx,
 179                                      const struct pipe_depth_stencil_alpha_state *cso)
 180 {
 181         struct vc4_depth_stencil_alpha_state *so;
 182
 183         so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state);
 184         if (!so)
 185                 return NULL;
 186
 187         so->base = *cso;
 188
 189         /* We always keep the early Z state correct, since a later state using
 190          * early Z may want it.
 191          */
 192         so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE;
 193
 194         if (cso->depth.enabled) {
 195                 if (cso->depth.writemask) {
 196                         so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE;
 197                 }
 198                 so->config_bits[1] |= (cso->depth.func <<
 199                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 200
 201                 /* We only handle early Z in the < direction because otherwise
 202                  * we'd have to runtime guess which direction to set in the
 203                  * render config.
 204                  */
 205                 if ((cso->depth.func == PIPE_FUNC_LESS ||
 206                      cso->depth.func == PIPE_FUNC_LEQUAL) &&
 207                     (!cso->stencil[0].enabled ||
 208                      (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
 209                       (!cso->stencil[1].enabled ||
 210                        cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP)))) {
 211                         so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z;
 212                 }
 213         } else {
 214                 so->config_bits[1] |= (PIPE_FUNC_ALWAYS <<
 215                                        VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT);
 216         }
 217
 218         if (cso->stencil[0].enabled) {
 219                 const struct pipe_stencil_state *front = &cso->stencil[0];
 220                 const struct pipe_stencil_state *back = &cso->stencil[1];
 221
 222                 uint8_t front_writemask_bits =
 223                         tlb_stencil_setup_writemask(front->writemask);
 224                 uint8_t back_writemask = front->writemask;
 225                 uint8_t back_writemask_bits = front_writemask_bits;
 226
 227                 so->stencil_uniforms[0] =
 228                         tlb_stencil_setup_bits(front, front_writemask_bits);
 229                 if (back->enabled) {
 230                         back_writemask = back->writemask;
 231                         back_writemask_bits =
 232                                 tlb_stencil_setup_writemask(back->writemask);
 233
 234                         so->stencil_uniforms[0] |= (1 << 30);
 235                         so->stencil_uniforms[1] =
 236                                 tlb_stencil_setup_bits(back, back_writemask_bits);
 237                         so->stencil_uniforms[1] |= (2 << 30);
 238                 } else {
 239                         so->stencil_uniforms[0] |= (3 << 30);
 240                 }
 241
 242                 if (front_writemask_bits == 0xff ||
 243                     back_writemask_bits == 0xff) {
 244                         so->stencil_uniforms[2] = (front->writemask |
 245                                                    (back_writemask << 8));
 246                 }
 247         }
 248
 249         return so;
 250 }
 251
 252 static void
 253 vc4_set_polygon_stipple(struct pipe_context *pctx,
 254                         const struct pipe_poly_stipple *stipple)
 255 {
 256         struct vc4_context *vc4 = vc4_context(pctx);
 257         vc4->stipple = *stipple;
 258         vc4->dirty |= VC4_DIRTY_STIPPLE;
 259 }
 260
 261 static void
 262 vc4_set_scissor_states(struct pipe_context *pctx,
 263                        unsigned start_slot,
 264                        unsigned num_scissors,
 265                        const struct pipe_scissor_state *scissor)
 266 {
 267         struct vc4_context *vc4 = vc4_context(pctx);
 268
 269         vc4->scissor = *scissor;
 270         vc4->dirty |= VC4_DIRTY_SCISSOR;
 271 }
 272
 273 static void
 274 vc4_set_viewport_states(struct pipe_context *pctx,
 275                         unsigned start_slot,
 276                         unsigned num_viewports,
 277                         const struct pipe_viewport_state *viewport)
 278 {
 279         struct vc4_context *vc4 = vc4_context(pctx);
 280         vc4->viewport = *viewport;
 281         vc4->dirty |= VC4_DIRTY_VIEWPORT;
 282 }
 283
 284 static void
 285 vc4_set_vertex_buffers(struct pipe_context *pctx,
 286                        unsigned start_slot, unsigned count,
 287                        const struct pipe_vertex_buffer *vb)
 288 {
 289         struct vc4_context *vc4 = vc4_context(pctx);
 290         struct vc4_vertexbuf_stateobj *so = &vc4->vertexbuf;
 291
 292         util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
 293                                      start_slot, count);
 294         so->count = util_last_bit(so->enabled_mask);
 295
 296         vc4->dirty |= VC4_DIRTY_VTXBUF;
 297 }
 298
 299 static void
 300 vc4_set_index_buffer(struct pipe_context *pctx,
 301                      const struct pipe_index_buffer *ib)
 302 {
 303         struct vc4_context *vc4 = vc4_context(pctx);
 304
 305         if (ib) {
 306                 assert(!ib->user_buffer);
 307                 pipe_resource_reference(&vc4->indexbuf.buffer, ib->buffer);
 308                 vc4->indexbuf.index_size = ib->index_size;
 309                 vc4->indexbuf.offset = ib->offset;
 310         } else {
 311                 pipe_resource_reference(&vc4->indexbuf.buffer, NULL);
 312         }
 313
 314         vc4->dirty |= VC4_DIRTY_INDEXBUF;
 315 }
 316
 317 static void
 318 vc4_blend_state_bind(struct pipe_context *pctx, void *hwcso)
 319 {
 320         struct vc4_context *vc4 = vc4_context(pctx);
 321         vc4->blend = hwcso;
 322         vc4->dirty |= VC4_DIRTY_BLEND;
 323 }
 324
 325 static void
 326 vc4_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
 327 {
 328         struct vc4_context *vc4 = vc4_context(pctx);
 329         struct vc4_rasterizer_state *rast = hwcso;
 330
 331         if (vc4->rasterizer && rast &&
 332             vc4->rasterizer->base.flatshade != rast->base.flatshade) {
 333                 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
 334         }
 335
 336         vc4->rasterizer = hwcso;
 337         vc4->dirty |= VC4_DIRTY_RASTERIZER;
 338 }
 339
 340 static void
 341 vc4_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
 342 {
 343         struct vc4_context *vc4 = vc4_context(pctx);
 344         vc4->zsa = hwcso;
 345         vc4->dirty |= VC4_DIRTY_ZSA;
 346 }
 347
 348 static void *
 349 vc4_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
 350                         const struct pipe_vertex_element *elements)
 351 {
 352         struct vc4_vertex_stateobj *so = CALLOC_STRUCT(vc4_vertex_stateobj);
 353
 354         if (!so)
 355                 return NULL;
 356
 357         memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
 358         so->num_elements = num_elements;
 359
 360         return so;
 361 }
 362
 363 static void
 364 vc4_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
 365 {
 366         struct vc4_context *vc4 = vc4_context(pctx);
 367         vc4->vtx = hwcso;
 368         vc4->dirty |= VC4_DIRTY_VTXSTATE;
 369 }
 370
 371 static void
 372 vc4_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
 373                         struct pipe_constant_buffer *cb)
 374 {
 375         struct vc4_context *vc4 = vc4_context(pctx);
 376         struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader];
 377
 378         assert(index == 0);
 379
 380         /* Note that the state tracker can unbind constant buffers by
 381          * passing NULL here.
 382          */
 383         if (unlikely(!cb)) {
 384                 so->enabled_mask &= ~(1 << index);
 385                 so->dirty_mask &= ~(1 << index);
 386                 return;
 387         }
 388
 389         assert(!cb->buffer);
 390         so->cb[index].buffer_offset = cb->buffer_offset;
 391         so->cb[index].buffer_size   = cb->buffer_size;
 392         so->cb[index].user_buffer   = cb->user_buffer;
 393
 394         so->enabled_mask |= 1 << index;
 395         so->dirty_mask |= 1 << index;
 396         vc4->dirty |= VC4_DIRTY_CONSTBUF;
 397 }
 398
 399 static void
 400 vc4_set_framebuffer_state(struct pipe_context *pctx,
 401                           const struct pipe_framebuffer_state *framebuffer)
 402 {
 403         struct vc4_context *vc4 = vc4_context(pctx);
 404         struct pipe_framebuffer_state *cso = &vc4->framebuffer;
 405         unsigned i;
 406
 407         vc4_flush(pctx);
 408
 409         for (i = 0; i < framebuffer->nr_cbufs; i++)
 410                 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
 411         for (; i < vc4->framebuffer.nr_cbufs; i++)
 412                 pipe_surface_reference(&cso->cbufs[i], NULL);
 413
 414         cso->nr_cbufs = framebuffer->nr_cbufs;
 415
 416         pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
 417
 418         cso->width = framebuffer->width;
 419         cso->height = framebuffer->height;
 420
 421         /* Nonzero texture mipmap levels are laid out as if they were in
 422          * power-of-two-sized spaces.  The renderbuffer config infers its
 423          * stride from the width parameter, so we need to configure our
 424          * framebuffer.  Note that if the z/color buffers were mismatched
 425          * sizes, we wouldn't be able to do this.
 426          */
 427         if (cso->cbufs[0] && cso->cbufs[0]->u.tex.level) {
 428                 struct vc4_resource *rsc =
 429                         vc4_resource(cso->cbufs[0]->texture);
 430                 cso->width =
 431                         (rsc->slices[cso->cbufs[0]->u.tex.level].stride /
 432                          rsc->cpp);
 433         } else if (cso->zsbuf && cso->zsbuf->u.tex.level){
 434                 struct vc4_resource *rsc =
 435                         vc4_resource(cso->zsbuf->texture);
 436                 cso->width =
 437                         (rsc->slices[cso->zsbuf->u.tex.level].stride /
 438                          rsc->cpp);
 439         }
 440
 441         vc4->dirty |= VC4_DIRTY_FRAMEBUFFER;
 442 }
 443
 444 static struct vc4_texture_stateobj *
 445 vc4_get_stage_tex(struct vc4_context *vc4, unsigned shader)
 446 {
 447         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 448
 449         switch (shader) {
 450         case PIPE_SHADER_FRAGMENT:
 451                 vc4->dirty |= VC4_DIRTY_FRAGTEX;
 452                 return &vc4->fragtex;
 453                 break;
 454         case PIPE_SHADER_VERTEX:
 455                 vc4->dirty |= VC4_DIRTY_VERTTEX;
 456                 return &vc4->verttex;
 457                 break;
 458         default:
 459                 fprintf(stderr, "Unknown shader target %d\n", shader);
 460                 abort();
 461         }
 462 }
 463
 464 static void *
 465 vc4_create_sampler_state(struct pipe_context *pctx,
 466                          const struct pipe_sampler_state *cso)
 467 {
 468         return vc4_generic_cso_state_create(cso, sizeof(*cso));
 469 }
 470
 471 static void
 472 vc4_sampler_states_bind(struct pipe_context *pctx,
 473                         unsigned shader, unsigned start,
 474                         unsigned nr, void **hwcso)
 475 {
 476         struct vc4_context *vc4 = vc4_context(pctx);
 477         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 478
 479         assert(start == 0);
 480         unsigned i;
 481         unsigned new_nr = 0;
 482
 483         for (i = 0; i < nr; i++) {
 484                 if (hwcso[i])
 485                         new_nr = i + 1;
 486                 stage_tex->samplers[i] = hwcso[i];
 487                 stage_tex->dirty_samplers |= (1 << i);
 488         }
 489
 490         for (; i < stage_tex->num_samplers; i++) {
 491                 stage_tex->samplers[i] = NULL;
 492                 stage_tex->dirty_samplers |= (1 << i);
 493         }
 494
 495         stage_tex->num_samplers = new_nr;
 496 }
 497
 498 static struct pipe_sampler_view *
 499 vc4_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
 500                         const struct pipe_sampler_view *cso)
 501 {
 502         struct pipe_sampler_view *so = malloc(sizeof(*so));
 503         struct vc4_resource *rsc = vc4_resource(prsc);
 504
 505         if (!so)
 506                 return NULL;
 507
 508         *so = *cso;
 509
 510         pipe_reference(NULL, &prsc->reference);
 511
 512         /* There is no hardware level clamping, and the start address of a
 513          * texture may be misaligned, so in that case we have to copy to a
 514          * temporary.
 515          *
 516          * Also, Raspberry Pi doesn't support sampling from raster textures,
 517          * so we also have to copy to a temporary then.
 518          */
 519         if (so->u.tex.first_level ||
 520             rsc->vc4_format == VC4_TEXTURE_TYPE_RGBA32R) {
 521                 struct vc4_resource *shadow_parent = vc4_resource(prsc);
 522                 struct pipe_resource tmpl = shadow_parent->base.b;
 523                 struct vc4_resource *clone;
 524
 525                 tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET;
 526                 tmpl.width0 = u_minify(tmpl.width0, so->u.tex.first_level);
 527                 tmpl.height0 = u_minify(tmpl.height0, so->u.tex.first_level);
 528                 tmpl.last_level = so->u.tex.last_level - so->u.tex.first_level;
 529
 530                 prsc = vc4_resource_create(pctx->screen, &tmpl);
 531                 clone = vc4_resource(prsc);
 532                 clone->shadow_parent = &shadow_parent->base.b;
 533                 /* Flag it as needing update of the contents from the parent. */
 534                 clone->writes = shadow_parent->writes - 1;
 535
 536                 assert(clone->vc4_format != VC4_TEXTURE_TYPE_RGBA32R);
 537         }
 538         so->texture = prsc;
 539         so->reference.count = 1;
 540         so->context = pctx;
 541
 542         return so;
 543 }
 544
 545 static void
 546 vc4_sampler_view_destroy(struct pipe_context *pctx,
 547                          struct pipe_sampler_view *view)
 548 {
 549         pipe_resource_reference(&view->texture, NULL);
 550         free(view);
 551 }
 552
 553 static void
 554 vc4_set_sampler_views(struct pipe_context *pctx, unsigned shader,
 555                       unsigned start, unsigned nr,
 556                       struct pipe_sampler_view **views)
 557 {
 558         struct vc4_context *vc4 = vc4_context(pctx);
 559         struct vc4_texture_stateobj *stage_tex = vc4_get_stage_tex(vc4, shader);
 560         unsigned i;
 561         unsigned new_nr = 0;
 562
 563         assert(start == 0);
 564
 565         vc4->dirty |= VC4_DIRTY_TEXSTATE;
 566
 567         for (i = 0; i < nr; i++) {
 568                 if (views[i])
 569                         new_nr = i + 1;
 570                 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
 571                 stage_tex->dirty_samplers |= (1 << i);
 572         }
 573
 574         for (; i < stage_tex->num_textures; i++) {
 575                 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
 576                 stage_tex->dirty_samplers |= (1 << i);
 577         }
 578
 579         stage_tex->num_textures = new_nr;
 580 }
 581
 582 void
 583 vc4_state_init(struct pipe_context *pctx)
 584 {
 585         pctx->set_blend_color = vc4_set_blend_color;
 586         pctx->set_stencil_ref = vc4_set_stencil_ref;
 587         pctx->set_clip_state = vc4_set_clip_state;
 588         pctx->set_sample_mask = vc4_set_sample_mask;
 589         pctx->set_constant_buffer = vc4_set_constant_buffer;
 590         pctx->set_framebuffer_state = vc4_set_framebuffer_state;
 591         pctx->set_polygon_stipple = vc4_set_polygon_stipple;
 592         pctx->set_scissor_states = vc4_set_scissor_states;
 593         pctx->set_viewport_states = vc4_set_viewport_states;
 594
 595         pctx->set_vertex_buffers = vc4_set_vertex_buffers;
 596         pctx->set_index_buffer = vc4_set_index_buffer;
 597
 598         pctx->create_blend_state = vc4_create_blend_state;
 599         pctx->bind_blend_state = vc4_blend_state_bind;
 600         pctx->delete_blend_state = vc4_generic_cso_state_delete;
 601
 602         pctx->create_rasterizer_state = vc4_create_rasterizer_state;
 603         pctx->bind_rasterizer_state = vc4_rasterizer_state_bind;
 604         pctx->delete_rasterizer_state = vc4_generic_cso_state_delete;
 605
 606         pctx->create_depth_stencil_alpha_state = vc4_create_depth_stencil_alpha_state;
 607         pctx->bind_depth_stencil_alpha_state = vc4_zsa_state_bind;
 608         pctx->delete_depth_stencil_alpha_state = vc4_generic_cso_state_delete;
 609
 610         pctx->create_vertex_elements_state = vc4_vertex_state_create;
 611         pctx->delete_vertex_elements_state = vc4_generic_cso_state_delete;
 612         pctx->bind_vertex_elements_state = vc4_vertex_state_bind;
 613
 614         pctx->create_sampler_state = vc4_create_sampler_state;
 615         pctx->delete_sampler_state = vc4_generic_cso_state_delete;
 616         pctx->bind_sampler_states = vc4_sampler_states_bind;
 617
 618         pctx->create_sampler_view = vc4_create_sampler_view;
 619         pctx->sampler_view_destroy = vc4_sampler_view_destroy;
 620         pctx->set_sampler_views = vc4_set_sampler_views;
 621 }