vc4: Fix vc4_nir_lower_io for non-vec4 I/O.
[mesa.git] / src / gallium / drivers / vc4 / vc4_tiling.c
1 /*
2 * Copyright © 2014 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file vc4_tiling.c
25 *
26 * Handles information about the VC4 tiling formats, and loading and storing
27 * from them.
28 *
29 * Texture mipmap levels on VC4 are (with the exception of 32-bit RGBA raster
30 * textures for scanout) stored as groups of microtiles. If the texture is at
31 * least 4x4 microtiles (utiles), then those microtiles are arranged in a sort
32 * of Hilbert-fractal-ish layout (T), otherwise the microtiles are in raster
33 * order (LT).
34 *
35 * Specifically, the T format has:
36 *
37 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
38 * pixels at 32 bit depth.
39 *
40 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
41 * 16x16 pixels).
42 *
43 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
44 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
45 * they're (TR, BR, BL, TL), where bottom left is start of memory.
46 *
47 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
48 * tiles) or right-to-left (odd rows of 4k tiles).
49 */
50
51 #include "vc4_screen.h"
52 #include "vc4_context.h"
53 #include "vc4_tiling.h"
54
55 /** Return the width in pixels of a 64-byte microtile. */
56 uint32_t
57 vc4_utile_width(int cpp)
58 {
59 switch (cpp) {
60 case 1:
61 case 2:
62 return 8;
63 case 4:
64 return 4;
65 case 8:
66 return 2;
67 default:
68 fprintf(stderr, "unknown cpp: %d\n", cpp);
69 abort();
70 }
71 }
72
73 /** Return the height in pixels of a 64-byte microtile. */
74 uint32_t
75 vc4_utile_height(int cpp)
76 {
77 switch (cpp) {
78 case 1:
79 return 8;
80 case 2:
81 case 4:
82 case 8:
83 return 4;
84 default:
85 fprintf(stderr, "unknown cpp: %d\n", cpp);
86 abort();
87 }
88 }
89
90 /**
91 * The texture unit decides what tiling format a particular miplevel is using
92 * this function, so we lay out our miptrees accordingly.
93 */
94 bool
95 vc4_size_is_lt(uint32_t width, uint32_t height, int cpp)
96 {
97 return (width <= 4 * vc4_utile_width(cpp) ||
98 height <= 4 * vc4_utile_height(cpp));
99 }
100
101 void
102 vc4_load_utile(void *dst, void *src, uint32_t dst_stride, uint32_t cpp)
103 {
104 uint32_t utile_h = vc4_utile_height(cpp);
105 uint32_t row_size = 64 / utile_h;
106
107 for (int y = 0; y < utile_h; y++) {
108 memcpy(dst, src, row_size);
109 dst += dst_stride;
110 src += row_size;
111 }
112 }
113
114 void
115 vc4_store_utile(void *dst, void *src, uint32_t src_stride, uint32_t cpp)
116 {
117 uint32_t utile_h = vc4_utile_height(cpp);
118 uint32_t row_size = 64 / utile_h;
119
120 for (int y = 0; y < utile_h; y++) {
121 memcpy(dst, src, row_size);
122 dst += row_size;
123 src += src_stride;
124 }
125 }
126
127 static void
128 check_box_utile_alignment(const struct pipe_box *box, int cpp)
129 {
130 assert(!(box->x & (vc4_utile_width(cpp) - 1)));
131 assert(!(box->y & (vc4_utile_height(cpp) - 1)));
132 assert(!(box->width & (vc4_utile_width(cpp) - 1)));
133 assert(!(box->height & (vc4_utile_height(cpp) - 1)));
134 }
135
136 static void
137 vc4_load_lt_image(void *dst, uint32_t dst_stride,
138 void *src, uint32_t src_stride,
139 int cpp, const struct pipe_box *box)
140 {
141 uint32_t utile_w = vc4_utile_width(cpp);
142 uint32_t utile_h = vc4_utile_height(cpp);
143 uint32_t xstart = box->x;
144 uint32_t ystart = box->y;
145
146 for (uint32_t y = 0; y < box->height; y += utile_h) {
147 for (int x = 0; x < box->width; x += utile_w) {
148 vc4_load_utile(dst + (dst_stride * y +
149 x * cpp),
150 src + ((ystart + y) * src_stride +
151 (xstart + x) * 64 / utile_w),
152 dst_stride, cpp);
153 }
154 }
155 }
156
157 static void
158 vc4_store_lt_image(void *dst, uint32_t dst_stride,
159 void *src, uint32_t src_stride,
160 int cpp, const struct pipe_box *box)
161 {
162 uint32_t utile_w = vc4_utile_width(cpp);
163 uint32_t utile_h = vc4_utile_height(cpp);
164 uint32_t xstart = box->x;
165 uint32_t ystart = box->y;
166
167 for (uint32_t y = 0; y < box->height; y += utile_h) {
168 for (int x = 0; x < box->width; x += utile_w) {
169 vc4_store_utile(dst + ((ystart + y) * dst_stride +
170 (xstart + x) * 64 / utile_w),
171 src + (src_stride * y +
172 x * cpp),
173 src_stride, cpp);
174 }
175 }
176 }
177
178 /**
179 * Takes a utile x and y (and the number of utiles of width of the image) and
180 * returns the offset to the utile within a VC4_TILING_FORMAT_TF image.
181 */
182 static uint32_t
183 t_utile_address(uint32_t utile_x, uint32_t utile_y,
184 uint32_t utile_stride)
185 {
186 /* T images have to be aligned to 8 utiles (4x4 subtiles, which are
187 * 2x2 in a 4k tile).
188 */
189 assert(!(utile_stride & 7));
190 uint32_t tile_stride = utile_stride >> 3;
191 /* 4k tile offsets. */
192 uint32_t tile_x = utile_x >> 3;
193 uint32_t tile_y = utile_y >> 3;
194 bool odd_tile_y = tile_y & 1;
195
196 /* Odd lines of 4k tiles go right-to-left. */
197 if (odd_tile_y)
198 tile_x = tile_stride - tile_x - 1;
199
200 uint32_t tile_offset = 4096 * (tile_y * tile_stride + tile_x);
201
202 uint32_t stile_x = (utile_x >> 2) & 1;
203 uint32_t stile_y = (utile_y >> 2) & 1;
204 uint32_t stile_index = (stile_y << 1) + stile_x;
205 static const uint32_t odd_stile_map[4] = {2, 1, 3, 0};
206 static const uint32_t even_stile_map[4] = {0, 3, 1, 2};
207
208 uint32_t stile_offset = 1024 * (odd_tile_y ?
209 odd_stile_map[stile_index] :
210 even_stile_map[stile_index]);
211
212 uint32_t utile_offset = 64 * ((utile_y & 3) * 4 + (utile_x & 3));
213
214 #if 0
215 fprintf(stderr, "utile %d,%d -> %d + %d + %d (stride %d,%d) = %d\n",
216 utile_x, utile_y,
217 tile_offset, stile_offset, utile_offset,
218 utile_stride, tile_stride,
219 tile_offset + stile_offset + utile_offset);
220 #endif
221
222 return tile_offset + stile_offset + utile_offset;
223 }
224
225 static void
226 vc4_load_t_image(void *dst, uint32_t dst_stride,
227 void *src, uint32_t src_stride,
228 int cpp, const struct pipe_box *box)
229 {
230 uint32_t utile_w = vc4_utile_width(cpp);
231 uint32_t utile_h = vc4_utile_height(cpp);
232 uint32_t utile_stride = src_stride / cpp / utile_w;
233 uint32_t xstart = box->x / utile_w;
234 uint32_t ystart = box->y / utile_h;
235
236 for (uint32_t y = 0; y < box->height / utile_h; y++) {
237 for (int x = 0; x < box->width / utile_w; x++) {
238 vc4_load_utile(dst + (y * utile_h * dst_stride +
239 x * utile_w * cpp),
240 src + t_utile_address(xstart + x,
241 ystart + y,
242 utile_stride),
243 dst_stride, cpp);
244 }
245 }
246 }
247
248 static void
249 vc4_store_t_image(void *dst, uint32_t dst_stride,
250 void *src, uint32_t src_stride,
251 int cpp, const struct pipe_box *box)
252 {
253 uint32_t utile_w = vc4_utile_width(cpp);
254 uint32_t utile_h = vc4_utile_height(cpp);
255 uint32_t utile_stride = dst_stride / cpp / utile_w;
256 uint32_t xstart = box->x / utile_w;
257 uint32_t ystart = box->y / utile_h;
258
259 for (uint32_t y = 0; y < box->height / utile_h; y++) {
260 for (int x = 0; x < box->width / utile_w; x++) {
261 vc4_store_utile(dst + t_utile_address(xstart + x,
262 ystart + y,
263 utile_stride),
264 src + (y * utile_h * src_stride +
265 x * utile_w * cpp),
266 src_stride, cpp);
267 }
268 }
269 }
270
271 /**
272 * Loads pixel data from the start (microtile-aligned) box in \p src to the
273 * start of \p dst according to the given tiling format.
274 */
275 void
276 vc4_load_tiled_image(void *dst, uint32_t dst_stride,
277 void *src, uint32_t src_stride,
278 uint8_t tiling_format, int cpp,
279 const struct pipe_box *box)
280 {
281 check_box_utile_alignment(box, cpp);
282
283 if (tiling_format == VC4_TILING_FORMAT_LT) {
284 vc4_load_lt_image(dst, dst_stride,
285 src, src_stride,
286 cpp, box);
287 } else {
288 assert(tiling_format == VC4_TILING_FORMAT_T);
289 vc4_load_t_image(dst, dst_stride,
290 src, src_stride,
291 cpp, box);
292 }
293 }
294
295 /**
296 * Stores pixel data from the start of \p src into a (microtile-aligned) box in
297 * \p dst according to the given tiling format.
298 */
299 void
300 vc4_store_tiled_image(void *dst, uint32_t dst_stride,
301 void *src, uint32_t src_stride,
302 uint8_t tiling_format, int cpp,
303 const struct pipe_box *box)
304 {
305 check_box_utile_alignment(box, cpp);
306
307 if (tiling_format == VC4_TILING_FORMAT_LT) {
308 vc4_store_lt_image(dst, dst_stride,
309 src, src_stride,
310 cpp, box);
311 } else {
312 assert(tiling_format == VC4_TILING_FORMAT_T);
313 vc4_store_t_image(dst, dst_stride,
314 src, src_stride,
315 cpp, box);
316 }
317 }
318