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24 /** @file vc4_tiling_lt.c
26 * Helper functions from vc4_tiling.c that will be compiled for using NEON
29 * If VC4_BUILD_NEON is set, then the functions will be suffixed with _neon.
30 * They will only use NEON assembly if __ARM_ARCH is also set, to keep the x86
35 #include "pipe/p_state.h"
36 #include "vc4_tiling.h"
39 #define NEON_TAG(x) x ## _neon
41 #define NEON_TAG(x) x ## _base
44 /** Returns the stride in bytes of a 64-byte microtile. */
46 vc4_utile_stride(int cpp
)
56 unreachable("bad cpp");
61 vc4_load_utile(void *cpu
, void *gpu
, uint32_t cpu_stride
, uint32_t cpp
)
63 uint32_t gpu_stride
= vc4_utile_stride(cpp
);
64 #if defined(VC4_BUILD_NEON) && defined(PIPE_ARCH_ARM)
65 if (gpu_stride
== 8) {
67 /* Load from the GPU in one shot, no interleave, to
70 "vldm %0, {q0, q1, q2, q3}\n"
71 /* Store each 8-byte line to cpu-side destination,
72 * incrementing it by the stride each time.
74 "vst1.8 d0, [%1], %2\n"
75 "vst1.8 d1, [%1], %2\n"
76 "vst1.8 d2, [%1], %2\n"
77 "vst1.8 d3, [%1], %2\n"
78 "vst1.8 d4, [%1], %2\n"
79 "vst1.8 d5, [%1], %2\n"
80 "vst1.8 d6, [%1], %2\n"
83 : "r"(gpu
), "r"(cpu
), "r"(cpu_stride
)
84 : "q0", "q1", "q2", "q3");
86 assert(gpu_stride
== 16);
88 /* Load from the GPU in one shot, no interleave, to
91 "vldm %0, {q0, q1, q2, q3};\n"
92 /* Store each 16-byte line in 2 parts to the cpu-side
93 * destination. (vld1 can only store one d-register
96 "vst1.8 d0, [%1], %3\n"
97 "vst1.8 d1, [%2], %3\n"
98 "vst1.8 d2, [%1], %3\n"
99 "vst1.8 d3, [%2], %3\n"
100 "vst1.8 d4, [%1], %3\n"
101 "vst1.8 d5, [%2], %3\n"
105 : "r"(gpu
), "r"(cpu
), "r"(cpu
+ 8), "r"(cpu_stride
)
106 : "q0", "q1", "q2", "q3");
109 for (uint32_t gpu_offset
= 0; gpu_offset
< 64; gpu_offset
+= gpu_stride
) {
110 memcpy(cpu
, gpu
+ gpu_offset
, gpu_stride
);
117 vc4_store_utile(void *gpu
, void *cpu
, uint32_t cpu_stride
, uint32_t cpp
)
119 uint32_t gpu_stride
= vc4_utile_stride(cpp
);
121 #if defined(VC4_BUILD_NEON) && defined(PIPE_ARCH_ARM)
122 if (gpu_stride
== 8) {
124 /* Load each 8-byte line from cpu-side source,
125 * incrementing it by the stride each time.
127 "vld1.8 d0, [%1], %2\n"
128 "vld1.8 d1, [%1], %2\n"
129 "vld1.8 d2, [%1], %2\n"
130 "vld1.8 d3, [%1], %2\n"
131 "vld1.8 d4, [%1], %2\n"
132 "vld1.8 d5, [%1], %2\n"
133 "vld1.8 d6, [%1], %2\n"
135 /* Load from the GPU in one shot, no interleave, to
138 "vstm %0, {q0, q1, q2, q3}\n"
140 : "r"(gpu
), "r"(cpu
), "r"(cpu_stride
)
141 : "q0", "q1", "q2", "q3");
143 assert(gpu_stride
== 16);
145 /* Load each 16-byte line in 2 parts from the cpu-side
146 * destination. (vld1 can only store one d-register
149 "vld1.8 d0, [%1], %3\n"
150 "vld1.8 d1, [%2], %3\n"
151 "vld1.8 d2, [%1], %3\n"
152 "vld1.8 d3, [%2], %3\n"
153 "vld1.8 d4, [%1], %3\n"
154 "vld1.8 d5, [%2], %3\n"
157 /* Store to the GPU in one shot, no interleave. */
158 "vstm %0, {q0, q1, q2, q3}\n"
160 : "r"(gpu
), "r"(cpu
), "r"(cpu
+ 8), "r"(cpu_stride
)
161 : "q0", "q1", "q2", "q3");
164 for (uint32_t gpu_offset
= 0; gpu_offset
< 64; gpu_offset
+= gpu_stride
) {
165 memcpy(gpu
+ gpu_offset
, cpu
, gpu_stride
);
173 NEON_TAG(vc4_load_lt_image
)(void *dst
, uint32_t dst_stride
,
174 void *src
, uint32_t src_stride
,
175 int cpp
, const struct pipe_box
*box
)
177 uint32_t utile_w
= vc4_utile_width(cpp
);
178 uint32_t utile_h
= vc4_utile_height(cpp
);
179 uint32_t xstart
= box
->x
;
180 uint32_t ystart
= box
->y
;
182 for (uint32_t y
= 0; y
< box
->height
; y
+= utile_h
) {
183 for (int x
= 0; x
< box
->width
; x
+= utile_w
) {
184 vc4_load_utile(dst
+ (dst_stride
* y
+
186 src
+ ((ystart
+ y
) * src_stride
+
187 (xstart
+ x
) * 64 / utile_w
),
194 NEON_TAG(vc4_store_lt_image
)(void *dst
, uint32_t dst_stride
,
195 void *src
, uint32_t src_stride
,
196 int cpp
, const struct pipe_box
*box
)
198 uint32_t utile_w
= vc4_utile_width(cpp
);
199 uint32_t utile_h
= vc4_utile_height(cpp
);
200 uint32_t xstart
= box
->x
;
201 uint32_t ystart
= box
->y
;
203 for (uint32_t y
= 0; y
< box
->height
; y
+= utile_h
) {
204 for (int x
= 0; x
< box
->width
; x
+= utile_w
) {
205 vc4_store_utile(dst
+ ((ystart
+ y
) * dst_stride
+
206 (xstart
+ x
) * 64 / utile_w
),
207 src
+ (src_stride
* y
+