src/gallium/drivers/vc5/vc5_context.h

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC5_CONTEXT_H
  26 #define VC5_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/bitset.h"
  33 #include "util/slab.h"
  34 #include "xf86drm.h"
  35 #include "vc5_drm.h"
  36 #include "vc5_screen.h"
  37
  38 struct vc5_job;
  39 struct vc5_bo;
  40 void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo);
  41
  42 #define __user
  43 #include "vc5_drm.h"
  44 #include "vc5_bufmgr.h"
  45 #include "vc5_resource.h"
  46 #include "vc5_cl.h"
  47
  48 #ifdef USE_VC5_SIMULATOR
  49 #define using_vc5_simulator true
  50 #else
  51 #define using_vc5_simulator false
  52 #endif
  53
  54 #define VC5_DIRTY_BLEND         (1 <<  0)
  55 #define VC5_DIRTY_RASTERIZER    (1 <<  1)
  56 #define VC5_DIRTY_ZSA           (1 <<  2)
  57 #define VC5_DIRTY_FRAGTEX       (1 <<  3)
  58 #define VC5_DIRTY_VERTTEX       (1 <<  4)
  59
  60 #define VC5_DIRTY_BLEND_COLOR   (1 <<  7)
  61 #define VC5_DIRTY_STENCIL_REF   (1 <<  8)
  62 #define VC5_DIRTY_SAMPLE_MASK   (1 <<  9)
  63 #define VC5_DIRTY_FRAMEBUFFER   (1 << 10)
  64 #define VC5_DIRTY_STIPPLE       (1 << 11)
  65 #define VC5_DIRTY_VIEWPORT      (1 << 12)
  66 #define VC5_DIRTY_CONSTBUF      (1 << 13)
  67 #define VC5_DIRTY_VTXSTATE      (1 << 14)
  68 #define VC5_DIRTY_VTXBUF        (1 << 15)
  69 #define VC5_DIRTY_SCISSOR       (1 << 17)
  70 #define VC5_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  71 #define VC5_DIRTY_PRIM_MODE     (1 << 19)
  72 #define VC5_DIRTY_CLIP          (1 << 20)
  73 #define VC5_DIRTY_UNCOMPILED_VS (1 << 21)
  74 #define VC5_DIRTY_UNCOMPILED_FS (1 << 22)
  75 #define VC5_DIRTY_COMPILED_CS   (1 << 23)
  76 #define VC5_DIRTY_COMPILED_VS   (1 << 24)
  77 #define VC5_DIRTY_COMPILED_FS   (1 << 25)
  78 #define VC5_DIRTY_FS_INPUTS     (1 << 26)
  79 #define VC5_DIRTY_STREAMOUT     (1 << 27)
  80 #define VC5_DIRTY_OQ            (1 << 28)
  81
  82 #define VC5_MAX_FS_INPUTS 64
  83
  84 struct vc5_sampler_view {
  85         struct pipe_sampler_view base;
  86         uint32_t p0;
  87         uint32_t p1;
  88         /* Precomputed swizzles to pass in to the shader key. */
  89         uint8_t swizzle[4];
  90
  91         uint8_t texture_shader_state[32];
  92 };
  93
  94 struct vc5_sampler_state {
  95         struct pipe_sampler_state base;
  96         uint32_t p0;
  97         uint32_t p1;
  98
  99         uint8_t texture_shader_state[32];
 100 };
 101
 102 struct vc5_texture_stateobj {
 103         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
 104         unsigned num_textures;
 105         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
 106         unsigned num_samplers;
 107         struct vc5_cl_reloc texture_state[PIPE_MAX_SAMPLERS];
 108 };
 109
 110 struct vc5_shader_uniform_info {
 111         enum quniform_contents *contents;
 112         uint32_t *data;
 113         uint32_t count;
 114 };
 115
 116 struct vc5_uncompiled_shader {
 117         /** A name for this program, so you can track it in shader-db output. */
 118         uint32_t program_id;
 119         /** How many variants of this program were compiled, for shader-db. */
 120         uint32_t compiled_variant_count;
 121         struct pipe_shader_state base;
 122         uint32_t num_tf_outputs;
 123         struct v3d_varying_slot *tf_outputs;
 124         uint16_t tf_specs[PIPE_MAX_SO_BUFFERS];
 125         uint32_t num_tf_specs;
 126 };
 127
 128 struct vc5_compiled_shader {
 129         struct vc5_bo *bo;
 130
 131         union {
 132                 struct v3d_prog_data *base;
 133                 struct v3d_vs_prog_data *vs;
 134                 struct v3d_fs_prog_data *fs;
 135         } prog_data;
 136
 137         /**
 138          * VC5_DIRTY_* flags that, when set in vc5->dirty, mean that the
 139          * uniforms have to be rewritten (and therefore the shader state
 140          * reemitted).
 141          */
 142         uint32_t uniform_dirty_bits;
 143 };
 144
 145 struct vc5_program_stateobj {
 146         struct vc5_uncompiled_shader *bind_vs, *bind_fs;
 147         struct vc5_compiled_shader *cs, *vs, *fs;
 148 };
 149
 150 struct vc5_constbuf_stateobj {
 151         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 152         uint32_t enabled_mask;
 153         uint32_t dirty_mask;
 154 };
 155
 156 struct vc5_vertexbuf_stateobj {
 157         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 158         unsigned count;
 159         uint32_t enabled_mask;
 160         uint32_t dirty_mask;
 161 };
 162
 163 struct vc5_vertex_stateobj {
 164         struct pipe_vertex_element pipe[VC5_MAX_ATTRIBUTES];
 165         unsigned num_elements;
 166
 167         uint8_t attrs[12 * VC5_MAX_ATTRIBUTES];
 168         struct vc5_bo *default_attribute_values;
 169 };
 170
 171 struct vc5_streamout_stateobj {
 172         struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
 173         unsigned num_targets;
 174 };
 175
 176 /* Hash table key for vc5->jobs */
 177 struct vc5_job_key {
 178         struct pipe_surface *cbufs[4];
 179         struct pipe_surface *zsbuf;
 180 };
 181
 182 /**
 183  * A complete bin/render job.
 184  *
 185  * This is all of the state necessary to submit a bin/render to the kernel.
 186  * We want to be able to have multiple in progress at a time, so that we don't
 187  * need to flush an existing CL just to switch to rendering to a new render
 188  * target (which would mean reading back from the old render target when
 189  * starting to render to it again).
 190  */
 191 struct vc5_job {
 192         struct vc5_context *vc5;
 193         struct vc5_cl bcl;
 194         struct vc5_cl rcl;
 195         struct vc5_cl indirect;
 196         struct vc5_bo *tile_alloc;
 197         uint32_t shader_rec_count;
 198
 199         struct drm_vc5_submit_cl submit;
 200
 201         /**
 202          * Set of all BOs referenced by the job.  This will be used for making
 203          * the list of BOs that the kernel will need to have paged in to
 204          * execute our job.
 205          */
 206         struct set *bos;
 207
 208         struct set *write_prscs;
 209
 210         /* Size of the submit.bo_handles array. */
 211         uint32_t bo_handles_size;
 212
 213         /** @{ Surfaces to submit rendering for. */
 214         struct pipe_surface *cbufs[4];
 215         struct pipe_surface *zsbuf;
 216         /** @} */
 217         /** @{
 218          * Bounding box of the scissor across all queued drawing.
 219          *
 220          * Note that the max values are exclusive.
 221          */
 222         uint32_t draw_min_x;
 223         uint32_t draw_min_y;
 224         uint32_t draw_max_x;
 225         uint32_t draw_max_y;
 226         /** @} */
 227         /** @{
 228          * Width/height of the color framebuffer being rendered to,
 229          * for VC5_TILE_RENDERING_MODE_CONFIG.
 230         */
 231         uint32_t draw_width;
 232         uint32_t draw_height;
 233         /** @} */
 234         /** @{ Tile information, depending on MSAA and float color buffer. */
 235         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 236         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 237
 238         uint32_t tile_width; /** @< Width of a tile. */
 239         uint32_t tile_height; /** @< Height of a tile. */
 240         /** maximum internal_bpp of all color render targets. */
 241         uint32_t internal_bpp;
 242
 243         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 244         bool msaa;
 245         /** @} */
 246
 247         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 248          * first rendering.
 249          */
 250         uint32_t cleared;
 251         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 252          * (either clears or draws).
 253          */
 254         uint32_t resolve;
 255         uint32_t clear_color[4][4];
 256         float clear_z;
 257         uint8_t clear_s;
 258
 259         /**
 260          * Set if some drawing (triangles, blits, or just a glClear()) has
 261          * been done to the FBO, meaning that we need to
 262          * DRM_IOCTL_VC5_SUBMIT_CL.
 263          */
 264         bool needs_flush;
 265
 266         /**
 267          * Set if there is a nonzero address for OCCLUSION_QUERY_COUNTER.  If
 268          * so, we need to disable it and flush before ending the CL, to keep
 269          * the next tile from starting with it enabled.
 270          */
 271         bool oq_enabled;
 272
 273         bool uses_early_z;
 274
 275         /**
 276          * Number of draw calls (not counting full buffer clears) queued in
 277          * the current job.
 278          */
 279         uint32_t draw_calls_queued;
 280
 281         struct vc5_job_key key;
 282 };
 283
 284 struct vc5_context {
 285         struct pipe_context base;
 286
 287         int fd;
 288         struct vc5_screen *screen;
 289
 290         /** The 3D rendering job for the currently bound FBO. */
 291         struct vc5_job *job;
 292
 293         /* Map from struct vc5_job_key to the job for that FBO.
 294          */
 295         struct hash_table *jobs;
 296
 297         /**
 298          * Map from vc5_resource to a job writing to that resource.
 299          *
 300          * Primarily for flushing jobs rendering to textures that are now
 301          * being read from.
 302          */
 303         struct hash_table *write_jobs;
 304
 305         struct slab_child_pool transfer_pool;
 306         struct blitter_context *blitter;
 307
 308         /** bitfield of VC5_DIRTY_* */
 309         uint32_t dirty;
 310
 311         struct primconvert_context *primconvert;
 312
 313         struct hash_table *fs_cache, *vs_cache;
 314         uint32_t next_uncompiled_program_id;
 315         uint64_t next_compiled_program_id;
 316
 317         struct vc5_compiler_state *compiler_state;
 318
 319         uint8_t prim_mode;
 320
 321         /** Maximum index buffer valid for the current shader_rec. */
 322         uint32_t max_index;
 323
 324         /** Seqno of the last CL flush's job. */
 325         uint64_t last_emit_seqno;
 326
 327         struct u_upload_mgr *uploader;
 328
 329         /** @{ Current pipeline state objects */
 330         struct pipe_scissor_state scissor;
 331         struct pipe_blend_state *blend;
 332         struct vc5_rasterizer_state *rasterizer;
 333         struct vc5_depth_stencil_alpha_state *zsa;
 334
 335         struct vc5_texture_stateobj verttex, fragtex;
 336
 337         struct vc5_program_stateobj prog;
 338
 339         struct vc5_vertex_stateobj *vtx;
 340
 341         struct {
 342                 struct pipe_blend_color f;
 343                 uint16_t hf[4];
 344         } blend_color;
 345         struct pipe_stencil_ref stencil_ref;
 346         unsigned sample_mask;
 347         struct pipe_framebuffer_state framebuffer;
 348
 349         /* Per render target, whether we should swap the R and B fields in the
 350          * shader's color output and in blending.  If render targets disagree
 351          * on the R/B swap and use the constant color, then we would need to
 352          * fall back to in-shader blending.
 353          */
 354         uint8_t swap_color_rb;
 355
 356         /* Per render target, whether we should treat the dst alpha values as
 357          * one in blending.
 358          *
 359          * For RGBX formats, the tile buffer's alpha channel will be
 360          * undefined.
 361          */
 362         uint8_t blend_dst_alpha_one;
 363
 364         bool active_queries;
 365
 366         uint32_t tf_prims_generated;
 367         uint32_t prims_generated;
 368
 369         struct pipe_poly_stipple stipple;
 370         struct pipe_clip_state clip;
 371         struct pipe_viewport_state viewport;
 372         struct vc5_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 373         struct vc5_vertexbuf_stateobj vertexbuf;
 374         struct vc5_streamout_stateobj streamout;
 375         struct vc5_bo *current_oq;
 376         /** @} */
 377 };
 378
 379 struct vc5_rasterizer_state {
 380         struct pipe_rasterizer_state base;
 381
 382         /* VC5_CONFIGURATION_BITS */
 383         uint8_t config_bits[3];
 384
 385         float point_size;
 386
 387         /**
 388          * Half-float (1/8/7 bits) value of polygon offset units for
 389          * VC5_PACKET_DEPTH_OFFSET
 390          */
 391         uint16_t offset_units;
 392         /**
 393          * Half-float (1/8/7 bits) value of polygon offset scale for
 394          * VC5_PACKET_DEPTH_OFFSET
 395          */
 396         uint16_t offset_factor;
 397 };
 398
 399 struct vc5_depth_stencil_alpha_state {
 400         struct pipe_depth_stencil_alpha_state base;
 401
 402         bool early_z_enable;
 403
 404         /** Uniforms for stencil state.
 405          *
 406          * Index 0 is either the front config, or the front-and-back config.
 407          * Index 1 is the back config if doing separate back stencil.
 408          * Index 2 is the writemask config if it's not a common mask value.
 409          */
 410         uint32_t stencil_uniforms[3];
 411
 412         uint8_t stencil_front[6];
 413         uint8_t stencil_back[6];
 414 };
 415
 416 #define perf_debug(...) do {                            \
 417         if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF))       \
 418                 fprintf(stderr, __VA_ARGS__);           \
 419 } while (0)
 420
 421 static inline struct vc5_context *
 422 vc5_context(struct pipe_context *pcontext)
 423 {
 424         return (struct vc5_context *)pcontext;
 425 }
 426
 427 static inline struct vc5_sampler_view *
 428 vc5_sampler_view(struct pipe_sampler_view *psview)
 429 {
 430         return (struct vc5_sampler_view *)psview;
 431 }
 432
 433 static inline struct vc5_sampler_state *
 434 vc5_sampler_state(struct pipe_sampler_state *psampler)
 435 {
 436         return (struct vc5_sampler_state *)psampler;
 437 }
 438
 439 struct pipe_context *vc5_context_create(struct pipe_screen *pscreen,
 440                                         void *priv, unsigned flags);
 441 void vc5_draw_init(struct pipe_context *pctx);
 442 void vc5_state_init(struct pipe_context *pctx);
 443 void vc5_program_init(struct pipe_context *pctx);
 444 void vc5_program_fini(struct pipe_context *pctx);
 445 void vc5_query_init(struct pipe_context *pctx);
 446
 447 void vc5_simulator_init(struct vc5_screen *screen);
 448 void vc5_simulator_init(struct vc5_screen *screen);
 449 void vc5_simulator_destroy(struct vc5_screen *screen);
 450 void vc5_simulator_destroy(struct vc5_screen *screen);
 451 int vc5_simulator_flush(struct vc5_context *vc5,
 452                         struct drm_vc5_submit_cl *args,
 453                         struct vc5_job *job);
 454 int vc5_simulator_ioctl(int fd, unsigned long request, void *arg);
 455 void vc5_simulator_open_from_handle(int fd, uint32_t winsys_stride,
 456                                     int handle, uint32_t size);
 457
 458 static inline int
 459 vc5_ioctl(int fd, unsigned long request, void *arg)
 460 {
 461         if (using_vc5_simulator)
 462                 return vc5_simulator_ioctl(fd, request, arg);
 463         else
 464                 return drmIoctl(fd, request, arg);
 465 }
 466
 467 void vc5_set_shader_uniform_dirty_flags(struct vc5_compiled_shader *shader);
 468 struct vc5_cl_reloc vc5_write_uniforms(struct vc5_context *vc5,
 469                                        struct vc5_compiled_shader *shader,
 470                                        struct vc5_constbuf_stateobj *cb,
 471                                        struct vc5_texture_stateobj *texstate);
 472
 473 void vc5_flush(struct pipe_context *pctx);
 474 void vc5_job_init(struct vc5_context *vc5);
 475 struct vc5_job *vc5_get_job(struct vc5_context *vc5,
 476                             struct pipe_surface **cbufs,
 477                             struct pipe_surface *zsbuf);
 478 struct vc5_job *vc5_get_job_for_fbo(struct vc5_context *vc5);
 479 void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo);
 480 void vc5_job_add_write_resource(struct vc5_job *job, struct pipe_resource *prsc);
 481 void vc5_job_submit(struct vc5_context *vc5, struct vc5_job *job);
 482 void vc5_flush_jobs_writing_resource(struct vc5_context *vc5,
 483                                      struct pipe_resource *prsc);
 484 void vc5_flush_jobs_reading_resource(struct vc5_context *vc5,
 485                                      struct pipe_resource *prsc);
 486 void vc5_emit_state(struct pipe_context *pctx);
 487 void vc5_update_compiled_shaders(struct vc5_context *vc5, uint8_t prim_mode);
 488
 489 bool vc5_rt_format_supported(enum pipe_format f);
 490 bool vc5_tex_format_supported(enum pipe_format f);
 491 uint8_t vc5_get_rt_format(enum pipe_format f);
 492 uint8_t vc5_get_tex_format(enum pipe_format f);
 493 uint8_t vc5_get_tex_return_size(enum pipe_format f);
 494 uint8_t vc5_get_tex_return_channels(enum pipe_format f);
 495 const uint8_t *vc5_get_format_swizzle(enum pipe_format f);
 496 void vc5_get_internal_type_bpp_for_output_format(uint32_t format,
 497                                                  uint32_t *type,
 498                                                  uint32_t *bpp);
 499
 500 void vc5_init_query_functions(struct vc5_context *vc5);
 501 void vc5_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 502 void vc5_blitter_save(struct vc5_context *vc5);
 503 void vc5_emit_rcl(struct vc5_job *job);
 504
 505
 506 #endif /* VC5_CONTEXT_H */