2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "pipe/p_context.h"
31 #include "pipe/p_state.h"
32 #include "util/bitset.h"
33 #include "util/slab.h"
36 #include "vc5_screen.h"
40 void vc5_job_add_bo(struct vc5_job
*job
, struct vc5_bo
*bo
);
44 #include "vc5_bufmgr.h"
45 #include "vc5_resource.h"
48 #ifdef USE_VC5_SIMULATOR
49 #define using_vc5_simulator true
51 #define using_vc5_simulator false
54 #define VC5_DIRTY_BLEND (1 << 0)
55 #define VC5_DIRTY_RASTERIZER (1 << 1)
56 #define VC5_DIRTY_ZSA (1 << 2)
57 #define VC5_DIRTY_FRAGTEX (1 << 3)
58 #define VC5_DIRTY_VERTTEX (1 << 4)
60 #define VC5_DIRTY_BLEND_COLOR (1 << 7)
61 #define VC5_DIRTY_STENCIL_REF (1 << 8)
62 #define VC5_DIRTY_SAMPLE_MASK (1 << 9)
63 #define VC5_DIRTY_FRAMEBUFFER (1 << 10)
64 #define VC5_DIRTY_STIPPLE (1 << 11)
65 #define VC5_DIRTY_VIEWPORT (1 << 12)
66 #define VC5_DIRTY_CONSTBUF (1 << 13)
67 #define VC5_DIRTY_VTXSTATE (1 << 14)
68 #define VC5_DIRTY_VTXBUF (1 << 15)
69 #define VC5_DIRTY_SCISSOR (1 << 17)
70 #define VC5_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
71 #define VC5_DIRTY_PRIM_MODE (1 << 19)
72 #define VC5_DIRTY_CLIP (1 << 20)
73 #define VC5_DIRTY_UNCOMPILED_VS (1 << 21)
74 #define VC5_DIRTY_UNCOMPILED_FS (1 << 22)
75 #define VC5_DIRTY_COMPILED_CS (1 << 23)
76 #define VC5_DIRTY_COMPILED_VS (1 << 24)
77 #define VC5_DIRTY_COMPILED_FS (1 << 25)
78 #define VC5_DIRTY_FS_INPUTS (1 << 26)
79 #define VC5_DIRTY_STREAMOUT (1 << 27)
81 #define VC5_MAX_FS_INPUTS 64
83 struct vc5_sampler_view
{
84 struct pipe_sampler_view base
;
87 /* Precomputed swizzles to pass in to the shader key. */
90 uint8_t texture_shader_state
[32];
93 struct vc5_sampler_state
{
94 struct pipe_sampler_state base
;
98 uint8_t texture_shader_state
[32];
101 struct vc5_texture_stateobj
{
102 struct pipe_sampler_view
*textures
[PIPE_MAX_SAMPLERS
];
103 unsigned num_textures
;
104 struct pipe_sampler_state
*samplers
[PIPE_MAX_SAMPLERS
];
105 unsigned num_samplers
;
106 struct vc5_cl_reloc texture_state
[PIPE_MAX_SAMPLERS
];
109 struct vc5_shader_uniform_info
{
110 enum quniform_contents
*contents
;
115 struct vc5_uncompiled_shader
{
116 /** A name for this program, so you can track it in shader-db output. */
118 /** How many variants of this program were compiled, for shader-db. */
119 uint32_t compiled_variant_count
;
120 struct pipe_shader_state base
;
121 uint32_t num_tf_outputs
;
122 struct v3d_varying_slot
*tf_outputs
;
123 uint16_t tf_specs
[PIPE_MAX_SO_BUFFERS
];
124 uint32_t num_tf_specs
;
127 struct vc5_compiled_shader
{
131 struct v3d_prog_data
*base
;
132 struct v3d_vs_prog_data
*vs
;
133 struct v3d_fs_prog_data
*fs
;
137 * VC5_DIRTY_* flags that, when set in vc5->dirty, mean that the
138 * uniforms have to be rewritten (and therefore the shader state
141 uint32_t uniform_dirty_bits
;
144 struct vc5_program_stateobj
{
145 struct vc5_uncompiled_shader
*bind_vs
, *bind_fs
;
146 struct vc5_compiled_shader
*cs
, *vs
, *fs
;
149 struct vc5_constbuf_stateobj
{
150 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
151 uint32_t enabled_mask
;
155 struct vc5_vertexbuf_stateobj
{
156 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
158 uint32_t enabled_mask
;
162 struct vc5_vertex_stateobj
{
163 struct pipe_vertex_element pipe
[VC5_MAX_ATTRIBUTES
];
164 unsigned num_elements
;
166 uint8_t attrs
[12 * VC5_MAX_ATTRIBUTES
];
167 struct vc5_bo
*default_attribute_values
;
170 struct vc5_streamout_stateobj
{
171 struct pipe_stream_output_target
*targets
[PIPE_MAX_SO_BUFFERS
];
172 unsigned num_targets
;
175 /* Hash table key for vc5->jobs */
177 struct pipe_surface
*cbufs
[4];
178 struct pipe_surface
*zsbuf
;
182 * A complete bin/render job.
184 * This is all of the state necessary to submit a bin/render to the kernel.
185 * We want to be able to have multiple in progress at a time, so that we don't
186 * need to flush an existing CL just to switch to rendering to a new render
187 * target (which would mean reading back from the old render target when
188 * starting to render to it again).
191 struct vc5_context
*vc5
;
194 struct vc5_cl indirect
;
195 struct vc5_bo
*tile_alloc
;
196 uint32_t shader_rec_count
;
198 struct drm_vc5_submit_cl submit
;
201 * Set of all BOs referenced by the job. This will be used for making
202 * the list of BOs that the kernel will need to have paged in to
207 struct set
*write_prscs
;
209 /* Size of the submit.bo_handles array. */
210 uint32_t bo_handles_size
;
212 /** @{ Surfaces to submit rendering for. */
213 struct pipe_surface
*cbufs
[4];
214 struct pipe_surface
*zsbuf
;
217 * Bounding box of the scissor across all queued drawing.
219 * Note that the max values are exclusive.
227 * Width/height of the color framebuffer being rendered to,
228 * for VC5_TILE_RENDERING_MODE_CONFIG.
231 uint32_t draw_height
;
233 /** @{ Tile information, depending on MSAA and float color buffer. */
234 uint32_t draw_tiles_x
; /** @< Number of tiles wide for framebuffer. */
235 uint32_t draw_tiles_y
; /** @< Number of tiles high for framebuffer. */
237 uint32_t tile_width
; /** @< Width of a tile. */
238 uint32_t tile_height
; /** @< Height of a tile. */
239 /** maximum internal_bpp of all color render targets. */
240 uint32_t internal_bpp
;
242 /** Whether the current rendering is in a 4X MSAA tile buffer. */
246 /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
250 /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
251 * (either clears or draws).
254 uint32_t clear_color
[4][4];
259 * Set if some drawing (triangles, blits, or just a glClear()) has
260 * been done to the FBO, meaning that we need to
261 * DRM_IOCTL_VC5_SUBMIT_CL.
268 * Number of draw calls (not counting full buffer clears) queued in
271 uint32_t draw_calls_queued
;
273 struct vc5_job_key key
;
277 struct pipe_context base
;
280 struct vc5_screen
*screen
;
282 /** The 3D rendering job for the currently bound FBO. */
285 /* Map from struct vc5_job_key to the job for that FBO.
287 struct hash_table
*jobs
;
290 * Map from vc5_resource to a job writing to that resource.
292 * Primarily for flushing jobs rendering to textures that are now
295 struct hash_table
*write_jobs
;
297 struct slab_child_pool transfer_pool
;
298 struct blitter_context
*blitter
;
300 /** bitfield of VC5_DIRTY_* */
303 struct primconvert_context
*primconvert
;
305 struct hash_table
*fs_cache
, *vs_cache
;
306 uint32_t next_uncompiled_program_id
;
307 uint64_t next_compiled_program_id
;
309 struct vc5_compiler_state
*compiler_state
;
313 /** Maximum index buffer valid for the current shader_rec. */
316 /** Seqno of the last CL flush's job. */
317 uint64_t last_emit_seqno
;
319 struct u_upload_mgr
*uploader
;
321 /** @{ Current pipeline state objects */
322 struct pipe_scissor_state scissor
;
323 struct pipe_blend_state
*blend
;
324 struct vc5_rasterizer_state
*rasterizer
;
325 struct vc5_depth_stencil_alpha_state
*zsa
;
327 struct vc5_texture_stateobj verttex
, fragtex
;
329 struct vc5_program_stateobj prog
;
331 struct vc5_vertex_stateobj
*vtx
;
334 struct pipe_blend_color f
;
337 struct pipe_stencil_ref stencil_ref
;
338 unsigned sample_mask
;
339 struct pipe_framebuffer_state framebuffer
;
341 /* Per render target, whether we should swap the R and B fields in the
342 * shader's color output and in blending. If render targets disagree
343 * on the R/B swap and use the constant color, then we would need to
344 * fall back to in-shader blending.
346 uint8_t swap_color_rb
;
348 struct pipe_poly_stipple stipple
;
349 struct pipe_clip_state clip
;
350 struct pipe_viewport_state viewport
;
351 struct vc5_constbuf_stateobj constbuf
[PIPE_SHADER_TYPES
];
352 struct vc5_vertexbuf_stateobj vertexbuf
;
353 struct vc5_streamout_stateobj streamout
;
357 struct vc5_rasterizer_state
{
358 struct pipe_rasterizer_state base
;
360 /* VC5_CONFIGURATION_BITS */
361 uint8_t config_bits
[3];
366 * Half-float (1/8/7 bits) value of polygon offset units for
367 * VC5_PACKET_DEPTH_OFFSET
369 uint16_t offset_units
;
371 * Half-float (1/8/7 bits) value of polygon offset scale for
372 * VC5_PACKET_DEPTH_OFFSET
374 uint16_t offset_factor
;
377 struct vc5_depth_stencil_alpha_state
{
378 struct pipe_depth_stencil_alpha_state base
;
382 /** Uniforms for stencil state.
384 * Index 0 is either the front config, or the front-and-back config.
385 * Index 1 is the back config if doing separate back stencil.
386 * Index 2 is the writemask config if it's not a common mask value.
388 uint32_t stencil_uniforms
[3];
391 #define perf_debug(...) do { \
392 if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF)) \
393 fprintf(stderr, __VA_ARGS__); \
396 static inline struct vc5_context
*
397 vc5_context(struct pipe_context
*pcontext
)
399 return (struct vc5_context
*)pcontext
;
402 static inline struct vc5_sampler_view
*
403 vc5_sampler_view(struct pipe_sampler_view
*psview
)
405 return (struct vc5_sampler_view
*)psview
;
408 static inline struct vc5_sampler_state
*
409 vc5_sampler_state(struct pipe_sampler_state
*psampler
)
411 return (struct vc5_sampler_state
*)psampler
;
414 struct pipe_context
*vc5_context_create(struct pipe_screen
*pscreen
,
415 void *priv
, unsigned flags
);
416 void vc5_draw_init(struct pipe_context
*pctx
);
417 void vc5_state_init(struct pipe_context
*pctx
);
418 void vc5_program_init(struct pipe_context
*pctx
);
419 void vc5_program_fini(struct pipe_context
*pctx
);
420 void vc5_query_init(struct pipe_context
*pctx
);
422 void vc5_simulator_init(struct vc5_screen
*screen
);
423 void vc5_simulator_init(struct vc5_screen
*screen
);
424 void vc5_simulator_destroy(struct vc5_screen
*screen
);
425 void vc5_simulator_destroy(struct vc5_screen
*screen
);
426 int vc5_simulator_flush(struct vc5_context
*vc5
,
427 struct drm_vc5_submit_cl
*args
,
428 struct vc5_job
*job
);
429 int vc5_simulator_ioctl(int fd
, unsigned long request
, void *arg
);
430 void vc5_simulator_open_from_handle(int fd
, uint32_t winsys_stride
,
431 int handle
, uint32_t size
);
434 vc5_ioctl(int fd
, unsigned long request
, void *arg
)
436 if (using_vc5_simulator
)
437 return vc5_simulator_ioctl(fd
, request
, arg
);
439 return drmIoctl(fd
, request
, arg
);
442 void vc5_set_shader_uniform_dirty_flags(struct vc5_compiled_shader
*shader
);
443 struct vc5_cl_reloc
vc5_write_uniforms(struct vc5_context
*vc5
,
444 struct vc5_compiled_shader
*shader
,
445 struct vc5_constbuf_stateobj
*cb
,
446 struct vc5_texture_stateobj
*texstate
);
448 void vc5_flush(struct pipe_context
*pctx
);
449 void vc5_job_init(struct vc5_context
*vc5
);
450 struct vc5_job
*vc5_get_job(struct vc5_context
*vc5
,
451 struct pipe_surface
**cbufs
,
452 struct pipe_surface
*zsbuf
);
453 struct vc5_job
*vc5_get_job_for_fbo(struct vc5_context
*vc5
);
454 void vc5_job_add_bo(struct vc5_job
*job
, struct vc5_bo
*bo
);
455 void vc5_job_add_write_resource(struct vc5_job
*job
, struct pipe_resource
*prsc
);
456 void vc5_job_submit(struct vc5_context
*vc5
, struct vc5_job
*job
);
457 void vc5_flush_jobs_writing_resource(struct vc5_context
*vc5
,
458 struct pipe_resource
*prsc
);
459 void vc5_flush_jobs_reading_resource(struct vc5_context
*vc5
,
460 struct pipe_resource
*prsc
);
461 void vc5_emit_state(struct pipe_context
*pctx
);
462 void vc5_update_compiled_shaders(struct vc5_context
*vc5
, uint8_t prim_mode
);
464 bool vc5_rt_format_supported(enum pipe_format f
);
465 bool vc5_tex_format_supported(enum pipe_format f
);
466 uint8_t vc5_get_rt_format(enum pipe_format f
);
467 uint8_t vc5_get_tex_format(enum pipe_format f
);
468 uint8_t vc5_get_tex_return_size(enum pipe_format f
);
469 uint8_t vc5_get_tex_return_channels(enum pipe_format f
);
470 const uint8_t *vc5_get_format_swizzle(enum pipe_format f
);
471 void vc5_get_internal_type_bpp_for_output_format(uint32_t format
,
475 void vc5_init_query_functions(struct vc5_context
*vc5
);
476 void vc5_blit(struct pipe_context
*pctx
, const struct pipe_blit_info
*blit_info
);
477 void vc5_blitter_save(struct vc5_context
*vc5
);
478 void vc5_emit_rcl(struct vc5_job
*job
);
481 #endif /* VC5_CONTEXT_H */