src/gallium/drivers/vc5/vc5_context.h

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC5_CONTEXT_H
  26 #define VC5_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/bitset.h"
  33 #include "util/slab.h"
  34 #include "xf86drm.h"
  35 #include "vc5_drm.h"
  36 #include "vc5_screen.h"
  37
  38 struct vc5_job;
  39 struct vc5_bo;
  40 void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo);
  41
  42 #define __user
  43 #include "vc5_drm.h"
  44 #include "vc5_bufmgr.h"
  45 #include "vc5_resource.h"
  46 #include "vc5_cl.h"
  47
  48 #ifdef USE_VC5_SIMULATOR
  49 #define using_vc5_simulator true
  50 #else
  51 #define using_vc5_simulator false
  52 #endif
  53
  54 #define VC5_DIRTY_BLEND         (1 <<  0)
  55 #define VC5_DIRTY_RASTERIZER    (1 <<  1)
  56 #define VC5_DIRTY_ZSA           (1 <<  2)
  57 #define VC5_DIRTY_FRAGTEX       (1 <<  3)
  58 #define VC5_DIRTY_VERTTEX       (1 <<  4)
  59
  60 #define VC5_DIRTY_BLEND_COLOR   (1 <<  7)
  61 #define VC5_DIRTY_STENCIL_REF   (1 <<  8)
  62 #define VC5_DIRTY_SAMPLE_MASK   (1 <<  9)
  63 #define VC5_DIRTY_FRAMEBUFFER   (1 << 10)
  64 #define VC5_DIRTY_STIPPLE       (1 << 11)
  65 #define VC5_DIRTY_VIEWPORT      (1 << 12)
  66 #define VC5_DIRTY_CONSTBUF      (1 << 13)
  67 #define VC5_DIRTY_VTXSTATE      (1 << 14)
  68 #define VC5_DIRTY_VTXBUF        (1 << 15)
  69 #define VC5_DIRTY_SCISSOR       (1 << 17)
  70 #define VC5_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  71 #define VC5_DIRTY_PRIM_MODE     (1 << 19)
  72 #define VC5_DIRTY_CLIP          (1 << 20)
  73 #define VC5_DIRTY_UNCOMPILED_VS (1 << 21)
  74 #define VC5_DIRTY_UNCOMPILED_FS (1 << 22)
  75 #define VC5_DIRTY_COMPILED_CS   (1 << 23)
  76 #define VC5_DIRTY_COMPILED_VS   (1 << 24)
  77 #define VC5_DIRTY_COMPILED_FS   (1 << 25)
  78 #define VC5_DIRTY_FS_INPUTS     (1 << 26)
  79 #define VC5_DIRTY_STREAMOUT     (1 << 27)
  80
  81 #define VC5_MAX_FS_INPUTS 64
  82
  83 struct vc5_sampler_view {
  84         struct pipe_sampler_view base;
  85         uint32_t p0;
  86         uint32_t p1;
  87         /* Precomputed swizzles to pass in to the shader key. */
  88         uint8_t swizzle[4];
  89
  90         uint8_t texture_shader_state[32];
  91 };
  92
  93 struct vc5_sampler_state {
  94         struct pipe_sampler_state base;
  95         uint32_t p0;
  96         uint32_t p1;
  97
  98         uint8_t texture_shader_state[32];
  99 };
 100
 101 struct vc5_texture_stateobj {
 102         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
 103         unsigned num_textures;
 104         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
 105         unsigned num_samplers;
 106         struct vc5_cl_reloc texture_state[PIPE_MAX_SAMPLERS];
 107 };
 108
 109 struct vc5_shader_uniform_info {
 110         enum quniform_contents *contents;
 111         uint32_t *data;
 112         uint32_t count;
 113 };
 114
 115 struct vc5_uncompiled_shader {
 116         /** A name for this program, so you can track it in shader-db output. */
 117         uint32_t program_id;
 118         /** How many variants of this program were compiled, for shader-db. */
 119         uint32_t compiled_variant_count;
 120         struct pipe_shader_state base;
 121         uint32_t num_tf_outputs;
 122         struct v3d_varying_slot *tf_outputs;
 123         uint16_t tf_specs[PIPE_MAX_SO_BUFFERS];
 124         uint32_t num_tf_specs;
 125 };
 126
 127 struct vc5_compiled_shader {
 128         struct vc5_bo *bo;
 129
 130         union {
 131                 struct v3d_prog_data *base;
 132                 struct v3d_vs_prog_data *vs;
 133                 struct v3d_fs_prog_data *fs;
 134         } prog_data;
 135
 136         /**
 137          * VC5_DIRTY_* flags that, when set in vc5->dirty, mean that the
 138          * uniforms have to be rewritten (and therefore the shader state
 139          * reemitted).
 140          */
 141         uint32_t uniform_dirty_bits;
 142 };
 143
 144 struct vc5_program_stateobj {
 145         struct vc5_uncompiled_shader *bind_vs, *bind_fs;
 146         struct vc5_compiled_shader *cs, *vs, *fs;
 147 };
 148
 149 struct vc5_constbuf_stateobj {
 150         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 151         uint32_t enabled_mask;
 152         uint32_t dirty_mask;
 153 };
 154
 155 struct vc5_vertexbuf_stateobj {
 156         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 157         unsigned count;
 158         uint32_t enabled_mask;
 159         uint32_t dirty_mask;
 160 };
 161
 162 struct vc5_vertex_stateobj {
 163         struct pipe_vertex_element pipe[VC5_MAX_ATTRIBUTES];
 164         unsigned num_elements;
 165
 166         uint8_t attrs[12 * VC5_MAX_ATTRIBUTES];
 167         struct vc5_bo *default_attribute_values;
 168 };
 169
 170 struct vc5_streamout_stateobj {
 171         struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
 172         unsigned num_targets;
 173 };
 174
 175 /* Hash table key for vc5->jobs */
 176 struct vc5_job_key {
 177         struct pipe_surface *cbufs[4];
 178         struct pipe_surface *zsbuf;
 179 };
 180
 181 /**
 182  * A complete bin/render job.
 183  *
 184  * This is all of the state necessary to submit a bin/render to the kernel.
 185  * We want to be able to have multiple in progress at a time, so that we don't
 186  * need to flush an existing CL just to switch to rendering to a new render
 187  * target (which would mean reading back from the old render target when
 188  * starting to render to it again).
 189  */
 190 struct vc5_job {
 191         struct vc5_context *vc5;
 192         struct vc5_cl bcl;
 193         struct vc5_cl rcl;
 194         struct vc5_cl indirect;
 195         struct vc5_bo *tile_alloc;
 196         uint32_t shader_rec_count;
 197
 198         struct drm_vc5_submit_cl submit;
 199
 200         /**
 201          * Set of all BOs referenced by the job.  This will be used for making
 202          * the list of BOs that the kernel will need to have paged in to
 203          * execute our job.
 204          */
 205         struct set *bos;
 206
 207         struct set *write_prscs;
 208
 209         /* Size of the submit.bo_handles array. */
 210         uint32_t bo_handles_size;
 211
 212         /** @{ Surfaces to submit rendering for. */
 213         struct pipe_surface *cbufs[4];
 214         struct pipe_surface *zsbuf;
 215         /** @} */
 216         /** @{
 217          * Bounding box of the scissor across all queued drawing.
 218          *
 219          * Note that the max values are exclusive.
 220          */
 221         uint32_t draw_min_x;
 222         uint32_t draw_min_y;
 223         uint32_t draw_max_x;
 224         uint32_t draw_max_y;
 225         /** @} */
 226         /** @{
 227          * Width/height of the color framebuffer being rendered to,
 228          * for VC5_TILE_RENDERING_MODE_CONFIG.
 229         */
 230         uint32_t draw_width;
 231         uint32_t draw_height;
 232         /** @} */
 233         /** @{ Tile information, depending on MSAA and float color buffer. */
 234         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 235         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 236
 237         uint32_t tile_width; /** @< Width of a tile. */
 238         uint32_t tile_height; /** @< Height of a tile. */
 239         /** maximum internal_bpp of all color render targets. */
 240         uint32_t internal_bpp;
 241
 242         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 243         bool msaa;
 244         /** @} */
 245
 246         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 247          * first rendering.
 248          */
 249         uint32_t cleared;
 250         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 251          * (either clears or draws).
 252          */
 253         uint32_t resolve;
 254         uint32_t clear_color[4][4];
 255         float clear_z;
 256         uint8_t clear_s;
 257
 258         /**
 259          * Set if some drawing (triangles, blits, or just a glClear()) has
 260          * been done to the FBO, meaning that we need to
 261          * DRM_IOCTL_VC5_SUBMIT_CL.
 262          */
 263         bool needs_flush;
 264
 265         bool uses_early_z;
 266
 267         /**
 268          * Number of draw calls (not counting full buffer clears) queued in
 269          * the current job.
 270          */
 271         uint32_t draw_calls_queued;
 272
 273         struct vc5_job_key key;
 274 };
 275
 276 struct vc5_context {
 277         struct pipe_context base;
 278
 279         int fd;
 280         struct vc5_screen *screen;
 281
 282         /** The 3D rendering job for the currently bound FBO. */
 283         struct vc5_job *job;
 284
 285         /* Map from struct vc5_job_key to the job for that FBO.
 286          */
 287         struct hash_table *jobs;
 288
 289         /**
 290          * Map from vc5_resource to a job writing to that resource.
 291          *
 292          * Primarily for flushing jobs rendering to textures that are now
 293          * being read from.
 294          */
 295         struct hash_table *write_jobs;
 296
 297         struct slab_child_pool transfer_pool;
 298         struct blitter_context *blitter;
 299
 300         /** bitfield of VC5_DIRTY_* */
 301         uint32_t dirty;
 302
 303         struct primconvert_context *primconvert;
 304
 305         struct hash_table *fs_cache, *vs_cache;
 306         uint32_t next_uncompiled_program_id;
 307         uint64_t next_compiled_program_id;
 308
 309         struct vc5_compiler_state *compiler_state;
 310
 311         uint8_t prim_mode;
 312
 313         /** Maximum index buffer valid for the current shader_rec. */
 314         uint32_t max_index;
 315
 316         /** Seqno of the last CL flush's job. */
 317         uint64_t last_emit_seqno;
 318
 319         struct u_upload_mgr *uploader;
 320
 321         /** @{ Current pipeline state objects */
 322         struct pipe_scissor_state scissor;
 323         struct pipe_blend_state *blend;
 324         struct vc5_rasterizer_state *rasterizer;
 325         struct vc5_depth_stencil_alpha_state *zsa;
 326
 327         struct vc5_texture_stateobj verttex, fragtex;
 328
 329         struct vc5_program_stateobj prog;
 330
 331         struct vc5_vertex_stateobj *vtx;
 332
 333         struct {
 334                 struct pipe_blend_color f;
 335                 uint16_t hf[4];
 336         } blend_color;
 337         struct pipe_stencil_ref stencil_ref;
 338         unsigned sample_mask;
 339         struct pipe_framebuffer_state framebuffer;
 340         struct pipe_poly_stipple stipple;
 341         struct pipe_clip_state clip;
 342         struct pipe_viewport_state viewport;
 343         struct vc5_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 344         struct vc5_vertexbuf_stateobj vertexbuf;
 345         struct vc5_streamout_stateobj streamout;
 346         /** @} */
 347 };
 348
 349 struct vc5_rasterizer_state {
 350         struct pipe_rasterizer_state base;
 351
 352         /* VC5_CONFIGURATION_BITS */
 353         uint8_t config_bits[3];
 354
 355         float point_size;
 356
 357         /**
 358          * Half-float (1/8/7 bits) value of polygon offset units for
 359          * VC5_PACKET_DEPTH_OFFSET
 360          */
 361         uint16_t offset_units;
 362         /**
 363          * Half-float (1/8/7 bits) value of polygon offset scale for
 364          * VC5_PACKET_DEPTH_OFFSET
 365          */
 366         uint16_t offset_factor;
 367 };
 368
 369 struct vc5_depth_stencil_alpha_state {
 370         struct pipe_depth_stencil_alpha_state base;
 371
 372         bool early_z_enable;
 373
 374         /** Uniforms for stencil state.
 375          *
 376          * Index 0 is either the front config, or the front-and-back config.
 377          * Index 1 is the back config if doing separate back stencil.
 378          * Index 2 is the writemask config if it's not a common mask value.
 379          */
 380         uint32_t stencil_uniforms[3];
 381 };
 382
 383 #define perf_debug(...) do {                            \
 384         if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF))       \
 385                 fprintf(stderr, __VA_ARGS__);           \
 386 } while (0)
 387
 388 static inline struct vc5_context *
 389 vc5_context(struct pipe_context *pcontext)
 390 {
 391         return (struct vc5_context *)pcontext;
 392 }
 393
 394 static inline struct vc5_sampler_view *
 395 vc5_sampler_view(struct pipe_sampler_view *psview)
 396 {
 397         return (struct vc5_sampler_view *)psview;
 398 }
 399
 400 static inline struct vc5_sampler_state *
 401 vc5_sampler_state(struct pipe_sampler_state *psampler)
 402 {
 403         return (struct vc5_sampler_state *)psampler;
 404 }
 405
 406 struct pipe_context *vc5_context_create(struct pipe_screen *pscreen,
 407                                         void *priv, unsigned flags);
 408 void vc5_draw_init(struct pipe_context *pctx);
 409 void vc5_state_init(struct pipe_context *pctx);
 410 void vc5_program_init(struct pipe_context *pctx);
 411 void vc5_program_fini(struct pipe_context *pctx);
 412 void vc5_query_init(struct pipe_context *pctx);
 413
 414 void vc5_simulator_init(struct vc5_screen *screen);
 415 void vc5_simulator_init(struct vc5_screen *screen);
 416 void vc5_simulator_destroy(struct vc5_screen *screen);
 417 void vc5_simulator_destroy(struct vc5_screen *screen);
 418 int vc5_simulator_flush(struct vc5_context *vc5,
 419                         struct drm_vc5_submit_cl *args,
 420                         struct vc5_job *job);
 421 int vc5_simulator_ioctl(int fd, unsigned long request, void *arg);
 422 void vc5_simulator_open_from_handle(int fd, uint32_t winsys_stride,
 423                                     int handle, uint32_t size);
 424
 425 static inline int
 426 vc5_ioctl(int fd, unsigned long request, void *arg)
 427 {
 428         if (using_vc5_simulator)
 429                 return vc5_simulator_ioctl(fd, request, arg);
 430         else
 431                 return drmIoctl(fd, request, arg);
 432 }
 433
 434 void vc5_set_shader_uniform_dirty_flags(struct vc5_compiled_shader *shader);
 435 struct vc5_cl_reloc vc5_write_uniforms(struct vc5_context *vc5,
 436                                        struct vc5_compiled_shader *shader,
 437                                        struct vc5_constbuf_stateobj *cb,
 438                                        struct vc5_texture_stateobj *texstate);
 439
 440 void vc5_flush(struct pipe_context *pctx);
 441 void vc5_job_init(struct vc5_context *vc5);
 442 struct vc5_job *vc5_get_job(struct vc5_context *vc5,
 443                             struct pipe_surface **cbufs,
 444                             struct pipe_surface *zsbuf);
 445 struct vc5_job *vc5_get_job_for_fbo(struct vc5_context *vc5);
 446 void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo);
 447 void vc5_job_add_write_resource(struct vc5_job *job, struct pipe_resource *prsc);
 448 void vc5_job_submit(struct vc5_context *vc5, struct vc5_job *job);
 449 void vc5_flush_jobs_writing_resource(struct vc5_context *vc5,
 450                                      struct pipe_resource *prsc);
 451 void vc5_flush_jobs_reading_resource(struct vc5_context *vc5,
 452                                      struct pipe_resource *prsc);
 453 void vc5_emit_state(struct pipe_context *pctx);
 454 void vc5_update_compiled_shaders(struct vc5_context *vc5, uint8_t prim_mode);
 455
 456 bool vc5_rt_format_supported(enum pipe_format f);
 457 bool vc5_tex_format_supported(enum pipe_format f);
 458 uint8_t vc5_get_rt_format(enum pipe_format f);
 459 uint8_t vc5_get_tex_format(enum pipe_format f);
 460 uint8_t vc5_get_tex_return_size(enum pipe_format f);
 461 uint8_t vc5_get_tex_return_channels(enum pipe_format f);
 462 const uint8_t *vc5_get_format_swizzle(enum pipe_format f);
 463 void vc5_get_internal_type_bpp_for_output_format(uint32_t format,
 464                                                  uint32_t *type,
 465                                                  uint32_t *bpp);
 466
 467 void vc5_init_query_functions(struct vc5_context *vc5);
 468 void vc5_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 469 void vc5_blitter_save(struct vc5_context *vc5);
 470 void vc5_emit_rcl(struct vc5_job *job);
 471
 472
 473 #endif /* VC5_CONTEXT_H */