src/gallium/drivers/vc5/vc5_context.h

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC5_CONTEXT_H
  26 #define VC5_CONTEXT_H
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_context.h"
  31 #include "pipe/p_state.h"
  32 #include "util/bitset.h"
  33 #include "util/slab.h"
  34 #include "xf86drm.h"
  35 #include "vc5_drm.h"
  36
  37 struct vc5_job;
  38 struct vc5_bo;
  39 void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo);
  40
  41 #define __user
  42 #include "vc5_drm.h"
  43 #include "vc5_bufmgr.h"
  44 #include "vc5_resource.h"
  45 #include "vc5_cl.h"
  46
  47 #ifdef USE_VC5_SIMULATOR
  48 #define using_vc5_simulator true
  49 #else
  50 #define using_vc5_simulator false
  51 #endif
  52
  53 #define VC5_DIRTY_BLEND         (1 <<  0)
  54 #define VC5_DIRTY_RASTERIZER    (1 <<  1)
  55 #define VC5_DIRTY_ZSA           (1 <<  2)
  56 #define VC5_DIRTY_FRAGTEX       (1 <<  3)
  57 #define VC5_DIRTY_VERTTEX       (1 <<  4)
  58
  59 #define VC5_DIRTY_BLEND_COLOR   (1 <<  7)
  60 #define VC5_DIRTY_STENCIL_REF   (1 <<  8)
  61 #define VC5_DIRTY_SAMPLE_MASK   (1 <<  9)
  62 #define VC5_DIRTY_FRAMEBUFFER   (1 << 10)
  63 #define VC5_DIRTY_STIPPLE       (1 << 11)
  64 #define VC5_DIRTY_VIEWPORT      (1 << 12)
  65 #define VC5_DIRTY_CONSTBUF      (1 << 13)
  66 #define VC5_DIRTY_VTXSTATE      (1 << 14)
  67 #define VC5_DIRTY_VTXBUF        (1 << 15)
  68 #define VC5_DIRTY_SCISSOR       (1 << 17)
  69 #define VC5_DIRTY_FLAT_SHADE_FLAGS (1 << 18)
  70 #define VC5_DIRTY_PRIM_MODE     (1 << 19)
  71 #define VC5_DIRTY_CLIP          (1 << 20)
  72 #define VC5_DIRTY_UNCOMPILED_VS (1 << 21)
  73 #define VC5_DIRTY_UNCOMPILED_FS (1 << 22)
  74 #define VC5_DIRTY_COMPILED_CS   (1 << 23)
  75 #define VC5_DIRTY_COMPILED_VS   (1 << 24)
  76 #define VC5_DIRTY_COMPILED_FS   (1 << 25)
  77 #define VC5_DIRTY_FS_INPUTS     (1 << 26)
  78 #define VC5_DIRTY_STREAMOUT     (1 << 27)
  79
  80 #define VC5_MAX_FS_INPUTS 64
  81
  82 struct vc5_sampler_view {
  83         struct pipe_sampler_view base;
  84         uint32_t p0;
  85         uint32_t p1;
  86         /* Precomputed swizzles to pass in to the shader key. */
  87         uint8_t swizzle[4];
  88
  89         uint8_t texture_shader_state[32];
  90 };
  91
  92 struct vc5_sampler_state {
  93         struct pipe_sampler_state base;
  94         uint32_t p0;
  95         uint32_t p1;
  96
  97         uint8_t texture_shader_state[32];
  98 };
  99
 100 struct vc5_texture_stateobj {
 101         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
 102         unsigned num_textures;
 103         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
 104         unsigned num_samplers;
 105         struct vc5_cl_reloc texture_state[PIPE_MAX_SAMPLERS];
 106 };
 107
 108 struct vc5_shader_uniform_info {
 109         enum quniform_contents *contents;
 110         uint32_t *data;
 111         uint32_t count;
 112 };
 113
 114 struct vc5_uncompiled_shader {
 115         /** A name for this program, so you can track it in shader-db output. */
 116         uint32_t program_id;
 117         /** How many variants of this program were compiled, for shader-db. */
 118         uint32_t compiled_variant_count;
 119         struct pipe_shader_state base;
 120         uint32_t num_tf_outputs;
 121         struct v3d_varying_slot *tf_outputs;
 122         uint16_t tf_specs[PIPE_MAX_SO_BUFFERS];
 123         uint32_t num_tf_specs;
 124 };
 125
 126 struct vc5_compiled_shader {
 127         struct vc5_bo *bo;
 128
 129         union {
 130                 struct v3d_prog_data *base;
 131                 struct v3d_vs_prog_data *vs;
 132                 struct v3d_fs_prog_data *fs;
 133         } prog_data;
 134
 135         /**
 136          * VC5_DIRTY_* flags that, when set in vc5->dirty, mean that the
 137          * uniforms have to be rewritten (and therefore the shader state
 138          * reemitted).
 139          */
 140         uint32_t uniform_dirty_bits;
 141 };
 142
 143 struct vc5_program_stateobj {
 144         struct vc5_uncompiled_shader *bind_vs, *bind_fs;
 145         struct vc5_compiled_shader *cs, *vs, *fs;
 146 };
 147
 148 struct vc5_constbuf_stateobj {
 149         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
 150         uint32_t enabled_mask;
 151         uint32_t dirty_mask;
 152 };
 153
 154 struct vc5_vertexbuf_stateobj {
 155         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
 156         unsigned count;
 157         uint32_t enabled_mask;
 158         uint32_t dirty_mask;
 159 };
 160
 161 struct vc5_vertex_stateobj {
 162         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
 163         unsigned num_elements;
 164 };
 165
 166 struct vc5_streamout_stateobj {
 167         struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
 168         unsigned num_targets;
 169 };
 170
 171 /* Hash table key for vc5->jobs */
 172 struct vc5_job_key {
 173         struct pipe_surface *cbufs[4];
 174         struct pipe_surface *zsbuf;
 175 };
 176
 177 /**
 178  * A complete bin/render job.
 179  *
 180  * This is all of the state necessary to submit a bin/render to the kernel.
 181  * We want to be able to have multiple in progress at a time, so that we don't
 182  * need to flush an existing CL just to switch to rendering to a new render
 183  * target (which would mean reading back from the old render target when
 184  * starting to render to it again).
 185  */
 186 struct vc5_job {
 187         struct vc5_context *vc5;
 188         struct vc5_cl bcl;
 189         struct vc5_cl rcl;
 190         struct vc5_cl indirect;
 191         struct vc5_bo *tile_alloc;
 192         uint32_t shader_rec_count;
 193
 194         struct drm_vc5_submit_cl submit;
 195
 196         /**
 197          * Set of all BOs referenced by the job.  This will be used for making
 198          * the list of BOs that the kernel will need to have paged in to
 199          * execute our job.
 200          */
 201         struct set *bos;
 202         /* Size of the submit.bo_handles array. */
 203         uint32_t bo_handles_size;
 204
 205         /** @{ Surfaces to submit rendering for. */
 206         struct pipe_surface *cbufs[4];
 207         struct pipe_surface *zsbuf;
 208         /** @} */
 209         /** @{
 210          * Bounding box of the scissor across all queued drawing.
 211          *
 212          * Note that the max values are exclusive.
 213          */
 214         uint32_t draw_min_x;
 215         uint32_t draw_min_y;
 216         uint32_t draw_max_x;
 217         uint32_t draw_max_y;
 218         /** @} */
 219         /** @{
 220          * Width/height of the color framebuffer being rendered to,
 221          * for VC5_TILE_RENDERING_MODE_CONFIG.
 222         */
 223         uint32_t draw_width;
 224         uint32_t draw_height;
 225         /** @} */
 226         /** @{ Tile information, depending on MSAA and float color buffer. */
 227         uint32_t draw_tiles_x; /** @< Number of tiles wide for framebuffer. */
 228         uint32_t draw_tiles_y; /** @< Number of tiles high for framebuffer. */
 229
 230         uint32_t tile_width; /** @< Width of a tile. */
 231         uint32_t tile_height; /** @< Height of a tile. */
 232         /** maximum internal_bpp of all color render targets. */
 233         uint32_t internal_bpp;
 234
 235         /** Whether the current rendering is in a 4X MSAA tile buffer. */
 236         bool msaa;
 237         /** @} */
 238
 239         /* Bitmask of PIPE_CLEAR_* of buffers that were cleared before the
 240          * first rendering.
 241          */
 242         uint32_t cleared;
 243         /* Bitmask of PIPE_CLEAR_* of buffers that have been rendered to
 244          * (either clears or draws).
 245          */
 246         uint32_t resolve;
 247         uint32_t clear_color[2];
 248         float clear_z;
 249         uint8_t clear_s;
 250
 251         /**
 252          * Set if some drawing (triangles, blits, or just a glClear()) has
 253          * been done to the FBO, meaning that we need to
 254          * DRM_IOCTL_VC5_SUBMIT_CL.
 255          */
 256         bool needs_flush;
 257
 258         bool uses_early_z;
 259
 260         /**
 261          * Number of draw calls (not counting full buffer clears) queued in
 262          * the current job.
 263          */
 264         uint32_t draw_calls_queued;
 265
 266         struct vc5_job_key key;
 267 };
 268
 269 struct vc5_context {
 270         struct pipe_context base;
 271
 272         int fd;
 273         struct vc5_screen *screen;
 274
 275         /** The 3D rendering job for the currently bound FBO. */
 276         struct vc5_job *job;
 277
 278         /* Map from struct vc5_job_key to the job for that FBO.
 279          */
 280         struct hash_table *jobs;
 281
 282         /**
 283          * Map from vc5_resource to a job writing to that resource.
 284          *
 285          * Primarily for flushing jobs rendering to textures that are now
 286          * being read from.
 287          */
 288         struct hash_table *write_jobs;
 289
 290         struct slab_child_pool transfer_pool;
 291         struct blitter_context *blitter;
 292
 293         /** bitfield of VC5_DIRTY_* */
 294         uint32_t dirty;
 295
 296         struct primconvert_context *primconvert;
 297
 298         struct hash_table *fs_cache, *vs_cache;
 299         uint32_t next_uncompiled_program_id;
 300         uint64_t next_compiled_program_id;
 301
 302         struct vc5_compiler_state *compiler_state;
 303
 304         uint8_t prim_mode;
 305
 306         /** Maximum index buffer valid for the current shader_rec. */
 307         uint32_t max_index;
 308
 309         /** Seqno of the last CL flush's job. */
 310         uint64_t last_emit_seqno;
 311
 312         struct u_upload_mgr *uploader;
 313
 314         /** @{ Current pipeline state objects */
 315         struct pipe_scissor_state scissor;
 316         struct pipe_blend_state *blend;
 317         struct vc5_rasterizer_state *rasterizer;
 318         struct vc5_depth_stencil_alpha_state *zsa;
 319
 320         struct vc5_texture_stateobj verttex, fragtex;
 321
 322         struct vc5_program_stateobj prog;
 323
 324         struct vc5_vertex_stateobj *vtx;
 325
 326         struct {
 327                 struct pipe_blend_color f;
 328                 uint16_t hf[4];
 329         } blend_color;
 330         struct pipe_stencil_ref stencil_ref;
 331         unsigned sample_mask;
 332         struct pipe_framebuffer_state framebuffer;
 333         struct pipe_poly_stipple stipple;
 334         struct pipe_clip_state clip;
 335         struct pipe_viewport_state viewport;
 336         struct vc5_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 337         struct vc5_vertexbuf_stateobj vertexbuf;
 338         struct vc5_streamout_stateobj streamout;
 339         /** @} */
 340 };
 341
 342 struct vc5_rasterizer_state {
 343         struct pipe_rasterizer_state base;
 344
 345         /* VC5_CONFIGURATION_BITS */
 346         uint8_t config_bits[3];
 347
 348         float point_size;
 349
 350         /**
 351          * Half-float (1/8/7 bits) value of polygon offset units for
 352          * VC5_PACKET_DEPTH_OFFSET
 353          */
 354         uint16_t offset_units;
 355         /**
 356          * Half-float (1/8/7 bits) value of polygon offset scale for
 357          * VC5_PACKET_DEPTH_OFFSET
 358          */
 359         uint16_t offset_factor;
 360 };
 361
 362 struct vc5_depth_stencil_alpha_state {
 363         struct pipe_depth_stencil_alpha_state base;
 364
 365         bool early_z_enable;
 366
 367         /** Uniforms for stencil state.
 368          *
 369          * Index 0 is either the front config, or the front-and-back config.
 370          * Index 1 is the back config if doing separate back stencil.
 371          * Index 2 is the writemask config if it's not a common mask value.
 372          */
 373         uint32_t stencil_uniforms[3];
 374 };
 375
 376 #define perf_debug(...) do {                            \
 377         if (unlikely(V3D_DEBUG & V3D_DEBUG_PERF))       \
 378                 fprintf(stderr, __VA_ARGS__);           \
 379 } while (0)
 380
 381 static inline struct vc5_context *
 382 vc5_context(struct pipe_context *pcontext)
 383 {
 384         return (struct vc5_context *)pcontext;
 385 }
 386
 387 static inline struct vc5_sampler_view *
 388 vc5_sampler_view(struct pipe_sampler_view *psview)
 389 {
 390         return (struct vc5_sampler_view *)psview;
 391 }
 392
 393 static inline struct vc5_sampler_state *
 394 vc5_sampler_state(struct pipe_sampler_state *psampler)
 395 {
 396         return (struct vc5_sampler_state *)psampler;
 397 }
 398
 399 struct pipe_context *vc5_context_create(struct pipe_screen *pscreen,
 400                                         void *priv, unsigned flags);
 401 void vc5_draw_init(struct pipe_context *pctx);
 402 void vc5_state_init(struct pipe_context *pctx);
 403 void vc5_program_init(struct pipe_context *pctx);
 404 void vc5_program_fini(struct pipe_context *pctx);
 405 void vc5_query_init(struct pipe_context *pctx);
 406
 407 void vc5_simulator_init(struct vc5_screen *screen);
 408 void vc5_simulator_init(struct vc5_screen *screen);
 409 void vc5_simulator_destroy(struct vc5_screen *screen);
 410 void vc5_simulator_destroy(struct vc5_screen *screen);
 411 int vc5_simulator_flush(struct vc5_context *vc5,
 412                         struct drm_vc5_submit_cl *args,
 413                         struct vc5_job *job);
 414 int vc5_simulator_ioctl(int fd, unsigned long request, void *arg);
 415 void vc5_simulator_open_from_handle(int fd, uint32_t winsys_stride,
 416                                     int handle, uint32_t size);
 417
 418 static inline int
 419 vc5_ioctl(int fd, unsigned long request, void *arg)
 420 {
 421         if (using_vc5_simulator)
 422                 return vc5_simulator_ioctl(fd, request, arg);
 423         else
 424                 return drmIoctl(fd, request, arg);
 425 }
 426
 427 void vc5_set_shader_uniform_dirty_flags(struct vc5_compiled_shader *shader);
 428 struct vc5_cl_reloc vc5_write_uniforms(struct vc5_context *vc5,
 429                                        struct vc5_compiled_shader *shader,
 430                                        struct vc5_constbuf_stateobj *cb,
 431                                        struct vc5_texture_stateobj *texstate);
 432
 433 void vc5_flush(struct pipe_context *pctx);
 434 void vc5_job_init(struct vc5_context *vc5);
 435 struct vc5_job *vc5_get_job(struct vc5_context *vc5,
 436                             struct pipe_surface **cbufs,
 437                             struct pipe_surface *zsbuf);
 438 struct vc5_job *vc5_get_job_for_fbo(struct vc5_context *vc5);
 439 void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo);
 440 void vc5_job_submit(struct vc5_context *vc5, struct vc5_job *job);
 441 void vc5_flush_jobs_writing_resource(struct vc5_context *vc5,
 442                                      struct pipe_resource *prsc);
 443 void vc5_flush_jobs_reading_resource(struct vc5_context *vc5,
 444                                      struct pipe_resource *prsc);
 445 void vc5_emit_state(struct pipe_context *pctx);
 446 void vc5_update_compiled_shaders(struct vc5_context *vc5, uint8_t prim_mode);
 447
 448 bool vc5_rt_format_supported(enum pipe_format f);
 449 bool vc5_tex_format_supported(enum pipe_format f);
 450 uint8_t vc5_get_rt_format(enum pipe_format f);
 451 uint8_t vc5_get_tex_format(enum pipe_format f);
 452 uint8_t vc5_get_tex_return_size(enum pipe_format f);
 453 uint8_t vc5_get_tex_return_channels(enum pipe_format f);
 454 const uint8_t *vc5_get_format_swizzle(enum pipe_format f);
 455 void vc5_get_internal_type_bpp_for_output_format(uint32_t format,
 456                                                  uint32_t *type,
 457                                                  uint32_t *bpp);
 458
 459 void vc5_init_query_functions(struct vc5_context *vc5);
 460 void vc5_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info);
 461 void vc5_blitter_save(struct vc5_context *vc5);
 462 void vc5_emit_rcl(struct vc5_job *job);
 463
 464
 465 #endif /* VC5_CONTEXT_H */