src/gallium/drivers/vc5/vc5_draw.c

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/u_blitter.h"
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "util/u_prim_restart.h"
  29 #include "util/u_upload_mgr.h"
  30 #include "indices/u_primconvert.h"
  31
  32 #include "vc5_context.h"
  33 #include "vc5_resource.h"
  34 #include "vc5_cl.h"
  35 #include "broadcom/cle/v3d_packet_v33_pack.h"
  36 #include "broadcom/compiler/v3d_compiler.h"
  37
  38 /**
  39  * Does the initial bining command list setup for drawing to a given FBO.
  40  */
  41 static void
  42 vc5_start_draw(struct vc5_context *vc5)
  43 {
  44         struct vc5_job *job = vc5->job;
  45
  46         if (job->needs_flush)
  47                 return;
  48
  49         /* Get space to emit our BCL state, using a branch to jump to a new BO
  50          * if necessary.
  51          */
  52         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
  53
  54         job->submit.bcl_start = job->bcl.bo->offset;
  55         vc5_job_add_bo(job, job->bcl.bo);
  56
  57         job->tile_alloc = vc5_bo_alloc(vc5->screen, 1024 * 1024, "tile alloc");
  58         struct vc5_bo *tsda = vc5_bo_alloc(vc5->screen,
  59                                            job->draw_tiles_y *
  60                                            job->draw_tiles_x *
  61                                            64,
  62                                            "TSDA");
  63
  64         /* "Binning mode lists start with a Tile Binning Mode Configuration
  65          * item (120)"
  66          *
  67          * Part1 signals the end of binning config setup.
  68          */
  69         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART2, config) {
  70                 config.tile_allocation_memory_address =
  71                         cl_address(job->tile_alloc, 0);
  72                 config.tile_allocation_memory_size = job->tile_alloc->size;
  73         }
  74
  75         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART1, config) {
  76                 config.tile_state_data_array_base_address =
  77                         cl_address(tsda, 0);
  78
  79                 config.width_in_tiles = job->draw_tiles_x;
  80                 config.height_in_tiles = job->draw_tiles_y;
  81
  82                 /* Must be >= 1 */
  83                 config.number_of_render_targets =
  84                         MAX2(vc5->framebuffer.nr_cbufs, 1);
  85
  86                 config.multisample_mode_4x = job->msaa;
  87
  88                 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
  89         }
  90
  91         vc5_bo_unreference(&tsda);
  92
  93         /* There's definitely nothing in the VCD cache we want. */
  94         cl_emit(&job->bcl, FLUSH_VCD_CACHE, bin);
  95
  96         /* "Binning mode lists must have a Start Tile Binning item (6) after
  97          *  any prefix state data before the binning list proper starts."
  98          */
  99         cl_emit(&job->bcl, START_TILE_BINNING, bin);
 100
 101         cl_emit(&job->bcl, PRIMITIVE_LIST_FORMAT, fmt) {
 102                 fmt.data_type = LIST_INDEXED;
 103                 fmt.primitive_type = LIST_TRIANGLES;
 104         }
 105
 106         job->needs_flush = true;
 107         job->draw_width = vc5->framebuffer.width;
 108         job->draw_height = vc5->framebuffer.height;
 109 }
 110
 111 static void
 112 vc5_predraw_check_textures(struct pipe_context *pctx,
 113                            struct vc5_texture_stateobj *stage_tex)
 114 {
 115         struct vc5_context *vc5 = vc5_context(pctx);
 116
 117         for (int i = 0; i < stage_tex->num_textures; i++) {
 118                 struct pipe_sampler_view *view = stage_tex->textures[i];
 119                 if (!view)
 120                         continue;
 121
 122                 vc5_flush_jobs_writing_resource(vc5, view->texture);
 123         }
 124 }
 125
 126 static void
 127 vc5_emit_gl_shader_state(struct vc5_context *vc5,
 128                          const struct pipe_draw_info *info)
 129 {
 130         struct vc5_job *job = vc5->job;
 131         /* VC5_DIRTY_VTXSTATE */
 132         struct vc5_vertex_stateobj *vtx = vc5->vtx;
 133         /* VC5_DIRTY_VTXBUF */
 134         struct vc5_vertexbuf_stateobj *vertexbuf = &vc5->vertexbuf;
 135
 136         /* Upload the uniforms to the indirect CL first */
 137         struct vc5_cl_reloc fs_uniforms =
 138                 vc5_write_uniforms(vc5, vc5->prog.fs,
 139                                    &vc5->constbuf[PIPE_SHADER_FRAGMENT],
 140                                    &vc5->fragtex);
 141         struct vc5_cl_reloc vs_uniforms =
 142                 vc5_write_uniforms(vc5, vc5->prog.vs,
 143                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 144                                    &vc5->verttex);
 145         struct vc5_cl_reloc cs_uniforms =
 146                 vc5_write_uniforms(vc5, vc5->prog.cs,
 147                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 148                                    &vc5->verttex);
 149
 150         uint32_t shader_rec_offset =
 151                 vc5_cl_ensure_space(&job->indirect,
 152                                     cl_packet_length(GL_SHADER_STATE_RECORD) +
 153                                     vtx->num_elements *
 154                                     cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD),
 155                                     32);
 156
 157         cl_emit(&job->indirect, GL_SHADER_STATE_RECORD, shader) {
 158                 shader.enable_clipping = true;
 159                 /* VC5_DIRTY_PRIM_MODE | VC5_DIRTY_RASTERIZER */
 160                 shader.point_size_in_shaded_vertex_data =
 161                         (info->mode == PIPE_PRIM_POINTS &&
 162                          vc5->rasterizer->base.point_size_per_vertex);
 163
 164                 /* Must be set if the shader modifies Z, discards, or modifies
 165                  * the sample mask.  For any of these cases, the fragment
 166                  * shader needs to write the Z value (even just discards).
 167                  */
 168                 shader.fragment_shader_does_z_writes =
 169                         (vc5->prog.fs->prog_data.fs->writes_z ||
 170                          vc5->prog.fs->prog_data.fs->discard);
 171
 172                 shader.number_of_varyings_in_fragment_shader =
 173                         vc5->prog.fs->prog_data.base->num_inputs;
 174
 175                 shader.propagate_nans = true;
 176
 177                 shader.coordinate_shader_code_address =
 178                         cl_address(vc5->prog.cs->bo, 0);
 179                 shader.vertex_shader_code_address =
 180                         cl_address(vc5->prog.vs->bo, 0);
 181                 shader.fragment_shader_code_address =
 182                         cl_address(vc5->prog.fs->bo, 0);
 183
 184                 /* XXX: Use combined input/output size flag in the common
 185                  * case.
 186                  */
 187                 shader.coordinate_shader_has_separate_input_and_output_vpm_blocks = true;
 188                 shader.vertex_shader_has_separate_input_and_output_vpm_blocks = true;
 189                 shader.coordinate_shader_input_vpm_segment_size =
 190                         vc5->prog.cs->prog_data.vs->vpm_input_size;
 191                 shader.vertex_shader_input_vpm_segment_size =
 192                         vc5->prog.vs->prog_data.vs->vpm_input_size;
 193
 194                 shader.coordinate_shader_output_vpm_segment_size =
 195                         vc5->prog.cs->prog_data.vs->vpm_output_size;
 196                 shader.vertex_shader_output_vpm_segment_size =
 197                         vc5->prog.vs->prog_data.vs->vpm_output_size;
 198
 199                 shader.coordinate_shader_uniforms_address = cs_uniforms;
 200                 shader.vertex_shader_uniforms_address = vs_uniforms;
 201                 shader.fragment_shader_uniforms_address = fs_uniforms;
 202
 203                 shader.vertex_id_read_by_coordinate_shader =
 204                         vc5->prog.cs->prog_data.vs->uses_vid;
 205                 shader.instance_id_read_by_coordinate_shader =
 206                         vc5->prog.cs->prog_data.vs->uses_iid;
 207                 shader.vertex_id_read_by_vertex_shader =
 208                         vc5->prog.vs->prog_data.vs->uses_vid;
 209                 shader.instance_id_read_by_vertex_shader =
 210                         vc5->prog.vs->prog_data.vs->uses_iid;
 211
 212                 shader.address_of_default_attribute_values =
 213                         cl_address(vtx->default_attribute_values, 0);
 214         }
 215
 216         for (int i = 0; i < vtx->num_elements; i++) {
 217                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 218                 struct pipe_vertex_buffer *vb =
 219                         &vertexbuf->vb[elem->vertex_buffer_index];
 220                 struct vc5_resource *rsc = vc5_resource(vb->buffer.resource);
 221
 222                 struct V3D33_GL_SHADER_STATE_ATTRIBUTE_RECORD attr_unpacked = {
 223                         .stride = vb->stride,
 224                         .address = cl_address(rsc->bo,
 225                                               vb->buffer_offset +
 226                                               elem->src_offset),
 227                         .number_of_values_read_by_coordinate_shader =
 228                                 vc5->prog.cs->prog_data.vs->vattr_sizes[i],
 229                         .number_of_values_read_by_vertex_shader =
 230                                 vc5->prog.vs->prog_data.vs->vattr_sizes[i],
 231                 };
 232                 const uint32_t size =
 233                         cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD);
 234                 uint8_t attr_packed[size];
 235                 V3D33_GL_SHADER_STATE_ATTRIBUTE_RECORD_pack(&job->indirect,
 236                                                             attr_packed,
 237                                                             &attr_unpacked);
 238                 for (int j = 0; j < size; j++)
 239                         attr_packed[j] |= vtx->attrs[i * size + j];
 240                 cl_emit_prepacked(&job->indirect, &attr_packed);
 241         }
 242
 243         cl_emit(&job->bcl, GL_SHADER_STATE, state) {
 244                 state.address = cl_address(job->indirect.bo, shader_rec_offset);
 245                 state.number_of_attribute_arrays = vtx->num_elements;
 246         }
 247
 248         vc5_bo_unreference(&cs_uniforms.bo);
 249         vc5_bo_unreference(&vs_uniforms.bo);
 250         vc5_bo_unreference(&fs_uniforms.bo);
 251
 252         job->shader_rec_count++;
 253 }
 254
 255 static void
 256 vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 257 {
 258         struct vc5_context *vc5 = vc5_context(pctx);
 259
 260         if (!info->count_from_stream_output && !info->indirect &&
 261             !info->primitive_restart &&
 262             !u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
 263                 return;
 264
 265         /* Fall back for weird desktop GL primitive restart values. */
 266         if (info->primitive_restart &&
 267             info->index_size) {
 268                 uint32_t mask = ~0;
 269
 270                 switch (info->index_size) {
 271                 case 2:
 272                         mask = 0xffff;
 273                         break;
 274                 case 1:
 275                         mask = 0xff;
 276                         break;
 277                 }
 278
 279                 if (info->restart_index != mask) {
 280                         util_draw_vbo_without_prim_restart(pctx, info);
 281                         return;
 282                 }
 283         }
 284
 285         if (info->mode >= PIPE_PRIM_QUADS) {
 286                 util_primconvert_save_rasterizer_state(vc5->primconvert, &vc5->rasterizer->base);
 287                 util_primconvert_draw_vbo(vc5->primconvert, info);
 288                 perf_debug("Fallback conversion for %d %s vertices\n",
 289                            info->count, u_prim_name(info->mode));
 290                 return;
 291         }
 292
 293         /* Before setting up the draw, flush anything writing to the textures
 294          * that we read from.
 295          */
 296         vc5_predraw_check_textures(pctx, &vc5->verttex);
 297         vc5_predraw_check_textures(pctx, &vc5->fragtex);
 298
 299         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 300
 301         /* Get space to emit our draw call into the BCL, using a branch to
 302          * jump to a new BO if necessary.
 303          */
 304         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
 305
 306         if (vc5->prim_mode != info->mode) {
 307                 vc5->prim_mode = info->mode;
 308                 vc5->dirty |= VC5_DIRTY_PRIM_MODE;
 309         }
 310
 311         vc5_start_draw(vc5);
 312         vc5_update_compiled_shaders(vc5, info->mode);
 313
 314         vc5_emit_state(pctx);
 315
 316         if (vc5->dirty & (VC5_DIRTY_VTXBUF |
 317                           VC5_DIRTY_VTXSTATE |
 318                           VC5_DIRTY_PRIM_MODE |
 319                           VC5_DIRTY_RASTERIZER |
 320                           VC5_DIRTY_COMPILED_CS |
 321                           VC5_DIRTY_COMPILED_VS |
 322                           VC5_DIRTY_COMPILED_FS |
 323                           vc5->prog.cs->uniform_dirty_bits |
 324                           vc5->prog.vs->uniform_dirty_bits |
 325                           vc5->prog.fs->uniform_dirty_bits)) {
 326                 vc5_emit_gl_shader_state(vc5, info);
 327         }
 328
 329         vc5->dirty = 0;
 330
 331         /* The Base Vertex/Base Instance packet sets those values to nonzero
 332          * for the next draw call only.
 333          */
 334         if (info->index_bias || info->start_instance) {
 335                 cl_emit(&job->bcl, BASE_VERTEX_BASE_INSTANCE, base) {
 336                         base.base_instance = info->start_instance;
 337                         base.base_vertex = info->index_bias;
 338                 }
 339         }
 340
 341         /* The HW only processes transform feedback on primitives with the
 342          * flag set.
 343          */
 344         uint32_t prim_tf_enable = 0;
 345         if (vc5->prog.bind_vs->num_tf_outputs)
 346                 prim_tf_enable = (V3D_PRIM_POINTS_TF - V3D_PRIM_POINTS);
 347
 348         /* Note that the primitive type fields match with OpenGL/gallium
 349          * definitions, up to but not including QUADS.
 350          */
 351         if (info->index_size) {
 352                 uint32_t index_size = info->index_size;
 353                 uint32_t offset = info->start * index_size;
 354                 struct pipe_resource *prsc;
 355                 if (info->has_user_indices) {
 356                         prsc = NULL;
 357                         u_upload_data(vc5->uploader, 0,
 358                                       info->count * info->index_size, 4,
 359                                       info->index.user,
 360                                       &offset, &prsc);
 361                 } else {
 362                         prsc = info->index.resource;
 363                 }
 364                 struct vc5_resource *rsc = vc5_resource(prsc);
 365
 366                 if (info->instance_count > 1) {
 367                         cl_emit(&job->bcl, INDEXED_INSTANCED_PRIMITIVE_LIST, prim) {
 368                                 prim.index_type = ffs(info->index_size) - 1;
 369                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 370                                 prim.address_of_indices_list =
 371                                         cl_address(rsc->bo, offset);
 372                                 prim.mode = info->mode | prim_tf_enable;
 373                                 prim.enable_primitive_restarts = info->primitive_restart;
 374
 375                                 prim.number_of_instances = info->instance_count;
 376                                 prim.instance_length = info->count;
 377                         }
 378                 } else {
 379                         cl_emit(&job->bcl, INDEXED_PRIMITIVE_LIST, prim) {
 380                                 prim.index_type = ffs(info->index_size) - 1;
 381                                 prim.length = info->count;
 382                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 383                                 prim.address_of_indices_list =
 384                                         cl_address(rsc->bo, offset);
 385                                 prim.mode = info->mode | prim_tf_enable;
 386                                 prim.enable_primitive_restarts = info->primitive_restart;
 387                         }
 388                 }
 389
 390                 job->draw_calls_queued++;
 391
 392                 if (info->has_user_indices)
 393                         pipe_resource_reference(&prsc, NULL);
 394         } else {
 395                 if (info->instance_count > 1) {
 396                         cl_emit(&job->bcl, VERTEX_ARRAY_INSTANCED_PRIMITIVES, prim) {
 397                                 prim.mode = info->mode | prim_tf_enable;
 398                                 prim.index_of_first_vertex = info->start;
 399                                 prim.number_of_instances = info->instance_count;
 400                                 prim.instance_length = info->count;
 401                         }
 402                 } else {
 403                         cl_emit(&job->bcl, VERTEX_ARRAY_PRIMITIVES, prim) {
 404                                 prim.mode = info->mode | prim_tf_enable;
 405                                 prim.length = info->count;
 406                                 prim.index_of_first_vertex = info->start;
 407                         }
 408                 }
 409         }
 410         job->draw_calls_queued++;
 411
 412         if (vc5->zsa && job->zsbuf &&
 413             (vc5->zsa->base.depth.enabled ||
 414              vc5->zsa->base.stencil[0].enabled)) {
 415                 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
 416                 vc5_job_add_bo(job, rsc->bo);
 417
 418                 if (vc5->zsa->base.depth.enabled) {
 419                         job->resolve |= PIPE_CLEAR_DEPTH;
 420                         rsc->initialized_buffers = PIPE_CLEAR_DEPTH;
 421
 422                         if (vc5->zsa->early_z_enable)
 423                                 job->uses_early_z = true;
 424                 }
 425
 426                 if (vc5->zsa->base.stencil[0].enabled) {
 427                         job->resolve |= PIPE_CLEAR_STENCIL;
 428                         rsc->initialized_buffers |= PIPE_CLEAR_STENCIL;
 429                 }
 430         }
 431
 432         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 433                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 434
 435                 if (job->resolve & bit || !job->cbufs[i])
 436                         continue;
 437                 struct vc5_resource *rsc = vc5_resource(job->cbufs[i]->texture);
 438
 439                 job->resolve |= bit;
 440                 vc5_job_add_bo(job, rsc->bo);
 441         }
 442
 443         if (V3D_DEBUG & V3D_DEBUG_ALWAYS_FLUSH)
 444                 vc5_flush(pctx);
 445 }
 446
 447 static void
 448 vc5_clear(struct pipe_context *pctx, unsigned buffers,
 449           const union pipe_color_union *color, double depth, unsigned stencil)
 450 {
 451         struct vc5_context *vc5 = vc5_context(pctx);
 452         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 453
 454         /* We can't flag new buffers for clearing once we've queued draws.  We
 455          * could avoid this by using the 3d engine to clear.
 456          */
 457         if (job->draw_calls_queued) {
 458                 perf_debug("Flushing rendering to process new clear.\n");
 459                 vc5_job_submit(vc5, job);
 460                 job = vc5_get_job_for_fbo(vc5);
 461         }
 462
 463         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 464                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 465                 if (!(buffers & bit))
 466                         continue;
 467
 468                 struct pipe_surface *cbuf = vc5->framebuffer.cbufs[i];
 469                 struct vc5_resource *rsc =
 470                         vc5_resource(cbuf->texture);
 471
 472                 union util_color uc;
 473                 util_pack_color(color->f, cbuf->format, &uc);
 474
 475                 memcpy(job->clear_color[i], uc.ui,
 476                        util_format_get_blocksize(cbuf->format));
 477
 478                 rsc->initialized_buffers |= bit;
 479         }
 480
 481         unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
 482         if (zsclear) {
 483                 struct vc5_resource *rsc =
 484                         vc5_resource(vc5->framebuffer.zsbuf->texture);
 485
 486                 if (zsclear & PIPE_CLEAR_DEPTH)
 487                         job->clear_z = depth;
 488                 if (zsclear & PIPE_CLEAR_STENCIL)
 489                         job->clear_s = stencil;
 490
 491                 rsc->initialized_buffers |= zsclear;
 492         }
 493
 494         job->draw_min_x = 0;
 495         job->draw_min_y = 0;
 496         job->draw_max_x = vc5->framebuffer.width;
 497         job->draw_max_y = vc5->framebuffer.height;
 498         job->cleared |= buffers;
 499         job->resolve |= buffers;
 500
 501         vc5_start_draw(vc5);
 502 }
 503
 504 static void
 505 vc5_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 506                         const union pipe_color_union *color,
 507                         unsigned x, unsigned y, unsigned w, unsigned h,
 508                         bool render_condition_enabled)
 509 {
 510         fprintf(stderr, "unimpl: clear RT\n");
 511 }
 512
 513 static void
 514 vc5_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 515                         unsigned buffers, double depth, unsigned stencil,
 516                         unsigned x, unsigned y, unsigned w, unsigned h,
 517                         bool render_condition_enabled)
 518 {
 519         fprintf(stderr, "unimpl: clear DS\n");
 520 }
 521
 522 void
 523 vc5_draw_init(struct pipe_context *pctx)
 524 {
 525         pctx->draw_vbo = vc5_draw_vbo;
 526         pctx->clear = vc5_clear;
 527         pctx->clear_render_target = vc5_clear_render_target;
 528         pctx->clear_depth_stencil = vc5_clear_depth_stencil;
 529 }