src/gallium/drivers/vc5/vc5_draw.c

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/u_blitter.h"
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "util/u_prim_restart.h"
  29 #include "util/u_upload_mgr.h"
  30 #include "indices/u_primconvert.h"
  31
  32 #include "vc5_context.h"
  33 #include "vc5_resource.h"
  34 #include "vc5_cl.h"
  35 #include "broadcom/cle/v3d_packet_v33_pack.h"
  36 #include "broadcom/compiler/v3d_compiler.h"
  37
  38 /**
  39  * Does the initial bining command list setup for drawing to a given FBO.
  40  */
  41 static void
  42 vc5_start_draw(struct vc5_context *vc5)
  43 {
  44         struct vc5_job *job = vc5->job;
  45
  46         if (job->needs_flush)
  47                 return;
  48
  49         /* Get space to emit our BCL state, using a branch to jump to a new BO
  50          * if necessary.
  51          */
  52         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
  53
  54         job->submit.bcl_start = job->bcl.bo->offset;
  55         vc5_job_add_bo(job, job->bcl.bo);
  56
  57         job->tile_alloc = vc5_bo_alloc(vc5->screen, 1024 * 1024, "tile alloc");
  58         struct vc5_bo *tsda = vc5_bo_alloc(vc5->screen,
  59                                            job->draw_tiles_y *
  60                                            job->draw_tiles_x *
  61                                            64,
  62                                            "TSDA");
  63
  64         /* "Binning mode lists start with a Tile Binning Mode Configuration
  65          * item (120)"
  66          *
  67          * Part1 signals the end of binning config setup.
  68          */
  69         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART2, config) {
  70                 config.tile_allocation_memory_address =
  71                         cl_address(job->tile_alloc, 0);
  72                 config.tile_allocation_memory_size = job->tile_alloc->size;
  73         }
  74
  75         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART1, config) {
  76                 config.tile_state_data_array_base_address =
  77                         cl_address(tsda, 0);
  78
  79                 config.width_in_tiles = job->draw_tiles_x;
  80                 config.height_in_tiles = job->draw_tiles_y;
  81
  82                 /* Must be >= 1 */
  83                 config.number_of_render_targets =
  84                         MAX2(vc5->framebuffer.nr_cbufs, 1);
  85
  86                 config.multisample_mode_4x = job->msaa;
  87
  88                 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
  89         }
  90
  91         vc5_bo_unreference(&tsda);
  92
  93         /* There's definitely nothing in the VCD cache we want. */
  94         cl_emit(&job->bcl, FLUSH_VCD_CACHE, bin);
  95
  96         /* Disable any leftover OQ state from another job. */
  97         cl_emit(&job->bcl, OCCLUSION_QUERY_COUNTER, counter);
  98
  99         /* "Binning mode lists must have a Start Tile Binning item (6) after
 100          *  any prefix state data before the binning list proper starts."
 101          */
 102         cl_emit(&job->bcl, START_TILE_BINNING, bin);
 103
 104         job->needs_flush = true;
 105         job->draw_width = vc5->framebuffer.width;
 106         job->draw_height = vc5->framebuffer.height;
 107 }
 108
 109 static void
 110 vc5_predraw_check_textures(struct pipe_context *pctx,
 111                            struct vc5_texture_stateobj *stage_tex)
 112 {
 113         struct vc5_context *vc5 = vc5_context(pctx);
 114
 115         for (int i = 0; i < stage_tex->num_textures; i++) {
 116                 struct pipe_sampler_view *view = stage_tex->textures[i];
 117                 if (!view)
 118                         continue;
 119
 120                 vc5_flush_jobs_writing_resource(vc5, view->texture);
 121         }
 122 }
 123
 124 static void
 125 vc5_emit_gl_shader_state(struct vc5_context *vc5,
 126                          const struct pipe_draw_info *info)
 127 {
 128         struct vc5_job *job = vc5->job;
 129         /* VC5_DIRTY_VTXSTATE */
 130         struct vc5_vertex_stateobj *vtx = vc5->vtx;
 131         /* VC5_DIRTY_VTXBUF */
 132         struct vc5_vertexbuf_stateobj *vertexbuf = &vc5->vertexbuf;
 133
 134         /* Upload the uniforms to the indirect CL first */
 135         struct vc5_cl_reloc fs_uniforms =
 136                 vc5_write_uniforms(vc5, vc5->prog.fs,
 137                                    &vc5->constbuf[PIPE_SHADER_FRAGMENT],
 138                                    &vc5->fragtex);
 139         struct vc5_cl_reloc vs_uniforms =
 140                 vc5_write_uniforms(vc5, vc5->prog.vs,
 141                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 142                                    &vc5->verttex);
 143         struct vc5_cl_reloc cs_uniforms =
 144                 vc5_write_uniforms(vc5, vc5->prog.cs,
 145                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 146                                    &vc5->verttex);
 147
 148         /* See GFXH-930 workaround below */
 149         uint32_t num_elements_to_emit = MAX2(vtx->num_elements, 1);
 150         uint32_t shader_rec_offset =
 151                 vc5_cl_ensure_space(&job->indirect,
 152                                     cl_packet_length(GL_SHADER_STATE_RECORD) +
 153                                     num_elements_to_emit *
 154                                     cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD),
 155                                     32);
 156
 157         cl_emit(&job->indirect, GL_SHADER_STATE_RECORD, shader) {
 158                 shader.enable_clipping = true;
 159                 /* VC5_DIRTY_PRIM_MODE | VC5_DIRTY_RASTERIZER */
 160                 shader.point_size_in_shaded_vertex_data =
 161                         (info->mode == PIPE_PRIM_POINTS &&
 162                          vc5->rasterizer->base.point_size_per_vertex);
 163
 164                 /* Must be set if the shader modifies Z, discards, or modifies
 165                  * the sample mask.  For any of these cases, the fragment
 166                  * shader needs to write the Z value (even just discards).
 167                  */
 168                 shader.fragment_shader_does_z_writes =
 169                         (vc5->prog.fs->prog_data.fs->writes_z ||
 170                          vc5->prog.fs->prog_data.fs->discard);
 171
 172                 shader.number_of_varyings_in_fragment_shader =
 173                         vc5->prog.fs->prog_data.base->num_inputs;
 174
 175                 shader.propagate_nans = true;
 176
 177                 shader.coordinate_shader_code_address =
 178                         cl_address(vc5->prog.cs->bo, 0);
 179                 shader.vertex_shader_code_address =
 180                         cl_address(vc5->prog.vs->bo, 0);
 181                 shader.fragment_shader_code_address =
 182                         cl_address(vc5->prog.fs->bo, 0);
 183
 184                 /* XXX: Use combined input/output size flag in the common
 185                  * case.
 186                  */
 187                 shader.coordinate_shader_has_separate_input_and_output_vpm_blocks = true;
 188                 shader.vertex_shader_has_separate_input_and_output_vpm_blocks = true;
 189                 shader.coordinate_shader_input_vpm_segment_size =
 190                         MAX2(vc5->prog.cs->prog_data.vs->vpm_input_size, 1);
 191                 shader.vertex_shader_input_vpm_segment_size =
 192                         MAX2(vc5->prog.vs->prog_data.vs->vpm_input_size, 1);
 193
 194                 shader.coordinate_shader_output_vpm_segment_size =
 195                         vc5->prog.cs->prog_data.vs->vpm_output_size;
 196                 shader.vertex_shader_output_vpm_segment_size =
 197                         vc5->prog.vs->prog_data.vs->vpm_output_size;
 198
 199                 shader.coordinate_shader_uniforms_address = cs_uniforms;
 200                 shader.vertex_shader_uniforms_address = vs_uniforms;
 201                 shader.fragment_shader_uniforms_address = fs_uniforms;
 202
 203                 shader.vertex_id_read_by_coordinate_shader =
 204                         vc5->prog.cs->prog_data.vs->uses_vid;
 205                 shader.instance_id_read_by_coordinate_shader =
 206                         vc5->prog.cs->prog_data.vs->uses_iid;
 207                 shader.vertex_id_read_by_vertex_shader =
 208                         vc5->prog.vs->prog_data.vs->uses_vid;
 209                 shader.instance_id_read_by_vertex_shader =
 210                         vc5->prog.vs->prog_data.vs->uses_iid;
 211
 212                 shader.address_of_default_attribute_values =
 213                         cl_address(vtx->default_attribute_values, 0);
 214         }
 215
 216         for (int i = 0; i < vtx->num_elements; i++) {
 217                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 218                 struct pipe_vertex_buffer *vb =
 219                         &vertexbuf->vb[elem->vertex_buffer_index];
 220                 struct vc5_resource *rsc = vc5_resource(vb->buffer.resource);
 221
 222                 const uint32_t size =
 223                         cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD);
 224                 cl_emit_with_prepacked(&job->indirect,
 225                                        GL_SHADER_STATE_ATTRIBUTE_RECORD,
 226                                        &vtx->attrs[i * size], attr) {
 227                         attr.stride = vb->stride;
 228                         attr.address = cl_address(rsc->bo,
 229                                                   vb->buffer_offset +
 230                                                   elem->src_offset);
 231                         attr.number_of_values_read_by_coordinate_shader =
 232                                 vc5->prog.cs->prog_data.vs->vattr_sizes[i];
 233                         attr.number_of_values_read_by_vertex_shader =
 234                                 vc5->prog.vs->prog_data.vs->vattr_sizes[i];
 235                 }
 236         }
 237
 238         if (vtx->num_elements == 0) {
 239                 /* GFXH-930: At least one attribute must be enabled and read
 240                  * by CS and VS.  If we have no attributes being consumed by
 241                  * the shader, set up a dummy to be loaded into the VPM.
 242                  */
 243                 cl_emit(&job->indirect, GL_SHADER_STATE_ATTRIBUTE_RECORD, attr) {
 244                         /* Valid address of data whose value will be unused. */
 245                         attr.address = cl_address(job->indirect.bo, 0);
 246
 247                         attr.type = ATTRIBUTE_FLOAT;
 248                         attr.stride = 0;
 249                         attr.vec_size = 1;
 250
 251                         attr.number_of_values_read_by_coordinate_shader = 1;
 252                         attr.number_of_values_read_by_vertex_shader = 1;
 253                 }
 254         }
 255
 256         cl_emit(&job->bcl, GL_SHADER_STATE, state) {
 257                 state.address = cl_address(job->indirect.bo, shader_rec_offset);
 258                 state.number_of_attribute_arrays = num_elements_to_emit;
 259         }
 260
 261         vc5_bo_unreference(&cs_uniforms.bo);
 262         vc5_bo_unreference(&vs_uniforms.bo);
 263         vc5_bo_unreference(&fs_uniforms.bo);
 264
 265         job->shader_rec_count++;
 266 }
 267
 268 /**
 269  * Computes the various transform feedback statistics, since they can't be
 270  * recorded by CL packets.
 271  */
 272 static void
 273 vc5_tf_statistics_record(struct vc5_context *vc5,
 274                          const struct pipe_draw_info *info,
 275                          bool prim_tf)
 276 {
 277         if (!vc5->active_queries)
 278                 return;
 279
 280         uint32_t prims = u_prims_for_vertices(info->mode, info->count);
 281         vc5->prims_generated += prims;
 282
 283         if (prim_tf) {
 284                 /* XXX: Only count if we didn't overflow. */
 285                 vc5->tf_prims_generated += prims;
 286         }
 287 }
 288
 289 static void
 290 vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 291 {
 292         struct vc5_context *vc5 = vc5_context(pctx);
 293
 294         if (!info->count_from_stream_output && !info->indirect &&
 295             !info->primitive_restart &&
 296             !u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
 297                 return;
 298
 299         /* Fall back for weird desktop GL primitive restart values. */
 300         if (info->primitive_restart &&
 301             info->index_size) {
 302                 uint32_t mask = ~0;
 303
 304                 switch (info->index_size) {
 305                 case 2:
 306                         mask = 0xffff;
 307                         break;
 308                 case 1:
 309                         mask = 0xff;
 310                         break;
 311                 }
 312
 313                 if (info->restart_index != mask) {
 314                         util_draw_vbo_without_prim_restart(pctx, info);
 315                         return;
 316                 }
 317         }
 318
 319         if (info->mode >= PIPE_PRIM_QUADS) {
 320                 util_primconvert_save_rasterizer_state(vc5->primconvert, &vc5->rasterizer->base);
 321                 util_primconvert_draw_vbo(vc5->primconvert, info);
 322                 perf_debug("Fallback conversion for %d %s vertices\n",
 323                            info->count, u_prim_name(info->mode));
 324                 return;
 325         }
 326
 327         /* Before setting up the draw, flush anything writing to the textures
 328          * that we read from.
 329          */
 330         vc5_predraw_check_textures(pctx, &vc5->verttex);
 331         vc5_predraw_check_textures(pctx, &vc5->fragtex);
 332
 333         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 334
 335         /* Get space to emit our draw call into the BCL, using a branch to
 336          * jump to a new BO if necessary.
 337          */
 338         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
 339
 340         if (vc5->prim_mode != info->mode) {
 341                 vc5->prim_mode = info->mode;
 342                 vc5->dirty |= VC5_DIRTY_PRIM_MODE;
 343         }
 344
 345         vc5_start_draw(vc5);
 346         vc5_update_compiled_shaders(vc5, info->mode);
 347
 348         vc5_emit_state(pctx);
 349
 350         if (vc5->dirty & (VC5_DIRTY_VTXBUF |
 351                           VC5_DIRTY_VTXSTATE |
 352                           VC5_DIRTY_PRIM_MODE |
 353                           VC5_DIRTY_RASTERIZER |
 354                           VC5_DIRTY_COMPILED_CS |
 355                           VC5_DIRTY_COMPILED_VS |
 356                           VC5_DIRTY_COMPILED_FS |
 357                           vc5->prog.cs->uniform_dirty_bits |
 358                           vc5->prog.vs->uniform_dirty_bits |
 359                           vc5->prog.fs->uniform_dirty_bits)) {
 360                 vc5_emit_gl_shader_state(vc5, info);
 361         }
 362
 363         vc5->dirty = 0;
 364
 365         /* The Base Vertex/Base Instance packet sets those values to nonzero
 366          * for the next draw call only.
 367          */
 368         if (info->index_bias || info->start_instance) {
 369                 cl_emit(&job->bcl, BASE_VERTEX_BASE_INSTANCE, base) {
 370                         base.base_instance = info->start_instance;
 371                         base.base_vertex = info->index_bias;
 372                 }
 373         }
 374
 375         /* The HW only processes transform feedback on primitives with the
 376          * flag set.
 377          */
 378         uint32_t prim_tf_enable = 0;
 379         if (vc5->streamout.num_targets)
 380                 prim_tf_enable = (V3D_PRIM_POINTS_TF - V3D_PRIM_POINTS);
 381
 382         vc5_tf_statistics_record(vc5, info, prim_tf_enable);
 383
 384         /* Note that the primitive type fields match with OpenGL/gallium
 385          * definitions, up to but not including QUADS.
 386          */
 387         if (info->index_size) {
 388                 uint32_t index_size = info->index_size;
 389                 uint32_t offset = info->start * index_size;
 390                 struct pipe_resource *prsc;
 391                 if (info->has_user_indices) {
 392                         prsc = NULL;
 393                         u_upload_data(vc5->uploader, 0,
 394                                       info->count * info->index_size, 4,
 395                                       info->index.user,
 396                                       &offset, &prsc);
 397                 } else {
 398                         prsc = info->index.resource;
 399                 }
 400                 struct vc5_resource *rsc = vc5_resource(prsc);
 401
 402                 if (info->instance_count > 1) {
 403                         cl_emit(&job->bcl, INDEXED_INSTANCED_PRIMITIVE_LIST, prim) {
 404                                 prim.index_type = ffs(info->index_size) - 1;
 405                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 406                                 prim.address_of_indices_list =
 407                                         cl_address(rsc->bo, offset);
 408                                 prim.mode = info->mode | prim_tf_enable;
 409                                 prim.enable_primitive_restarts = info->primitive_restart;
 410
 411                                 prim.number_of_instances = info->instance_count;
 412                                 prim.instance_length = info->count;
 413                         }
 414                 } else {
 415                         cl_emit(&job->bcl, INDEXED_PRIMITIVE_LIST, prim) {
 416                                 prim.index_type = ffs(info->index_size) - 1;
 417                                 prim.length = info->count;
 418                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 419                                 prim.address_of_indices_list =
 420                                         cl_address(rsc->bo, offset);
 421                                 prim.mode = info->mode | prim_tf_enable;
 422                                 prim.enable_primitive_restarts = info->primitive_restart;
 423                         }
 424                 }
 425
 426                 job->draw_calls_queued++;
 427
 428                 if (info->has_user_indices)
 429                         pipe_resource_reference(&prsc, NULL);
 430         } else {
 431                 if (info->instance_count > 1) {
 432                         cl_emit(&job->bcl, VERTEX_ARRAY_INSTANCED_PRIMITIVES, prim) {
 433                                 prim.mode = info->mode | prim_tf_enable;
 434                                 prim.index_of_first_vertex = info->start;
 435                                 prim.number_of_instances = info->instance_count;
 436                                 prim.instance_length = info->count;
 437                         }
 438                 } else {
 439                         cl_emit(&job->bcl, VERTEX_ARRAY_PRIMITIVES, prim) {
 440                                 prim.mode = info->mode | prim_tf_enable;
 441                                 prim.length = info->count;
 442                                 prim.index_of_first_vertex = info->start;
 443                         }
 444                 }
 445         }
 446         job->draw_calls_queued++;
 447
 448         if (vc5->zsa && job->zsbuf &&
 449             (vc5->zsa->base.depth.enabled ||
 450              vc5->zsa->base.stencil[0].enabled)) {
 451                 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
 452                 vc5_job_add_bo(job, rsc->bo);
 453
 454                 if (vc5->zsa->base.depth.enabled) {
 455                         job->resolve |= PIPE_CLEAR_DEPTH;
 456                         rsc->initialized_buffers = PIPE_CLEAR_DEPTH;
 457
 458                         if (vc5->zsa->early_z_enable)
 459                                 job->uses_early_z = true;
 460                 }
 461
 462                 if (vc5->zsa->base.stencil[0].enabled) {
 463                         job->resolve |= PIPE_CLEAR_STENCIL;
 464                         rsc->initialized_buffers |= PIPE_CLEAR_STENCIL;
 465                 }
 466         }
 467
 468         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 469                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 470
 471                 if (job->resolve & bit || !job->cbufs[i])
 472                         continue;
 473                 struct vc5_resource *rsc = vc5_resource(job->cbufs[i]->texture);
 474
 475                 job->resolve |= bit;
 476                 vc5_job_add_bo(job, rsc->bo);
 477         }
 478
 479         if (job->referenced_size > 768 * 1024 * 1024) {
 480                 perf_debug("Flushing job with %dkb to try to free up memory\n",
 481                         job->referenced_size / 1024);
 482                 vc5_flush(pctx);
 483         }
 484
 485         if (V3D_DEBUG & V3D_DEBUG_ALWAYS_FLUSH)
 486                 vc5_flush(pctx);
 487 }
 488
 489 static void
 490 vc5_clear(struct pipe_context *pctx, unsigned buffers,
 491           const union pipe_color_union *color, double depth, unsigned stencil)
 492 {
 493         struct vc5_context *vc5 = vc5_context(pctx);
 494         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 495
 496         /* We can't flag new buffers for clearing once we've queued draws.  We
 497          * could avoid this by using the 3d engine to clear.
 498          */
 499         if (job->draw_calls_queued) {
 500                 perf_debug("Flushing rendering to process new clear.\n");
 501                 vc5_job_submit(vc5, job);
 502                 job = vc5_get_job_for_fbo(vc5);
 503         }
 504
 505         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 506                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 507                 if (!(buffers & bit))
 508                         continue;
 509
 510                 struct pipe_surface *psurf = vc5->framebuffer.cbufs[i];
 511                 struct vc5_surface *surf = vc5_surface(psurf);
 512                 struct vc5_resource *rsc = vc5_resource(psurf->texture);
 513
 514                 union util_color uc;
 515                 uint32_t internal_size = 4 << surf->internal_bpp;
 516
 517                 static union pipe_color_union swapped_color;
 518                 if (vc5->swap_color_rb & (1 << i)) {
 519                         swapped_color.f[0] = color->f[2];
 520                         swapped_color.f[1] = color->f[1];
 521                         swapped_color.f[2] = color->f[0];
 522                         swapped_color.f[3] = color->f[3];
 523                         color = &swapped_color;
 524                 }
 525
 526                 switch (surf->internal_type) {
 527                 case INTERNAL_TYPE_8:
 528                         if (surf->format == PIPE_FORMAT_B4G4R4A4_UNORM ||
 529                             surf->format == PIPE_FORMAT_B4G4R4A4_UNORM) {
 530                                 /* Our actual hardware layout is ABGR4444, but
 531                                  * we apply a swizzle when texturing to flip
 532                                  * things back around.
 533                                  */
 534                                 util_pack_color(color->f, PIPE_FORMAT_A8R8G8B8_UNORM,
 535                                                 &uc);
 536                         } else {
 537                                 util_pack_color(color->f, PIPE_FORMAT_R8G8B8A8_UNORM,
 538                                                 &uc);
 539                         }
 540                         memcpy(job->clear_color[i], uc.ui, internal_size);
 541                         break;
 542                 case INTERNAL_TYPE_8I:
 543                 case INTERNAL_TYPE_8UI:
 544                         job->clear_color[i][0] = ((uc.ui[0] & 0xff) |
 545                                                   (uc.ui[1] & 0xff) << 8 |
 546                                                   (uc.ui[2] & 0xff) << 16 |
 547                                                   (uc.ui[3] & 0xff) << 24);
 548                         break;
 549                 case INTERNAL_TYPE_16F:
 550                         util_pack_color(color->f, PIPE_FORMAT_R16G16B16A16_FLOAT,
 551                                         &uc);
 552                         memcpy(job->clear_color[i], uc.ui, internal_size);
 553                         break;
 554                 case INTERNAL_TYPE_16I:
 555                 case INTERNAL_TYPE_16UI:
 556                         job->clear_color[i][0] = ((uc.ui[0] & 0xffff) |
 557                                                   uc.ui[1] << 16);
 558                         job->clear_color[i][1] = ((uc.ui[2] & 0xffff) |
 559                                                   uc.ui[3] << 16);
 560                         break;
 561                 case INTERNAL_TYPE_32F:
 562                 case INTERNAL_TYPE_32I:
 563                 case INTERNAL_TYPE_32UI:
 564                         memcpy(job->clear_color[i], color->ui, internal_size);
 565                         break;
 566                 }
 567
 568                 rsc->initialized_buffers |= bit;
 569         }
 570
 571         unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
 572         if (zsclear) {
 573                 struct vc5_resource *rsc =
 574                         vc5_resource(vc5->framebuffer.zsbuf->texture);
 575
 576                 if (zsclear & PIPE_CLEAR_DEPTH)
 577                         job->clear_z = depth;
 578                 if (zsclear & PIPE_CLEAR_STENCIL)
 579                         job->clear_s = stencil;
 580
 581                 rsc->initialized_buffers |= zsclear;
 582         }
 583
 584         job->draw_min_x = 0;
 585         job->draw_min_y = 0;
 586         job->draw_max_x = vc5->framebuffer.width;
 587         job->draw_max_y = vc5->framebuffer.height;
 588         job->cleared |= buffers;
 589         job->resolve |= buffers;
 590
 591         vc5_start_draw(vc5);
 592 }
 593
 594 static void
 595 vc5_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 596                         const union pipe_color_union *color,
 597                         unsigned x, unsigned y, unsigned w, unsigned h,
 598                         bool render_condition_enabled)
 599 {
 600         fprintf(stderr, "unimpl: clear RT\n");
 601 }
 602
 603 static void
 604 vc5_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 605                         unsigned buffers, double depth, unsigned stencil,
 606                         unsigned x, unsigned y, unsigned w, unsigned h,
 607                         bool render_condition_enabled)
 608 {
 609         fprintf(stderr, "unimpl: clear DS\n");
 610 }
 611
 612 void
 613 vc5_draw_init(struct pipe_context *pctx)
 614 {
 615         pctx->draw_vbo = vc5_draw_vbo;
 616         pctx->clear = vc5_clear;
 617         pctx->clear_render_target = vc5_clear_render_target;
 618         pctx->clear_depth_stencil = vc5_clear_depth_stencil;
 619 }