src/gallium/drivers/vc5/vc5_draw.c

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/u_blitter.h"
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "util/u_prim_restart.h"
  29 #include "util/u_upload_mgr.h"
  30 #include "indices/u_primconvert.h"
  31
  32 #include "vc5_context.h"
  33 #include "vc5_resource.h"
  34 #include "vc5_cl.h"
  35 #include "broadcom/cle/v3d_packet_v33_pack.h"
  36 #include "broadcom/compiler/v3d_compiler.h"
  37
  38 /**
  39  * Does the initial bining command list setup for drawing to a given FBO.
  40  */
  41 static void
  42 vc5_start_draw(struct vc5_context *vc5)
  43 {
  44         struct vc5_job *job = vc5->job;
  45
  46         if (job->needs_flush)
  47                 return;
  48
  49         /* Get space to emit our BCL state, using a branch to jump to a new BO
  50          * if necessary.
  51          */
  52         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
  53
  54         job->submit.bcl_start = job->bcl.bo->offset;
  55         vc5_job_add_bo(job, job->bcl.bo);
  56
  57         job->tile_alloc = vc5_bo_alloc(vc5->screen, 1024 * 1024, "tile alloc");
  58         struct vc5_bo *tsda = vc5_bo_alloc(vc5->screen,
  59                                            job->draw_tiles_y *
  60                                            job->draw_tiles_x *
  61                                            64,
  62                                            "TSDA");
  63
  64         /* "Binning mode lists start with a Tile Binning Mode Configuration
  65          * item (120)"
  66          *
  67          * Part1 signals the end of binning config setup.
  68          */
  69         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART2, config) {
  70                 config.tile_allocation_memory_address =
  71                         cl_address(job->tile_alloc, 0);
  72                 config.tile_allocation_memory_size = job->tile_alloc->size;
  73         }
  74
  75         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART1, config) {
  76                 config.tile_state_data_array_base_address =
  77                         cl_address(tsda, 0);
  78
  79                 config.width_in_tiles = job->draw_tiles_x;
  80                 config.height_in_tiles = job->draw_tiles_y;
  81
  82                 /* Must be >= 1 */
  83                 config.number_of_render_targets =
  84                         MAX2(vc5->framebuffer.nr_cbufs, 1);
  85
  86                 config.multisample_mode_4x = job->msaa;
  87
  88                 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
  89         }
  90
  91         vc5_bo_unreference(&tsda);
  92
  93         /* There's definitely nothing in the VCD cache we want. */
  94         cl_emit(&job->bcl, FLUSH_VCD_CACHE, bin);
  95
  96         /* Disable any leftover OQ state from another job. */
  97         cl_emit(&job->bcl, OCCLUSION_QUERY_COUNTER, counter);
  98
  99         /* "Binning mode lists must have a Start Tile Binning item (6) after
 100          *  any prefix state data before the binning list proper starts."
 101          */
 102         cl_emit(&job->bcl, START_TILE_BINNING, bin);
 103
 104         cl_emit(&job->bcl, PRIMITIVE_LIST_FORMAT, fmt) {
 105                 fmt.data_type = LIST_INDEXED;
 106                 fmt.primitive_type = LIST_TRIANGLES;
 107         }
 108
 109         job->needs_flush = true;
 110         job->draw_width = vc5->framebuffer.width;
 111         job->draw_height = vc5->framebuffer.height;
 112 }
 113
 114 static void
 115 vc5_predraw_check_textures(struct pipe_context *pctx,
 116                            struct vc5_texture_stateobj *stage_tex)
 117 {
 118         struct vc5_context *vc5 = vc5_context(pctx);
 119
 120         for (int i = 0; i < stage_tex->num_textures; i++) {
 121                 struct pipe_sampler_view *view = stage_tex->textures[i];
 122                 if (!view)
 123                         continue;
 124
 125                 vc5_flush_jobs_writing_resource(vc5, view->texture);
 126         }
 127 }
 128
 129 static void
 130 vc5_emit_gl_shader_state(struct vc5_context *vc5,
 131                          const struct pipe_draw_info *info)
 132 {
 133         struct vc5_job *job = vc5->job;
 134         /* VC5_DIRTY_VTXSTATE */
 135         struct vc5_vertex_stateobj *vtx = vc5->vtx;
 136         /* VC5_DIRTY_VTXBUF */
 137         struct vc5_vertexbuf_stateobj *vertexbuf = &vc5->vertexbuf;
 138
 139         /* Upload the uniforms to the indirect CL first */
 140         struct vc5_cl_reloc fs_uniforms =
 141                 vc5_write_uniforms(vc5, vc5->prog.fs,
 142                                    &vc5->constbuf[PIPE_SHADER_FRAGMENT],
 143                                    &vc5->fragtex);
 144         struct vc5_cl_reloc vs_uniforms =
 145                 vc5_write_uniforms(vc5, vc5->prog.vs,
 146                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 147                                    &vc5->verttex);
 148         struct vc5_cl_reloc cs_uniforms =
 149                 vc5_write_uniforms(vc5, vc5->prog.cs,
 150                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 151                                    &vc5->verttex);
 152
 153         /* See GFXH-930 workaround below */
 154         uint32_t num_elements_to_emit = MAX2(vtx->num_elements, 1);
 155         uint32_t shader_rec_offset =
 156                 vc5_cl_ensure_space(&job->indirect,
 157                                     cl_packet_length(GL_SHADER_STATE_RECORD) +
 158                                     num_elements_to_emit *
 159                                     cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD),
 160                                     32);
 161
 162         cl_emit(&job->indirect, GL_SHADER_STATE_RECORD, shader) {
 163                 shader.enable_clipping = true;
 164                 /* VC5_DIRTY_PRIM_MODE | VC5_DIRTY_RASTERIZER */
 165                 shader.point_size_in_shaded_vertex_data =
 166                         (info->mode == PIPE_PRIM_POINTS &&
 167                          vc5->rasterizer->base.point_size_per_vertex);
 168
 169                 /* Must be set if the shader modifies Z, discards, or modifies
 170                  * the sample mask.  For any of these cases, the fragment
 171                  * shader needs to write the Z value (even just discards).
 172                  */
 173                 shader.fragment_shader_does_z_writes =
 174                         (vc5->prog.fs->prog_data.fs->writes_z ||
 175                          vc5->prog.fs->prog_data.fs->discard);
 176
 177                 shader.number_of_varyings_in_fragment_shader =
 178                         vc5->prog.fs->prog_data.base->num_inputs;
 179
 180                 shader.propagate_nans = true;
 181
 182                 shader.coordinate_shader_code_address =
 183                         cl_address(vc5->prog.cs->bo, 0);
 184                 shader.vertex_shader_code_address =
 185                         cl_address(vc5->prog.vs->bo, 0);
 186                 shader.fragment_shader_code_address =
 187                         cl_address(vc5->prog.fs->bo, 0);
 188
 189                 /* XXX: Use combined input/output size flag in the common
 190                  * case.
 191                  */
 192                 shader.coordinate_shader_has_separate_input_and_output_vpm_blocks = true;
 193                 shader.vertex_shader_has_separate_input_and_output_vpm_blocks = true;
 194                 shader.coordinate_shader_input_vpm_segment_size =
 195                         MAX2(vc5->prog.cs->prog_data.vs->vpm_input_size, 1);
 196                 shader.vertex_shader_input_vpm_segment_size =
 197                         MAX2(vc5->prog.vs->prog_data.vs->vpm_input_size, 1);
 198
 199                 shader.coordinate_shader_output_vpm_segment_size =
 200                         vc5->prog.cs->prog_data.vs->vpm_output_size;
 201                 shader.vertex_shader_output_vpm_segment_size =
 202                         vc5->prog.vs->prog_data.vs->vpm_output_size;
 203
 204                 shader.coordinate_shader_uniforms_address = cs_uniforms;
 205                 shader.vertex_shader_uniforms_address = vs_uniforms;
 206                 shader.fragment_shader_uniforms_address = fs_uniforms;
 207
 208                 shader.vertex_id_read_by_coordinate_shader =
 209                         vc5->prog.cs->prog_data.vs->uses_vid;
 210                 shader.instance_id_read_by_coordinate_shader =
 211                         vc5->prog.cs->prog_data.vs->uses_iid;
 212                 shader.vertex_id_read_by_vertex_shader =
 213                         vc5->prog.vs->prog_data.vs->uses_vid;
 214                 shader.instance_id_read_by_vertex_shader =
 215                         vc5->prog.vs->prog_data.vs->uses_iid;
 216
 217                 shader.address_of_default_attribute_values =
 218                         cl_address(vtx->default_attribute_values, 0);
 219         }
 220
 221         for (int i = 0; i < vtx->num_elements; i++) {
 222                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 223                 struct pipe_vertex_buffer *vb =
 224                         &vertexbuf->vb[elem->vertex_buffer_index];
 225                 struct vc5_resource *rsc = vc5_resource(vb->buffer.resource);
 226
 227                 const uint32_t size =
 228                         cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD);
 229                 cl_emit_with_prepacked(&job->indirect,
 230                                        GL_SHADER_STATE_ATTRIBUTE_RECORD,
 231                                        &vtx->attrs[i * size], attr) {
 232                         attr.stride = vb->stride;
 233                         attr.address = cl_address(rsc->bo,
 234                                                   vb->buffer_offset +
 235                                                   elem->src_offset);
 236                         attr.number_of_values_read_by_coordinate_shader =
 237                                 vc5->prog.cs->prog_data.vs->vattr_sizes[i];
 238                         attr.number_of_values_read_by_vertex_shader =
 239                                 vc5->prog.vs->prog_data.vs->vattr_sizes[i];
 240                 }
 241         }
 242
 243         if (vtx->num_elements == 0) {
 244                 /* GFXH-930: At least one attribute must be enabled and read
 245                  * by CS and VS.  If we have no attributes being consumed by
 246                  * the shader, set up a dummy to be loaded into the VPM.
 247                  */
 248                 cl_emit(&job->indirect, GL_SHADER_STATE_ATTRIBUTE_RECORD, attr) {
 249                         /* Valid address of data whose value will be unused. */
 250                         attr.address = cl_address(job->indirect.bo, 0);
 251
 252                         attr.type = ATTRIBUTE_FLOAT;
 253                         attr.stride = 0;
 254                         attr.vec_size = 1;
 255
 256                         attr.number_of_values_read_by_coordinate_shader = 1;
 257                         attr.number_of_values_read_by_vertex_shader = 1;
 258                 }
 259         }
 260
 261         cl_emit(&job->bcl, GL_SHADER_STATE, state) {
 262                 state.address = cl_address(job->indirect.bo, shader_rec_offset);
 263                 state.number_of_attribute_arrays = num_elements_to_emit;
 264         }
 265
 266         vc5_bo_unreference(&cs_uniforms.bo);
 267         vc5_bo_unreference(&vs_uniforms.bo);
 268         vc5_bo_unreference(&fs_uniforms.bo);
 269
 270         job->shader_rec_count++;
 271 }
 272
 273 /**
 274  * Computes the various transform feedback statistics, since they can't be
 275  * recorded by CL packets.
 276  */
 277 static void
 278 vc5_tf_statistics_record(struct vc5_context *vc5,
 279                          const struct pipe_draw_info *info,
 280                          bool prim_tf)
 281 {
 282         if (!vc5->active_queries)
 283                 return;
 284
 285         uint32_t prims = u_prims_for_vertices(info->mode, info->count);
 286         vc5->prims_generated += prims;
 287
 288         if (prim_tf) {
 289                 /* XXX: Only count if we didn't overflow. */
 290                 vc5->tf_prims_generated += prims;
 291         }
 292 }
 293
 294 static void
 295 vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 296 {
 297         struct vc5_context *vc5 = vc5_context(pctx);
 298
 299         if (!info->count_from_stream_output && !info->indirect &&
 300             !info->primitive_restart &&
 301             !u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
 302                 return;
 303
 304         /* Fall back for weird desktop GL primitive restart values. */
 305         if (info->primitive_restart &&
 306             info->index_size) {
 307                 uint32_t mask = ~0;
 308
 309                 switch (info->index_size) {
 310                 case 2:
 311                         mask = 0xffff;
 312                         break;
 313                 case 1:
 314                         mask = 0xff;
 315                         break;
 316                 }
 317
 318                 if (info->restart_index != mask) {
 319                         util_draw_vbo_without_prim_restart(pctx, info);
 320                         return;
 321                 }
 322         }
 323
 324         if (info->mode >= PIPE_PRIM_QUADS) {
 325                 util_primconvert_save_rasterizer_state(vc5->primconvert, &vc5->rasterizer->base);
 326                 util_primconvert_draw_vbo(vc5->primconvert, info);
 327                 perf_debug("Fallback conversion for %d %s vertices\n",
 328                            info->count, u_prim_name(info->mode));
 329                 return;
 330         }
 331
 332         /* Before setting up the draw, flush anything writing to the textures
 333          * that we read from.
 334          */
 335         vc5_predraw_check_textures(pctx, &vc5->verttex);
 336         vc5_predraw_check_textures(pctx, &vc5->fragtex);
 337
 338         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 339
 340         /* Get space to emit our draw call into the BCL, using a branch to
 341          * jump to a new BO if necessary.
 342          */
 343         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
 344
 345         if (vc5->prim_mode != info->mode) {
 346                 vc5->prim_mode = info->mode;
 347                 vc5->dirty |= VC5_DIRTY_PRIM_MODE;
 348         }
 349
 350         vc5_start_draw(vc5);
 351         vc5_update_compiled_shaders(vc5, info->mode);
 352
 353         vc5_emit_state(pctx);
 354
 355         if (vc5->dirty & (VC5_DIRTY_VTXBUF |
 356                           VC5_DIRTY_VTXSTATE |
 357                           VC5_DIRTY_PRIM_MODE |
 358                           VC5_DIRTY_RASTERIZER |
 359                           VC5_DIRTY_COMPILED_CS |
 360                           VC5_DIRTY_COMPILED_VS |
 361                           VC5_DIRTY_COMPILED_FS |
 362                           vc5->prog.cs->uniform_dirty_bits |
 363                           vc5->prog.vs->uniform_dirty_bits |
 364                           vc5->prog.fs->uniform_dirty_bits)) {
 365                 vc5_emit_gl_shader_state(vc5, info);
 366         }
 367
 368         vc5->dirty = 0;
 369
 370         /* The Base Vertex/Base Instance packet sets those values to nonzero
 371          * for the next draw call only.
 372          */
 373         if (info->index_bias || info->start_instance) {
 374                 cl_emit(&job->bcl, BASE_VERTEX_BASE_INSTANCE, base) {
 375                         base.base_instance = info->start_instance;
 376                         base.base_vertex = info->index_bias;
 377                 }
 378         }
 379
 380         /* The HW only processes transform feedback on primitives with the
 381          * flag set.
 382          */
 383         uint32_t prim_tf_enable = 0;
 384         if (vc5->streamout.num_targets)
 385                 prim_tf_enable = (V3D_PRIM_POINTS_TF - V3D_PRIM_POINTS);
 386
 387         vc5_tf_statistics_record(vc5, info, prim_tf_enable);
 388
 389         /* Note that the primitive type fields match with OpenGL/gallium
 390          * definitions, up to but not including QUADS.
 391          */
 392         if (info->index_size) {
 393                 uint32_t index_size = info->index_size;
 394                 uint32_t offset = info->start * index_size;
 395                 struct pipe_resource *prsc;
 396                 if (info->has_user_indices) {
 397                         prsc = NULL;
 398                         u_upload_data(vc5->uploader, 0,
 399                                       info->count * info->index_size, 4,
 400                                       info->index.user,
 401                                       &offset, &prsc);
 402                 } else {
 403                         prsc = info->index.resource;
 404                 }
 405                 struct vc5_resource *rsc = vc5_resource(prsc);
 406
 407                 if (info->instance_count > 1) {
 408                         cl_emit(&job->bcl, INDEXED_INSTANCED_PRIMITIVE_LIST, prim) {
 409                                 prim.index_type = ffs(info->index_size) - 1;
 410                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 411                                 prim.address_of_indices_list =
 412                                         cl_address(rsc->bo, offset);
 413                                 prim.mode = info->mode | prim_tf_enable;
 414                                 prim.enable_primitive_restarts = info->primitive_restart;
 415
 416                                 prim.number_of_instances = info->instance_count;
 417                                 prim.instance_length = info->count;
 418                         }
 419                 } else {
 420                         cl_emit(&job->bcl, INDEXED_PRIMITIVE_LIST, prim) {
 421                                 prim.index_type = ffs(info->index_size) - 1;
 422                                 prim.length = info->count;
 423                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 424                                 prim.address_of_indices_list =
 425                                         cl_address(rsc->bo, offset);
 426                                 prim.mode = info->mode | prim_tf_enable;
 427                                 prim.enable_primitive_restarts = info->primitive_restart;
 428                         }
 429                 }
 430
 431                 job->draw_calls_queued++;
 432
 433                 if (info->has_user_indices)
 434                         pipe_resource_reference(&prsc, NULL);
 435         } else {
 436                 if (info->instance_count > 1) {
 437                         cl_emit(&job->bcl, VERTEX_ARRAY_INSTANCED_PRIMITIVES, prim) {
 438                                 prim.mode = info->mode | prim_tf_enable;
 439                                 prim.index_of_first_vertex = info->start;
 440                                 prim.number_of_instances = info->instance_count;
 441                                 prim.instance_length = info->count;
 442                         }
 443                 } else {
 444                         cl_emit(&job->bcl, VERTEX_ARRAY_PRIMITIVES, prim) {
 445                                 prim.mode = info->mode | prim_tf_enable;
 446                                 prim.length = info->count;
 447                                 prim.index_of_first_vertex = info->start;
 448                         }
 449                 }
 450         }
 451         job->draw_calls_queued++;
 452
 453         if (vc5->zsa && job->zsbuf &&
 454             (vc5->zsa->base.depth.enabled ||
 455              vc5->zsa->base.stencil[0].enabled)) {
 456                 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
 457                 vc5_job_add_bo(job, rsc->bo);
 458
 459                 if (vc5->zsa->base.depth.enabled) {
 460                         job->resolve |= PIPE_CLEAR_DEPTH;
 461                         rsc->initialized_buffers = PIPE_CLEAR_DEPTH;
 462
 463                         if (vc5->zsa->early_z_enable)
 464                                 job->uses_early_z = true;
 465                 }
 466
 467                 if (vc5->zsa->base.stencil[0].enabled) {
 468                         job->resolve |= PIPE_CLEAR_STENCIL;
 469                         rsc->initialized_buffers |= PIPE_CLEAR_STENCIL;
 470                 }
 471         }
 472
 473         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 474                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 475
 476                 if (job->resolve & bit || !job->cbufs[i])
 477                         continue;
 478                 struct vc5_resource *rsc = vc5_resource(job->cbufs[i]->texture);
 479
 480                 job->resolve |= bit;
 481                 vc5_job_add_bo(job, rsc->bo);
 482         }
 483
 484         if (job->referenced_size > 768 * 1024 * 1024) {
 485                 perf_debug("Flushing job with %dkb to try to free up memory\n",
 486                         job->referenced_size / 1024);
 487                 vc5_flush(pctx);
 488         }
 489
 490         if (V3D_DEBUG & V3D_DEBUG_ALWAYS_FLUSH)
 491                 vc5_flush(pctx);
 492 }
 493
 494 static void
 495 vc5_clear(struct pipe_context *pctx, unsigned buffers,
 496           const union pipe_color_union *color, double depth, unsigned stencil)
 497 {
 498         struct vc5_context *vc5 = vc5_context(pctx);
 499         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 500
 501         /* We can't flag new buffers for clearing once we've queued draws.  We
 502          * could avoid this by using the 3d engine to clear.
 503          */
 504         if (job->draw_calls_queued) {
 505                 perf_debug("Flushing rendering to process new clear.\n");
 506                 vc5_job_submit(vc5, job);
 507                 job = vc5_get_job_for_fbo(vc5);
 508         }
 509
 510         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 511                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 512                 if (!(buffers & bit))
 513                         continue;
 514
 515                 struct pipe_surface *psurf = vc5->framebuffer.cbufs[i];
 516                 struct vc5_surface *surf = vc5_surface(psurf);
 517                 struct vc5_resource *rsc = vc5_resource(psurf->texture);
 518
 519                 union util_color uc;
 520                 uint32_t internal_size = 4 << surf->internal_bpp;
 521
 522                 static union pipe_color_union swapped_color;
 523                 if (vc5->swap_color_rb & (1 << i)) {
 524                         swapped_color.f[0] = color->f[2];
 525                         swapped_color.f[1] = color->f[1];
 526                         swapped_color.f[2] = color->f[0];
 527                         swapped_color.f[3] = color->f[3];
 528                         color = &swapped_color;
 529                 }
 530
 531                 switch (surf->internal_type) {
 532                 case INTERNAL_TYPE_8:
 533                         if (surf->format == PIPE_FORMAT_B4G4R4A4_UNORM ||
 534                             surf->format == PIPE_FORMAT_B4G4R4A4_UNORM) {
 535                                 /* Our actual hardware layout is ABGR4444, but
 536                                  * we apply a swizzle when texturing to flip
 537                                  * things back around.
 538                                  */
 539                                 util_pack_color(color->f, PIPE_FORMAT_A8R8G8B8_UNORM,
 540                                                 &uc);
 541                         } else {
 542                                 util_pack_color(color->f, PIPE_FORMAT_R8G8B8A8_UNORM,
 543                                                 &uc);
 544                         }
 545                         memcpy(job->clear_color[i], uc.ui, internal_size);
 546                         break;
 547                 case INTERNAL_TYPE_8I:
 548                 case INTERNAL_TYPE_8UI:
 549                         job->clear_color[i][0] = ((uc.ui[0] & 0xff) |
 550                                                   (uc.ui[1] & 0xff) << 8 |
 551                                                   (uc.ui[2] & 0xff) << 16 |
 552                                                   (uc.ui[3] & 0xff) << 24);
 553                         break;
 554                 case INTERNAL_TYPE_16F:
 555                         util_pack_color(color->f, PIPE_FORMAT_R16G16B16A16_FLOAT,
 556                                         &uc);
 557                         memcpy(job->clear_color[i], uc.ui, internal_size);
 558                         break;
 559                 case INTERNAL_TYPE_16I:
 560                 case INTERNAL_TYPE_16UI:
 561                         job->clear_color[i][0] = ((uc.ui[0] & 0xffff) |
 562                                                   uc.ui[1] << 16);
 563                         job->clear_color[i][1] = ((uc.ui[2] & 0xffff) |
 564                                                   uc.ui[3] << 16);
 565                         break;
 566                 case INTERNAL_TYPE_32F:
 567                 case INTERNAL_TYPE_32I:
 568                 case INTERNAL_TYPE_32UI:
 569                         memcpy(job->clear_color[i], color->ui, internal_size);
 570                         break;
 571                 }
 572
 573                 rsc->initialized_buffers |= bit;
 574         }
 575
 576         unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
 577         if (zsclear) {
 578                 struct vc5_resource *rsc =
 579                         vc5_resource(vc5->framebuffer.zsbuf->texture);
 580
 581                 if (zsclear & PIPE_CLEAR_DEPTH)
 582                         job->clear_z = depth;
 583                 if (zsclear & PIPE_CLEAR_STENCIL)
 584                         job->clear_s = stencil;
 585
 586                 rsc->initialized_buffers |= zsclear;
 587         }
 588
 589         job->draw_min_x = 0;
 590         job->draw_min_y = 0;
 591         job->draw_max_x = vc5->framebuffer.width;
 592         job->draw_max_y = vc5->framebuffer.height;
 593         job->cleared |= buffers;
 594         job->resolve |= buffers;
 595
 596         vc5_start_draw(vc5);
 597 }
 598
 599 static void
 600 vc5_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 601                         const union pipe_color_union *color,
 602                         unsigned x, unsigned y, unsigned w, unsigned h,
 603                         bool render_condition_enabled)
 604 {
 605         fprintf(stderr, "unimpl: clear RT\n");
 606 }
 607
 608 static void
 609 vc5_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 610                         unsigned buffers, double depth, unsigned stencil,
 611                         unsigned x, unsigned y, unsigned w, unsigned h,
 612                         bool render_condition_enabled)
 613 {
 614         fprintf(stderr, "unimpl: clear DS\n");
 615 }
 616
 617 void
 618 vc5_draw_init(struct pipe_context *pctx)
 619 {
 620         pctx->draw_vbo = vc5_draw_vbo;
 621         pctx->clear = vc5_clear;
 622         pctx->clear_render_target = vc5_clear_render_target;
 623         pctx->clear_depth_stencil = vc5_clear_depth_stencil;
 624 }