src/gallium/drivers/vc5/vc5_draw.c

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/u_blitter.h"
  25 #include "util/u_prim.h"
  26 #include "util/u_format.h"
  27 #include "util/u_pack_color.h"
  28 #include "util/u_prim_restart.h"
  29 #include "util/u_upload_mgr.h"
  30 #include "indices/u_primconvert.h"
  31
  32 #include "vc5_context.h"
  33 #include "vc5_resource.h"
  34 #include "vc5_cl.h"
  35 #include "broadcom/cle/v3d_packet_v33_pack.h"
  36 #include "broadcom/compiler/v3d_compiler.h"
  37
  38 /**
  39  * Does the initial bining command list setup for drawing to a given FBO.
  40  */
  41 static void
  42 vc5_start_draw(struct vc5_context *vc5)
  43 {
  44         struct vc5_job *job = vc5->job;
  45
  46         if (job->needs_flush)
  47                 return;
  48
  49         /* Get space to emit our BCL state, using a branch to jump to a new BO
  50          * if necessary.
  51          */
  52         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
  53
  54         job->submit.bcl_start = job->bcl.bo->offset;
  55         vc5_job_add_bo(job, job->bcl.bo);
  56
  57         job->tile_alloc = vc5_bo_alloc(vc5->screen, 1024 * 1024, "tile alloc");
  58         struct vc5_bo *tsda = vc5_bo_alloc(vc5->screen,
  59                                            job->draw_tiles_y *
  60                                            job->draw_tiles_x *
  61                                            64,
  62                                            "TSDA");
  63
  64         /* "Binning mode lists start with a Tile Binning Mode Configuration
  65          * item (120)"
  66          *
  67          * Part1 signals the end of binning config setup.
  68          */
  69         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART2, config) {
  70                 config.tile_allocation_memory_address =
  71                         cl_address(job->tile_alloc, 0);
  72                 config.tile_allocation_memory_size = job->tile_alloc->size;
  73         }
  74
  75         cl_emit(&job->bcl, TILE_BINNING_MODE_CONFIGURATION_PART1, config) {
  76                 config.tile_state_data_array_base_address =
  77                         cl_address(tsda, 0);
  78
  79                 config.width_in_tiles = job->draw_tiles_x;
  80                 config.height_in_tiles = job->draw_tiles_y;
  81
  82                 /* Must be >= 1 */
  83                 config.number_of_render_targets =
  84                         MAX2(vc5->framebuffer.nr_cbufs, 1);
  85
  86                 config.multisample_mode_4x = job->msaa;
  87
  88                 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
  89         }
  90
  91         vc5_bo_unreference(&tsda);
  92
  93         /* There's definitely nothing in the VCD cache we want. */
  94         cl_emit(&job->bcl, FLUSH_VCD_CACHE, bin);
  95
  96         /* "Binning mode lists must have a Start Tile Binning item (6) after
  97          *  any prefix state data before the binning list proper starts."
  98          */
  99         cl_emit(&job->bcl, START_TILE_BINNING, bin);
 100
 101         cl_emit(&job->bcl, PRIMITIVE_LIST_FORMAT, fmt) {
 102                 fmt.data_type = LIST_INDEXED;
 103                 fmt.primitive_type = LIST_TRIANGLES;
 104         }
 105
 106         job->needs_flush = true;
 107         job->draw_width = vc5->framebuffer.width;
 108         job->draw_height = vc5->framebuffer.height;
 109 }
 110
 111 static void
 112 vc5_predraw_check_textures(struct pipe_context *pctx,
 113                            struct vc5_texture_stateobj *stage_tex)
 114 {
 115         struct vc5_context *vc5 = vc5_context(pctx);
 116
 117         for (int i = 0; i < stage_tex->num_textures; i++) {
 118                 struct pipe_sampler_view *view = stage_tex->textures[i];
 119                 if (!view)
 120                         continue;
 121
 122                 vc5_flush_jobs_writing_resource(vc5, view->texture);
 123         }
 124 }
 125
 126 static struct vc5_cl_reloc
 127 vc5_get_default_values(struct vc5_context *vc5)
 128 {
 129         struct vc5_job *job = vc5->job;
 130
 131         /* VC5_DIRTY_VTXSTATE */
 132         struct vc5_vertex_stateobj *vtx = vc5->vtx;
 133
 134         /* Set up the default values for attributes. */
 135         vc5_cl_ensure_space(&job->indirect, 4 * 4 * vtx->num_elements, 4);
 136         struct vc5_cl_reloc default_values =
 137                 cl_address(job->indirect.bo, cl_offset(&job->indirect));
 138         vc5_bo_reference(default_values.bo);
 139
 140         struct vc5_cl_out *defaults = cl_start(&job->indirect);
 141         for (int i = 0; i < vtx->num_elements; i++) {
 142                 cl_aligned_f(&defaults, 0.0);
 143                 cl_aligned_f(&defaults, 0.0);
 144                 cl_aligned_f(&defaults, 0.0);
 145                 cl_aligned_f(&defaults, 1.0);
 146         }
 147         cl_end(&job->indirect, defaults);
 148
 149         return default_values;
 150 }
 151
 152 static void
 153 vc5_emit_gl_shader_state(struct vc5_context *vc5,
 154                          const struct pipe_draw_info *info)
 155 {
 156         struct vc5_job *job = vc5->job;
 157         /* VC5_DIRTY_VTXSTATE */
 158         struct vc5_vertex_stateobj *vtx = vc5->vtx;
 159         /* VC5_DIRTY_VTXBUF */
 160         struct vc5_vertexbuf_stateobj *vertexbuf = &vc5->vertexbuf;
 161
 162         /* Upload the uniforms to the indirect CL first */
 163         struct vc5_cl_reloc fs_uniforms =
 164                 vc5_write_uniforms(vc5, vc5->prog.fs,
 165                                    &vc5->constbuf[PIPE_SHADER_FRAGMENT],
 166                                    &vc5->fragtex);
 167         struct vc5_cl_reloc vs_uniforms =
 168                 vc5_write_uniforms(vc5, vc5->prog.vs,
 169                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 170                                    &vc5->verttex);
 171         struct vc5_cl_reloc cs_uniforms =
 172                 vc5_write_uniforms(vc5, vc5->prog.cs,
 173                                    &vc5->constbuf[PIPE_SHADER_VERTEX],
 174                                    &vc5->verttex);
 175         struct vc5_cl_reloc default_values = vc5_get_default_values(vc5);
 176
 177         uint32_t shader_rec_offset =
 178                 vc5_cl_ensure_space(&job->indirect,
 179                                     cl_packet_length(GL_SHADER_STATE_RECORD) +
 180                                     vtx->num_elements *
 181                                     cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD),
 182                                     32);
 183
 184         cl_emit(&job->indirect, GL_SHADER_STATE_RECORD, shader) {
 185                 shader.enable_clipping = true;
 186                 /* VC5_DIRTY_PRIM_MODE | VC5_DIRTY_RASTERIZER */
 187                 shader.point_size_in_shaded_vertex_data =
 188                         (info->mode == PIPE_PRIM_POINTS &&
 189                          vc5->rasterizer->base.point_size_per_vertex);
 190
 191                 /* Must be set if the shader modifies Z, discards, or modifies
 192                  * the sample mask.  For any of these cases, the fragment
 193                  * shader needs to write the Z value (even just discards).
 194                  */
 195                 shader.fragment_shader_does_z_writes =
 196                         (vc5->prog.fs->prog_data.fs->writes_z ||
 197                          vc5->prog.fs->prog_data.fs->discard);
 198
 199                 shader.number_of_varyings_in_fragment_shader =
 200                         vc5->prog.fs->prog_data.base->num_inputs;
 201
 202                 shader.propagate_nans = true;
 203
 204                 shader.coordinate_shader_code_address =
 205                         cl_address(vc5->prog.cs->bo, 0);
 206                 shader.vertex_shader_code_address =
 207                         cl_address(vc5->prog.vs->bo, 0);
 208                 shader.fragment_shader_code_address =
 209                         cl_address(vc5->prog.fs->bo, 0);
 210
 211                 /* XXX: Use combined input/output size flag in the common
 212                  * case.
 213                  */
 214                 shader.coordinate_shader_has_separate_input_and_output_vpm_blocks = true;
 215                 shader.vertex_shader_has_separate_input_and_output_vpm_blocks = true;
 216                 shader.coordinate_shader_input_vpm_segment_size =
 217                         vc5->prog.cs->prog_data.vs->vpm_input_size;
 218                 shader.vertex_shader_input_vpm_segment_size =
 219                         vc5->prog.vs->prog_data.vs->vpm_input_size;
 220
 221                 shader.coordinate_shader_output_vpm_segment_size =
 222                         vc5->prog.cs->prog_data.vs->vpm_output_size;
 223                 shader.vertex_shader_output_vpm_segment_size =
 224                         vc5->prog.vs->prog_data.vs->vpm_output_size;
 225
 226                 shader.coordinate_shader_uniforms_address = cs_uniforms;
 227                 shader.vertex_shader_uniforms_address = vs_uniforms;
 228                 shader.fragment_shader_uniforms_address = fs_uniforms;
 229
 230                 shader.vertex_id_read_by_coordinate_shader =
 231                         vc5->prog.cs->prog_data.vs->uses_vid;
 232                 shader.instance_id_read_by_coordinate_shader =
 233                         vc5->prog.cs->prog_data.vs->uses_iid;
 234                 shader.vertex_id_read_by_vertex_shader =
 235                         vc5->prog.vs->prog_data.vs->uses_vid;
 236                 shader.instance_id_read_by_vertex_shader =
 237                         vc5->prog.vs->prog_data.vs->uses_iid;
 238
 239                 shader.address_of_default_attribute_values = default_values;
 240         }
 241
 242         for (int i = 0; i < vtx->num_elements; i++) {
 243                 struct pipe_vertex_element *elem = &vtx->pipe[i];
 244                 struct pipe_vertex_buffer *vb =
 245                         &vertexbuf->vb[elem->vertex_buffer_index];
 246                 struct vc5_resource *rsc = vc5_resource(vb->buffer.resource);
 247                 const struct util_format_description *desc =
 248                         util_format_description(elem->src_format);
 249
 250                 uint32_t offset = vb->buffer_offset + elem->src_offset;
 251
 252                 cl_emit(&job->indirect, GL_SHADER_STATE_ATTRIBUTE_RECORD, attr) {
 253                         uint32_t r_size = desc->channel[0].size;
 254
 255                         /* vec_size == 0 means 4 */
 256                         attr.vec_size = desc->nr_channels & 3;
 257
 258                         switch (desc->channel[0].type) {
 259                         case UTIL_FORMAT_TYPE_FLOAT:
 260                                 if (r_size == 32) {
 261                                         attr.type = ATTRIBUTE_FLOAT;
 262                                 } else {
 263                                         assert(r_size == 16);
 264                                         attr.type = ATTRIBUTE_HALF_FLOAT;
 265                                 }
 266                                 break;
 267
 268                         case UTIL_FORMAT_TYPE_SIGNED:
 269                         case UTIL_FORMAT_TYPE_UNSIGNED:
 270                                 switch (r_size) {
 271                                 case 32:
 272                                         attr.type = ATTRIBUTE_INT;
 273                                         break;
 274                                 case 16:
 275                                         attr.type = ATTRIBUTE_SHORT;
 276                                         break;
 277                                 case 10:
 278                                         attr.type = ATTRIBUTE_INT2_10_10_10;
 279                                         break;
 280                                 case 8:
 281                                         attr.type = ATTRIBUTE_BYTE;
 282                                         break;
 283                                 default:
 284                                         fprintf(stderr,
 285                                                 "format %s unsupported\n",
 286                                                 desc->name);
 287                                         attr.type = ATTRIBUTE_BYTE;
 288                                         abort();
 289                                 }
 290                                 break;
 291
 292                         default:
 293                                 fprintf(stderr,
 294                                         "format %s unsupported\n",
 295                                         desc->name);
 296                                 abort();
 297                         }
 298
 299                         attr.signed_int_type =
 300                                 desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED;
 301
 302                         attr.normalized_int_type = desc->channel[0].normalized;
 303                         attr.read_as_int_uint = desc->channel[0].pure_integer;
 304                         attr.address = cl_address(rsc->bo, offset);
 305                         attr.stride = vb->stride;
 306                         attr.instance_divisor = elem->instance_divisor;
 307                         attr.number_of_values_read_by_coordinate_shader =
 308                                 vc5->prog.cs->prog_data.vs->vattr_sizes[i];
 309                         attr.number_of_values_read_by_vertex_shader =
 310                                 vc5->prog.vs->prog_data.vs->vattr_sizes[i];
 311                 }
 312         }
 313
 314         cl_emit(&job->bcl, GL_SHADER_STATE, state) {
 315                 state.address = cl_address(job->indirect.bo, shader_rec_offset);
 316                 state.number_of_attribute_arrays = vtx->num_elements;
 317         }
 318
 319         vc5_bo_unreference(&cs_uniforms.bo);
 320         vc5_bo_unreference(&vs_uniforms.bo);
 321         vc5_bo_unreference(&fs_uniforms.bo);
 322         vc5_bo_unreference(&default_values.bo);
 323
 324         job->shader_rec_count++;
 325 }
 326
 327 static void
 328 vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
 329 {
 330         struct vc5_context *vc5 = vc5_context(pctx);
 331
 332         if (!info->count_from_stream_output && !info->indirect &&
 333             !info->primitive_restart &&
 334             !u_trim_pipe_prim(info->mode, (unsigned*)&info->count))
 335                 return;
 336
 337         /* Fall back for weird desktop GL primitive restart values. */
 338         if (info->primitive_restart &&
 339             info->index_size) {
 340                 uint32_t mask = ~0;
 341
 342                 switch (info->index_size) {
 343                 case 2:
 344                         mask = 0xffff;
 345                         break;
 346                 case 1:
 347                         mask = 0xff;
 348                         break;
 349                 }
 350
 351                 if (info->restart_index != mask) {
 352                         util_draw_vbo_without_prim_restart(pctx, info);
 353                         return;
 354                 }
 355         }
 356
 357         if (info->mode >= PIPE_PRIM_QUADS) {
 358                 util_primconvert_save_rasterizer_state(vc5->primconvert, &vc5->rasterizer->base);
 359                 util_primconvert_draw_vbo(vc5->primconvert, info);
 360                 perf_debug("Fallback conversion for %d %s vertices\n",
 361                            info->count, u_prim_name(info->mode));
 362                 return;
 363         }
 364
 365         /* Before setting up the draw, flush anything writing to the textures
 366          * that we read from.
 367          */
 368         vc5_predraw_check_textures(pctx, &vc5->verttex);
 369         vc5_predraw_check_textures(pctx, &vc5->fragtex);
 370
 371         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 372
 373         /* Get space to emit our draw call into the BCL, using a branch to
 374          * jump to a new BO if necessary.
 375          */
 376         vc5_cl_ensure_space_with_branch(&job->bcl, 256 /* XXX */);
 377
 378         if (vc5->prim_mode != info->mode) {
 379                 vc5->prim_mode = info->mode;
 380                 vc5->dirty |= VC5_DIRTY_PRIM_MODE;
 381         }
 382
 383         vc5_start_draw(vc5);
 384         vc5_update_compiled_shaders(vc5, info->mode);
 385
 386         vc5_emit_state(pctx);
 387
 388         if (vc5->dirty & (VC5_DIRTY_VTXBUF |
 389                           VC5_DIRTY_VTXSTATE |
 390                           VC5_DIRTY_PRIM_MODE |
 391                           VC5_DIRTY_RASTERIZER |
 392                           VC5_DIRTY_COMPILED_CS |
 393                           VC5_DIRTY_COMPILED_VS |
 394                           VC5_DIRTY_COMPILED_FS |
 395                           vc5->prog.cs->uniform_dirty_bits |
 396                           vc5->prog.vs->uniform_dirty_bits |
 397                           vc5->prog.fs->uniform_dirty_bits)) {
 398                 vc5_emit_gl_shader_state(vc5, info);
 399         }
 400
 401         vc5->dirty = 0;
 402
 403         /* The Base Vertex/Base Instance packet sets those values to nonzero
 404          * for the next draw call only.
 405          */
 406         if (info->index_bias || info->start_instance) {
 407                 cl_emit(&job->bcl, BASE_VERTEX_BASE_INSTANCE, base) {
 408                         base.base_instance = info->start_instance;
 409                         base.base_vertex = info->index_bias;
 410                 }
 411         }
 412
 413         /* The HW only processes transform feedback on primitives with the
 414          * flag set.
 415          */
 416         uint32_t prim_tf_enable = 0;
 417         if (vc5->prog.bind_vs->num_tf_outputs)
 418                 prim_tf_enable = (V3D_PRIM_POINTS_TF - V3D_PRIM_POINTS);
 419
 420         /* Note that the primitive type fields match with OpenGL/gallium
 421          * definitions, up to but not including QUADS.
 422          */
 423         if (info->index_size) {
 424                 uint32_t index_size = info->index_size;
 425                 uint32_t offset = info->start * index_size;
 426                 struct pipe_resource *prsc;
 427                 if (info->has_user_indices) {
 428                         prsc = NULL;
 429                         u_upload_data(vc5->uploader, 0,
 430                                       info->count * info->index_size, 4,
 431                                       info->index.user,
 432                                       &offset, &prsc);
 433                 } else {
 434                         prsc = info->index.resource;
 435                 }
 436                 struct vc5_resource *rsc = vc5_resource(prsc);
 437
 438                 if (info->instance_count > 1) {
 439                         cl_emit(&job->bcl, INDEXED_INSTANCED_PRIMITIVE_LIST, prim) {
 440                                 prim.index_type = ffs(info->index_size) - 1;
 441                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 442                                 prim.address_of_indices_list =
 443                                         cl_address(rsc->bo, offset);
 444                                 prim.mode = info->mode | prim_tf_enable;
 445                                 prim.enable_primitive_restarts = info->primitive_restart;
 446
 447                                 prim.number_of_instances = info->instance_count;
 448                                 prim.instance_length = info->count;
 449                         }
 450                 } else {
 451                         cl_emit(&job->bcl, INDEXED_PRIMITIVE_LIST, prim) {
 452                                 prim.index_type = ffs(info->index_size) - 1;
 453                                 prim.length = info->count;
 454                                 prim.maximum_index = (1u << 31) - 1; /* XXX */
 455                                 prim.address_of_indices_list =
 456                                         cl_address(rsc->bo, offset);
 457                                 prim.mode = info->mode | prim_tf_enable;
 458                                 prim.enable_primitive_restarts = info->primitive_restart;
 459                         }
 460                 }
 461
 462                 job->draw_calls_queued++;
 463
 464                 if (info->has_user_indices)
 465                         pipe_resource_reference(&prsc, NULL);
 466         } else {
 467                 if (info->instance_count > 1) {
 468                         cl_emit(&job->bcl, VERTEX_ARRAY_INSTANCED_PRIMITIVES, prim) {
 469                                 prim.mode = info->mode | prim_tf_enable;
 470                                 prim.index_of_first_vertex = info->start;
 471                                 prim.number_of_instances = info->instance_count;
 472                                 prim.instance_length = info->count;
 473                         }
 474                 } else {
 475                         cl_emit(&job->bcl, VERTEX_ARRAY_PRIMITIVES, prim) {
 476                                 prim.mode = info->mode | prim_tf_enable;
 477                                 prim.length = info->count;
 478                                 prim.index_of_first_vertex = info->start;
 479                         }
 480                 }
 481         }
 482         job->draw_calls_queued++;
 483
 484         if (vc5->zsa && job->zsbuf &&
 485             (vc5->zsa->base.depth.enabled ||
 486              vc5->zsa->base.stencil[0].enabled)) {
 487                 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
 488                 vc5_job_add_bo(job, rsc->bo);
 489
 490                 if (vc5->zsa->base.depth.enabled) {
 491                         job->resolve |= PIPE_CLEAR_DEPTH;
 492                         rsc->initialized_buffers = PIPE_CLEAR_DEPTH;
 493
 494                         if (vc5->zsa->early_z_enable)
 495                                 job->uses_early_z = true;
 496                 }
 497
 498                 if (vc5->zsa->base.stencil[0].enabled) {
 499                         job->resolve |= PIPE_CLEAR_STENCIL;
 500                         rsc->initialized_buffers |= PIPE_CLEAR_STENCIL;
 501                 }
 502         }
 503
 504         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 505                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 506
 507                 if (job->resolve & bit || !job->cbufs[i])
 508                         continue;
 509                 struct vc5_resource *rsc = vc5_resource(job->cbufs[i]->texture);
 510
 511                 job->resolve |= bit;
 512                 vc5_job_add_bo(job, rsc->bo);
 513         }
 514
 515         if (V3D_DEBUG & V3D_DEBUG_ALWAYS_FLUSH)
 516                 vc5_flush(pctx);
 517 }
 518
 519 static void
 520 vc5_clear(struct pipe_context *pctx, unsigned buffers,
 521           const union pipe_color_union *color, double depth, unsigned stencil)
 522 {
 523         struct vc5_context *vc5 = vc5_context(pctx);
 524         struct vc5_job *job = vc5_get_job_for_fbo(vc5);
 525
 526         /* We can't flag new buffers for clearing once we've queued draws.  We
 527          * could avoid this by using the 3d engine to clear.
 528          */
 529         if (job->draw_calls_queued) {
 530                 perf_debug("Flushing rendering to process new clear.\n");
 531                 vc5_job_submit(vc5, job);
 532                 job = vc5_get_job_for_fbo(vc5);
 533         }
 534
 535         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 536                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 537                 if (!(buffers & bit))
 538                         continue;
 539
 540                 struct pipe_surface *cbuf = vc5->framebuffer.cbufs[i];
 541                 struct vc5_resource *rsc =
 542                         vc5_resource(cbuf->texture);
 543
 544                 union util_color uc;
 545                 util_pack_color(color->f, cbuf->format, &uc);
 546
 547                 memcpy(job->clear_color[i], uc.ui,
 548                        util_format_get_blocksize(cbuf->format));
 549
 550                 rsc->initialized_buffers |= bit;
 551         }
 552
 553         unsigned zsclear = buffers & PIPE_CLEAR_DEPTHSTENCIL;
 554         if (zsclear) {
 555                 struct vc5_resource *rsc =
 556                         vc5_resource(vc5->framebuffer.zsbuf->texture);
 557
 558                 if (zsclear & PIPE_CLEAR_DEPTH)
 559                         job->clear_z = depth;
 560                 if (zsclear & PIPE_CLEAR_STENCIL)
 561                         job->clear_s = stencil;
 562
 563                 rsc->initialized_buffers |= zsclear;
 564         }
 565
 566         job->draw_min_x = 0;
 567         job->draw_min_y = 0;
 568         job->draw_max_x = vc5->framebuffer.width;
 569         job->draw_max_y = vc5->framebuffer.height;
 570         job->cleared |= buffers;
 571         job->resolve |= buffers;
 572
 573         vc5_start_draw(vc5);
 574 }
 575
 576 static void
 577 vc5_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 578                         const union pipe_color_union *color,
 579                         unsigned x, unsigned y, unsigned w, unsigned h,
 580                         bool render_condition_enabled)
 581 {
 582         fprintf(stderr, "unimpl: clear RT\n");
 583 }
 584
 585 static void
 586 vc5_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 587                         unsigned buffers, double depth, unsigned stencil,
 588                         unsigned x, unsigned y, unsigned w, unsigned h,
 589                         bool render_condition_enabled)
 590 {
 591         fprintf(stderr, "unimpl: clear DS\n");
 592 }
 593
 594 void
 595 vc5_draw_init(struct pipe_context *pctx)
 596 {
 597         pctx->draw_vbo = vc5_draw_vbo;
 598         pctx->clear = vc5_clear;
 599         pctx->clear_render_target = vc5_clear_render_target;
 600         pctx->clear_depth_stencil = vc5_clear_depth_stencil;
 601 }