src/gallium/drivers/vc5/vc5_drm.h

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef _VC5_DRM_H_
  25 #define _VC5_DRM_H_
  26
  27 #include "drm.h"
  28
  29 #if defined(__cplusplus)
  30 extern "C" {
  31 #endif
  32
  33 #define DRM_VC5_SUBMIT_CL                         0x00
  34 #define DRM_VC5_WAIT_SEQNO                        0x01
  35 #define DRM_VC5_WAIT_BO                           0x02
  36 #define DRM_VC5_CREATE_BO                         0x03
  37 #define DRM_VC5_MMAP_BO                           0x04
  38 #define DRM_VC5_GET_PARAM                         0x05
  39 #define DRM_VC5_GET_BO_OFFSET                     0x06
  40
  41 #define DRM_IOCTL_VC5_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_SUBMIT_CL, struct drm_vc5_submit_cl)
  42 #define DRM_IOCTL_VC5_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_WAIT_SEQNO, struct drm_vc5_wait_seqno)
  43 #define DRM_IOCTL_VC5_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_WAIT_BO, struct drm_vc5_wait_bo)
  44 #define DRM_IOCTL_VC5_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_CREATE_BO, struct drm_vc5_create_bo)
  45 #define DRM_IOCTL_VC5_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_MMAP_BO, struct drm_vc5_mmap_bo)
  46 #define DRM_IOCTL_VC5_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_GET_PARAM, struct drm_vc5_get_param)
  47 #define DRM_IOCTL_VC5_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_VC5_GET_BO_OFFSET, struct drm_vc5_get_bo_offset)
  48
  49 /**
  50  * struct drm_vc5_submit_cl - ioctl argument for submitting commands to the 3D
  51  * engine.
  52  *
  53  * This asks the kernel to have the GPU execute an optional binner
  54  * command list, and a render command list.
  55  */
  56 struct drm_vc5_submit_cl {
  57         /* Pointer to the binner command list.
  58          *
  59          * This is the first set of commands executed, which runs the
  60          * coordinate shader to determine where primitives land on the screen,
  61          * then writes out the state updates and draw calls necessary per tile
  62          * to the tile allocation BO.
  63          */
  64         __u32 bcl_start;
  65
  66          /** End address of the BCL (first byte after the BCL) */
  67         __u32 bcl_end;
  68
  69         /* Offset of the render command list.
  70          *
  71          * This is the second set of commands executed, which will either
  72          * execute the tiles that have been set up by the BCL, or a fixed set
  73          * of tiles (in the case of RCL-only blits).
  74          */
  75         __u32 rcl_start;
  76
  77          /** End address of the RCL (first byte after the RCL) */
  78         __u32 rcl_end;
  79
  80         /* Pointer to a u32 array of the BOs that are referenced by the job.
  81          */
  82         __u64 bo_handles;
  83
  84         /* Pointer to an array of chunks of extra submit CL information. (the
  85          * chunk struct is not yet defined)
  86          */
  87         __u64 chunks;
  88
  89         /* Number of BO handles passed in (size is that times 4). */
  90         __u32 bo_handle_count;
  91
  92         __u32 chunk_count;
  93
  94         __u64 flags;
  95 };
  96
  97 /**
  98  * struct drm_vc5_wait_seqno - ioctl argument for waiting for
  99  * DRM_VC5_SUBMIT_CL completion using its returned seqno.
 100  *
 101  * timeout_ns is the timeout in nanoseconds, where "0" means "don't
 102  * block, just return the status."
 103  */
 104 struct drm_vc5_wait_seqno {
 105         __u64 seqno;
 106         __u64 timeout_ns;
 107 };
 108
 109 /**
 110  * struct drm_vc5_wait_bo - ioctl argument for waiting for
 111  * completion of the last DRM_VC5_SUBMIT_CL on a BO.
 112  *
 113  * This is useful for cases where multiple processes might be
 114  * rendering to a BO and you want to wait for all rendering to be
 115  * completed.
 116  */
 117 struct drm_vc5_wait_bo {
 118         __u32 handle;
 119         __u32 pad;
 120         __u64 timeout_ns;
 121 };
 122
 123 /**
 124  * struct drm_vc5_create_bo - ioctl argument for creating VC5 BOs.
 125  *
 126  * There are currently no values for the flags argument, but it may be
 127  * used in a future extension.
 128  */
 129 struct drm_vc5_create_bo {
 130         __u32 size;
 131         __u32 flags;
 132         /** Returned GEM handle for the BO. */
 133         __u32 handle;
 134         /**
 135          * Returned offset for the BO in the V3D address space.  This offset
 136          * is private to the DRM fd and is valid for the lifetime of the GEM
 137          * handle.
 138          */
 139         __u32 offset;
 140 };
 141
 142 /**
 143  * struct drm_vc5_mmap_bo - ioctl argument for mapping VC5 BOs.
 144  *
 145  * This doesn't actually perform an mmap.  Instead, it returns the
 146  * offset you need to use in an mmap on the DRM device node.  This
 147  * means that tools like valgrind end up knowing about the mapped
 148  * memory.
 149  *
 150  * There are currently no values for the flags argument, but it may be
 151  * used in a future extension.
 152  */
 153 struct drm_vc5_mmap_bo {
 154         /** Handle for the object being mapped. */
 155         __u32 handle;
 156         __u32 flags;
 157         /** offset into the drm node to use for subsequent mmap call. */
 158         __u64 offset;
 159 };
 160
 161 enum drm_vc5_param {
 162         DRM_VC5_PARAM_V3D_UIFCFG,
 163         DRM_VC5_PARAM_V3D_HUB_IDENT1,
 164         DRM_VC5_PARAM_V3D_HUB_IDENT2,
 165         DRM_VC5_PARAM_V3D_HUB_IDENT3,
 166         DRM_VC5_PARAM_V3D_CORE0_IDENT0,
 167         DRM_VC5_PARAM_V3D_CORE0_IDENT1,
 168         DRM_VC5_PARAM_V3D_CORE0_IDENT2,
 169 };
 170
 171 struct drm_vc5_get_param {
 172         __u32 param;
 173         __u32 pad;
 174         __u64 value;
 175 };
 176
 177 /**
 178  * Returns the offset for the BO in the V3D address space for this DRM fd.
 179  * This is the same value returned by drm_vc5_create_bo, if that was called
 180  * from this DRM fd.
 181  */
 182 struct drm_vc5_get_bo_offset {
 183         __u32 handle;
 184         __u32 offset;
 185 };
 186
 187 #if defined(__cplusplus)
 188 }
 189 #endif
 190
 191 #endif /* _VC5_DRM_H_ */