2 * Copyright © 2014-2017 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "util/u_format.h"
25 #include "util/u_half.h"
26 #include "vc5_context.h"
27 #include "broadcom/cle/v3d_packet_v33_pack.h"
28 #include "broadcom/compiler/v3d_compiler.h"
31 vc5_factor(enum pipe_blendfactor factor
, bool dst_alpha_one
)
33 /* We may get a bad blendfactor when blending is disabled. */
35 return V3D_BLEND_FACTOR_ZERO
;
38 case PIPE_BLENDFACTOR_ZERO
:
39 return V3D_BLEND_FACTOR_ZERO
;
40 case PIPE_BLENDFACTOR_ONE
:
41 return V3D_BLEND_FACTOR_ONE
;
42 case PIPE_BLENDFACTOR_SRC_COLOR
:
43 return V3D_BLEND_FACTOR_SRC_COLOR
;
44 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
45 return V3D_BLEND_FACTOR_INV_SRC_COLOR
;
46 case PIPE_BLENDFACTOR_DST_COLOR
:
47 return V3D_BLEND_FACTOR_DST_COLOR
;
48 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
49 return V3D_BLEND_FACTOR_INV_DST_COLOR
;
50 case PIPE_BLENDFACTOR_SRC_ALPHA
:
51 return V3D_BLEND_FACTOR_SRC_ALPHA
;
52 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
53 return V3D_BLEND_FACTOR_INV_SRC_ALPHA
;
54 case PIPE_BLENDFACTOR_DST_ALPHA
:
55 return (dst_alpha_one
?
56 V3D_BLEND_FACTOR_ONE
:
57 V3D_BLEND_FACTOR_DST_ALPHA
);
58 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
59 return (dst_alpha_one
?
60 V3D_BLEND_FACTOR_ZERO
:
61 V3D_BLEND_FACTOR_INV_DST_ALPHA
);
62 case PIPE_BLENDFACTOR_CONST_COLOR
:
63 return V3D_BLEND_FACTOR_CONST_COLOR
;
64 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
65 return V3D_BLEND_FACTOR_INV_CONST_COLOR
;
66 case PIPE_BLENDFACTOR_CONST_ALPHA
:
67 return V3D_BLEND_FACTOR_CONST_ALPHA
;
68 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
69 return V3D_BLEND_FACTOR_INV_CONST_ALPHA
;
70 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
71 return V3D_BLEND_FACTOR_SRC_ALPHA_SATURATE
;
73 unreachable("Bad blend factor");
77 static inline uint16_t
78 swizzled_border_color(struct pipe_sampler_state
*sampler
,
79 struct vc5_sampler_view
*sview
,
82 const struct util_format_description
*desc
=
83 util_format_description(sview
->base
.format
);
86 /* If we're doing swizzling in the sampler, then only rearrange the
87 * border color for the mismatch between the VC5 texture format and
88 * the PIPE_FORMAT, since GL_ARB_texture_swizzle will be handled by
89 * the sampler's swizzle.
91 * For swizzling in the shader, we don't do any pre-swizzling of the
94 if (vc5_get_tex_return_size(sview
->base
.format
) != 32)
95 swiz
= desc
->swizzle
[swiz
];
99 return util_float_to_half(0.0);
101 return util_float_to_half(1.0);
103 return util_float_to_half(sampler
->border_color
.f
[swiz
]);
108 emit_one_texture(struct vc5_context
*vc5
, struct vc5_texture_stateobj
*stage_tex
,
111 struct vc5_job
*job
= vc5
->job
;
112 struct pipe_sampler_state
*psampler
= stage_tex
->samplers
[i
];
113 struct vc5_sampler_state
*sampler
= vc5_sampler_state(psampler
);
114 struct pipe_sampler_view
*psview
= stage_tex
->textures
[i
];
115 struct vc5_sampler_view
*sview
= vc5_sampler_view(psview
);
116 struct pipe_resource
*prsc
= psview
->texture
;
117 struct vc5_resource
*rsc
= vc5_resource(prsc
);
119 stage_tex
->texture_state
[i
].offset
=
120 vc5_cl_ensure_space(&job
->indirect
,
121 cl_packet_length(TEXTURE_SHADER_STATE
),
123 vc5_bo_set_reference(&stage_tex
->texture_state
[i
].bo
,
126 struct V3D33_TEXTURE_SHADER_STATE unpacked
= {
128 .border_color_red
= swizzled_border_color(psampler
, sview
, 0),
129 .border_color_green
= swizzled_border_color(psampler
, sview
, 1),
130 .border_color_blue
= swizzled_border_color(psampler
, sview
, 2),
131 .border_color_alpha
= swizzled_border_color(psampler
, sview
, 3),
133 /* XXX: Disable min/maxlod for txf */
134 .max_level_of_detail
= MIN2(MIN2(psampler
->max_lod
,
136 psview
->u
.tex
.last_level
),
138 .texture_base_pointer
= cl_address(rsc
->bo
,
139 rsc
->slices
[0].offset
),
142 int min_img_filter
= psampler
->min_img_filter
;
143 int min_mip_filter
= psampler
->min_mip_filter
;
144 int mag_img_filter
= psampler
->mag_img_filter
;
146 if (vc5_get_tex_return_size(psview
->format
) == 32) {
147 min_mip_filter
= PIPE_TEX_MIPFILTER_NEAREST
;
148 mag_img_filter
= PIPE_TEX_FILTER_NEAREST
;
149 mag_img_filter
= PIPE_TEX_FILTER_NEAREST
;
152 bool min_nearest
= (min_img_filter
== PIPE_TEX_FILTER_NEAREST
);
153 switch (min_mip_filter
) {
154 case PIPE_TEX_MIPFILTER_NONE
:
155 unpacked
.minification_filter
= 0 + min_nearest
;
157 case PIPE_TEX_MIPFILTER_NEAREST
:
158 unpacked
.minification_filter
= 2 + !min_nearest
;
160 case PIPE_TEX_MIPFILTER_LINEAR
:
161 unpacked
.minification_filter
= 4 + !min_nearest
;
164 unpacked
.magnification_filter
= (mag_img_filter
==
165 PIPE_TEX_FILTER_NEAREST
);
167 uint8_t packed
[cl_packet_length(TEXTURE_SHADER_STATE
)];
168 cl_packet_pack(TEXTURE_SHADER_STATE
)(&job
->indirect
, packed
, &unpacked
);
170 for (int i
= 0; i
< ARRAY_SIZE(packed
); i
++)
171 packed
[i
] |= sview
->texture_shader_state
[i
] | sampler
->texture_shader_state
[i
];
173 /* TMU indirect structs need to be 32b aligned. */
174 vc5_cl_ensure_space(&job
->indirect
, ARRAY_SIZE(packed
), 32);
175 cl_emit_prepacked(&job
->indirect
, &packed
);
179 emit_textures(struct vc5_context
*vc5
, struct vc5_texture_stateobj
*stage_tex
)
181 for (int i
= 0; i
< stage_tex
->num_textures
; i
++)
182 emit_one_texture(vc5
, stage_tex
, i
);
186 vc5_emit_state(struct pipe_context
*pctx
)
188 struct vc5_context
*vc5
= vc5_context(pctx
);
189 struct vc5_job
*job
= vc5
->job
;
191 if (vc5
->dirty
& (VC5_DIRTY_SCISSOR
| VC5_DIRTY_VIEWPORT
|
192 VC5_DIRTY_RASTERIZER
)) {
193 float *vpscale
= vc5
->viewport
.scale
;
194 float *vptranslate
= vc5
->viewport
.translate
;
195 float vp_minx
= -fabsf(vpscale
[0]) + vptranslate
[0];
196 float vp_maxx
= fabsf(vpscale
[0]) + vptranslate
[0];
197 float vp_miny
= -fabsf(vpscale
[1]) + vptranslate
[1];
198 float vp_maxy
= fabsf(vpscale
[1]) + vptranslate
[1];
200 /* Clip to the scissor if it's enabled, but still clip to the
201 * drawable regardless since that controls where the binner
202 * tries to put things.
204 * Additionally, always clip the rendering to the viewport,
205 * since the hardware does guardband clipping, meaning
206 * primitives would rasterize outside of the view volume.
208 uint32_t minx
, miny
, maxx
, maxy
;
209 if (!vc5
->rasterizer
->base
.scissor
) {
210 minx
= MAX2(vp_minx
, 0);
211 miny
= MAX2(vp_miny
, 0);
212 maxx
= MIN2(vp_maxx
, job
->draw_width
);
213 maxy
= MIN2(vp_maxy
, job
->draw_height
);
215 minx
= MAX2(vp_minx
, vc5
->scissor
.minx
);
216 miny
= MAX2(vp_miny
, vc5
->scissor
.miny
);
217 maxx
= MIN2(vp_maxx
, vc5
->scissor
.maxx
);
218 maxy
= MIN2(vp_maxy
, vc5
->scissor
.maxy
);
221 cl_emit(&job
->bcl
, CLIP_WINDOW
, clip
) {
222 clip
.clip_window_left_pixel_coordinate
= minx
;
223 clip
.clip_window_bottom_pixel_coordinate
= miny
;
224 clip
.clip_window_width_in_pixels
= maxx
- minx
;
225 clip
.clip_window_height_in_pixels
= maxy
- miny
;
228 job
->draw_min_x
= MIN2(job
->draw_min_x
, minx
);
229 job
->draw_min_y
= MIN2(job
->draw_min_y
, miny
);
230 job
->draw_max_x
= MAX2(job
->draw_max_x
, maxx
);
231 job
->draw_max_y
= MAX2(job
->draw_max_y
, maxy
);
234 if (vc5
->dirty
& (VC5_DIRTY_RASTERIZER
|
237 VC5_DIRTY_COMPILED_FS
)) {
238 cl_emit(&job
->bcl
, CONFIGURATION_BITS
, config
) {
239 config
.enable_forward_facing_primitive
=
240 !(vc5
->rasterizer
->base
.cull_face
&
242 config
.enable_reverse_facing_primitive
=
243 !(vc5
->rasterizer
->base
.cull_face
&
245 /* This seems backwards, but it's what gets the
246 * clipflat test to pass.
248 config
.clockwise_primitives
=
249 vc5
->rasterizer
->base
.front_ccw
;
251 config
.enable_depth_offset
=
252 vc5
->rasterizer
->base
.offset_tri
;
254 config
.rasterizer_oversample_mode
=
255 vc5
->rasterizer
->base
.multisample
;
257 config
.direct3d_provoking_vertex
=
258 vc5
->rasterizer
->base
.flatshade_first
;
260 config
.blend_enable
= vc5
->blend
->rt
[0].blend_enable
;
262 config
.early_z_updates_enable
= true;
263 if (vc5
->zsa
->base
.depth
.enabled
) {
264 config
.z_updates_enable
=
265 vc5
->zsa
->base
.depth
.writemask
;
266 config
.early_z_enable
=
267 vc5
->zsa
->early_z_enable
;
268 config
.depth_test_function
=
269 vc5
->zsa
->base
.depth
.func
;
271 config
.depth_test_function
= PIPE_FUNC_ALWAYS
;
274 config
.stencil_enable
=
275 vc5
->zsa
->base
.stencil
[0].enabled
;
280 if (vc5
->dirty
& VC5_DIRTY_RASTERIZER
) {
281 cl_emit(&job
->bcl
, DEPTH_OFFSET
, depth
) {
282 depth
.depth_offset_factor
=
283 vc5
->rasterizer
->offset_factor
;
284 depth
.depth_offset_units
=
285 vc5
->rasterizer
->offset_units
;
288 cl_emit(&job
->bcl
, POINT_SIZE
, point_size
) {
289 point_size
.point_size
= vc5
->rasterizer
->point_size
;
292 cl_emit(&job
->bcl
, LINE_WIDTH
, line_width
) {
293 line_width
.line_width
= vc5
->rasterizer
->base
.line_width
;
297 if (vc5
->dirty
& VC5_DIRTY_VIEWPORT
) {
298 cl_emit(&job
->bcl
, CLIPPER_XY_SCALING
, clip
) {
299 clip
.viewport_half_width_in_1_256th_of_pixel
=
300 vc5
->viewport
.scale
[0] * 256.0f
;
301 clip
.viewport_half_height_in_1_256th_of_pixel
=
302 vc5
->viewport
.scale
[1] * 256.0f
;
305 cl_emit(&job
->bcl
, CLIPPER_Z_SCALE_AND_OFFSET
, clip
) {
306 clip
.viewport_z_offset_zc_to_zs
=
307 vc5
->viewport
.translate
[2];
308 clip
.viewport_z_scale_zc_to_zs
=
309 vc5
->viewport
.scale
[2];
312 cl_emit(&job
->bcl
, CLIPPER_Z_MIN_MAX_CLIPPING_PLANES
, clip
) {
313 clip
.minimum_zw
= (vc5
->viewport
.translate
[2] -
314 vc5
->viewport
.scale
[2]);
315 clip
.maximum_zw
= (vc5
->viewport
.translate
[2] +
316 vc5
->viewport
.scale
[2]);
320 cl_emit(&job
->bcl
, VIEWPORT_OFFSET
, vp
) {
321 vp
.viewport_centre_x_coordinate
=
322 vc5
->viewport
.translate
[0];
323 vp
.viewport_centre_y_coordinate
=
324 vc5
->viewport
.translate
[1];
328 if (vc5
->dirty
& VC5_DIRTY_BLEND
&& vc5
->blend
->rt
[0].blend_enable
) {
329 struct pipe_blend_state
*blend
= vc5
->blend
;
331 cl_emit(&job
->bcl
, BLEND_CONFIG
, config
) {
332 struct pipe_rt_blend_state
*rtblend
= &blend
->rt
[0];
334 config
.colour_blend_mode
= rtblend
->rgb_func
;
335 config
.colour_blend_dst_factor
=
336 vc5_factor(rtblend
->rgb_dst_factor
,
337 vc5
->blend_dst_alpha_one
);
338 config
.colour_blend_src_factor
=
339 vc5_factor(rtblend
->rgb_src_factor
,
340 vc5
->blend_dst_alpha_one
);
342 config
.alpha_blend_mode
= rtblend
->alpha_func
;
343 config
.alpha_blend_dst_factor
=
344 vc5_factor(rtblend
->alpha_dst_factor
,
345 vc5
->blend_dst_alpha_one
);
346 config
.alpha_blend_src_factor
=
347 vc5_factor(rtblend
->alpha_src_factor
,
348 vc5
->blend_dst_alpha_one
);
352 if (vc5
->dirty
& VC5_DIRTY_BLEND
) {
353 struct pipe_blend_state
*blend
= vc5
->blend
;
355 cl_emit(&job
->bcl
, COLOUR_WRITE_MASKS
, mask
) {
356 if (blend
->independent_blend_enable
) {
357 mask
.render_target_0_per_colour_component_write_masks
=
358 (~blend
->rt
[0].colormask
) & 0xf;
359 mask
.render_target_1_per_colour_component_write_masks
=
360 (~blend
->rt
[1].colormask
) & 0xf;
361 mask
.render_target_2_per_colour_component_write_masks
=
362 (~blend
->rt
[2].colormask
) & 0xf;
363 mask
.render_target_3_per_colour_component_write_masks
=
364 (~blend
->rt
[3].colormask
) & 0xf;
366 uint8_t colormask
= (~blend
->rt
[0].colormask
) & 0xf;
367 mask
.render_target_0_per_colour_component_write_masks
= colormask
;
368 mask
.render_target_1_per_colour_component_write_masks
= colormask
;
369 mask
.render_target_2_per_colour_component_write_masks
= colormask
;
370 mask
.render_target_3_per_colour_component_write_masks
= colormask
;
375 if (vc5
->dirty
& VC5_DIRTY_BLEND_COLOR
) {
376 cl_emit(&job
->bcl
, BLEND_CONSTANT_COLOUR
, colour
) {
377 colour
.red_f16
= (vc5
->swap_color_rb
?
378 vc5
->blend_color
.hf
[2] :
379 vc5
->blend_color
.hf
[0]);
380 colour
.green_f16
= vc5
->blend_color
.hf
[1];
381 colour
.blue_f16
= (vc5
->swap_color_rb
?
382 vc5
->blend_color
.hf
[0] :
383 vc5
->blend_color
.hf
[2]);
384 colour
.alpha_f16
= vc5
->blend_color
.hf
[3];
388 if (vc5
->dirty
& (VC5_DIRTY_ZSA
| VC5_DIRTY_STENCIL_REF
) &&
389 vc5
->zsa
->base
.stencil
[0].enabled
) {
390 struct pipe_stencil_state
*front
= &vc5
->zsa
->base
.stencil
[0];
391 struct pipe_stencil_state
*back
= &vc5
->zsa
->base
.stencil
[1];
393 cl_emit(&job
->bcl
, STENCIL_CONFIG
, config
) {
394 config
.front_config
= true;
395 config
.back_config
= !back
->enabled
;
397 config
.stencil_write_mask
= front
->writemask
;
398 config
.stencil_test_mask
= front
->valuemask
;
400 config
.stencil_test_function
= front
->func
;
401 config
.stencil_pass_op
= front
->zpass_op
;
402 config
.depth_test_fail_op
= front
->zfail_op
;
403 config
.stencil_test_fail_op
= front
->fail_op
;
405 config
.stencil_ref_value
= vc5
->stencil_ref
.ref_value
[0];
409 cl_emit(&job
->bcl
, STENCIL_CONFIG
, config
) {
410 config
.front_config
= false;
411 config
.back_config
= true;
413 config
.stencil_write_mask
= back
->writemask
;
414 config
.stencil_test_mask
= back
->valuemask
;
416 config
.stencil_test_function
= back
->func
;
417 config
.stencil_pass_op
= back
->zpass_op
;
418 config
.depth_test_fail_op
= back
->zfail_op
;
419 config
.stencil_test_fail_op
= back
->fail_op
;
421 config
.stencil_ref_value
=
422 vc5
->stencil_ref
.ref_value
[1];
427 if (vc5
->dirty
& VC5_DIRTY_FRAGTEX
)
428 emit_textures(vc5
, &vc5
->fragtex
);
430 if (vc5
->dirty
& VC5_DIRTY_VERTTEX
)
431 emit_textures(vc5
, &vc5
->verttex
);
433 if (vc5
->dirty
& VC5_DIRTY_FLAT_SHADE_FLAGS
) {
434 /* XXX: Need to handle more than 24 entries. */
435 cl_emit(&job
->bcl
, FLAT_SHADE_FLAGS
, flags
) {
436 flags
.varying_offset_v0
= 0;
438 flags
.flat_shade_flags_for_varyings_v024
=
439 vc5
->prog
.fs
->prog_data
.fs
->flat_shade_flags
[0] & 0xfffff;
441 if (vc5
->rasterizer
->base
.flatshade
) {
442 flags
.flat_shade_flags_for_varyings_v024
|=
443 vc5
->prog
.fs
->prog_data
.fs
->shade_model_flags
[0] & 0xfffff;
448 if (vc5
->dirty
& VC5_DIRTY_STREAMOUT
) {
449 struct vc5_streamout_stateobj
*so
= &vc5
->streamout
;
451 if (so
->num_targets
) {
452 cl_emit(&job
->bcl
, TRANSFORM_FEEDBACK_ENABLE
, tfe
) {
453 tfe
.number_of_32_bit_output_buffer_address_following
=
455 tfe
.number_of_16_bit_output_data_specs_following
=
456 vc5
->prog
.bind_vs
->num_tf_specs
;
459 for (int i
= 0; i
< vc5
->prog
.bind_vs
->num_tf_specs
; i
++) {
460 cl_emit_prepacked(&job
->bcl
,
461 &vc5
->prog
.bind_vs
->tf_specs
[i
]);
464 for (int i
= 0; i
< so
->num_targets
; i
++) {
465 const struct pipe_stream_output_target
*target
=
467 struct vc5_resource
*rsc
=
468 vc5_resource(target
->buffer
);
470 cl_emit(&job
->bcl
, TRANSFORM_FEEDBACK_OUTPUT_ADDRESS
, output
) {
473 target
->buffer_offset
);
476 vc5_job_add_write_resource(vc5
->job
,
478 /* XXX: buffer_size? */