src/gallium/drivers/vc5/vc5_rcl.c

   1 /*
   2  * Copyright © 2017 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/u_format.h"
  25 #include "vc5_context.h"
  26 #include "vc5_tiling.h"
  27 #include "broadcom/common/v3d_macros.h"
  28 #include "broadcom/cle/v3dx_pack.h"
  29
  30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 |                   \
  31                                   PIPE_CLEAR_COLOR1 |                   \
  32                                   PIPE_CLEAR_COLOR2 |                   \
  33                                   PIPE_CLEAR_COLOR3)                    \
  34
  35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
  36
  37 /* The HW queues up the load until the tile coordinates show up, but can only
  38  * track one at a time.  If we need to do more than one load, then we need to
  39  * flush out the previous load by emitting the tile coordinates and doing a
  40  * dummy store.
  41  */
  42 static void
  43 flush_last_load(struct vc5_cl *cl)
  44 {
  45         if (V3D_VERSION >= 40)
  46                 return;
  47
  48         cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
  49         cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
  50                 store.buffer_to_store = NONE;
  51         }
  52 }
  53
  54 static void
  55 load_general(struct vc5_cl *cl, struct pipe_surface *psurf, int buffer,
  56              uint32_t pipe_bit, uint32_t *loads_pending)
  57 {
  58         struct vc5_surface *surf = vc5_surface(psurf);
  59         bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
  60         if (separate_stencil) {
  61                 psurf = surf->separate_stencil;
  62                 surf = vc5_surface(psurf);
  63         }
  64
  65         struct vc5_resource *rsc = vc5_resource(psurf->texture);
  66
  67         cl_emit(cl, LOAD_TILE_BUFFER_GENERAL, load) {
  68                 load.buffer_to_load = buffer;
  69                 load.address = cl_address(rsc->bo, surf->offset);
  70
  71 #if V3D_VERSION >= 40
  72                 load.memory_format = surf->tiling;
  73                 if (separate_stencil)
  74                         load.input_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
  75                 else
  76                         load.input_image_format = surf->format;
  77
  78                 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
  79                     surf->tiling == VC5_TILING_UIF_XOR) {
  80                         load.height_in_ub_or_stride =
  81                                 surf->padded_height_of_output_image_in_uif_blocks;
  82                 } else if (surf->tiling == VC5_TILING_RASTER) {
  83                         struct vc5_resource_slice *slice =
  84                                 &rsc->slices[psurf->u.tex.level];
  85                         load.height_in_ub_or_stride = slice->stride;
  86                 }
  87
  88                 /* XXX: MSAA */
  89 #else /* V3D_VERSION < 40 */
  90                 /* Can't do raw ZSTENCIL loads -- need to load/store them to
  91                  * separate buffers for Z and stencil.
  92                  */
  93                 assert(buffer != ZSTENCIL);
  94                 load.raw_mode = true;
  95                 load.padded_height_of_output_image_in_uif_blocks =
  96                         surf->padded_height_of_output_image_in_uif_blocks;
  97 #endif /* V3D_VERSION < 40 */
  98         }
  99
 100         *loads_pending &= ~pipe_bit;
 101         if (*loads_pending)
 102                 flush_last_load(cl);
 103 }
 104
 105 static void
 106 store_general(struct vc5_job *job,
 107               struct vc5_cl *cl, struct pipe_surface *psurf, int buffer,
 108               int pipe_bit, uint32_t *stores_pending, bool general_color_clear)
 109 {
 110         struct vc5_surface *surf = vc5_surface(psurf);
 111         bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
 112         if (separate_stencil) {
 113                 psurf = surf->separate_stencil;
 114                 surf = vc5_surface(psurf);
 115         }
 116
 117         *stores_pending &= ~pipe_bit;
 118         bool last_store = !(*stores_pending);
 119
 120         struct vc5_resource *rsc = vc5_resource(psurf->texture);
 121
 122         rsc->writes++;
 123
 124         cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
 125                 store.buffer_to_store = buffer;
 126                 store.address = cl_address(rsc->bo, surf->offset);
 127
 128 #if V3D_VERSION >= 40
 129                 store.clear_buffer_being_stored =
 130                         ((job->cleared & pipe_bit) &&
 131                          (general_color_clear ||
 132                           !(pipe_bit & PIPE_CLEAR_COLOR_BUFFERS)));
 133
 134                 if (separate_stencil)
 135                         store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
 136                 else
 137                         store.output_image_format = surf->format;
 138
 139                 store.memory_format = surf->tiling;
 140
 141                 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
 142                     surf->tiling == VC5_TILING_UIF_XOR) {
 143                         store.height_in_ub_or_stride =
 144                                 surf->padded_height_of_output_image_in_uif_blocks;
 145                 } else if (surf->tiling == VC5_TILING_RASTER) {
 146                         struct vc5_resource_slice *slice =
 147                                 &rsc->slices[psurf->u.tex.level];
 148                         store.height_in_ub_or_stride = slice->stride;
 149                 }
 150 #else /* V3D_VERSION < 40 */
 151                 /* Can't do raw ZSTENCIL stores -- need to load/store them to
 152                  * separate buffers for Z and stencil.
 153                  */
 154                 assert(buffer != ZSTENCIL);
 155                 store.raw_mode = true;
 156                 if (!last_store) {
 157                         store.disable_colour_buffers_clear_on_write = true;
 158                         store.disable_z_buffer_clear_on_write = true;
 159                         store.disable_stencil_buffer_clear_on_write = true;
 160                 } else {
 161                         store.disable_colour_buffers_clear_on_write =
 162                                 !(((pipe_bit & PIPE_CLEAR_COLOR_BUFFERS) &&
 163                                    general_color_clear &&
 164                                    (job->cleared & pipe_bit)));
 165                         store.disable_z_buffer_clear_on_write =
 166                                 !(job->cleared & PIPE_CLEAR_DEPTH);
 167                         store.disable_stencil_buffer_clear_on_write =
 168                                 !(job->cleared & PIPE_CLEAR_STENCIL);
 169                 }
 170                 store.padded_height_of_output_image_in_uif_blocks =
 171                         surf->padded_height_of_output_image_in_uif_blocks;
 172 #endif /* V3D_VERSION < 40 */
 173         }
 174
 175         /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
 176         if (V3D_VERSION < 40 && !last_store) {
 177                 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
 178         }
 179 }
 180
 181 static int
 182 zs_buffer_from_pipe_bits(int pipe_clear_bits)
 183 {
 184         switch (pipe_clear_bits & PIPE_CLEAR_DEPTHSTENCIL) {
 185         case PIPE_CLEAR_DEPTHSTENCIL:
 186                 return ZSTENCIL;
 187         case PIPE_CLEAR_DEPTH:
 188                 return Z;
 189         case PIPE_CLEAR_STENCIL:
 190                 return STENCIL;
 191         default:
 192                 return NONE;
 193         }
 194 }
 195
 196 static void
 197 vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
 198 {
 199         uint32_t loads_pending = job->resolve & ~job->cleared;
 200
 201         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 202                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 203                 if (!(loads_pending & bit))
 204                         continue;
 205
 206                 struct pipe_surface *psurf = job->cbufs[i];
 207                 if (!psurf || (V3D_VERSION < 40 &&
 208                                psurf->texture->nr_samples <= 1)) {
 209                         continue;
 210                 }
 211
 212                 load_general(cl, psurf, RENDER_TARGET_0 + i,
 213                              bit, &loads_pending);
 214         }
 215
 216         if ((loads_pending & PIPE_CLEAR_DEPTHSTENCIL) &&
 217             (V3D_VERSION >= 40 ||
 218              (job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
 219                 load_general(cl, job->zsbuf,
 220                              zs_buffer_from_pipe_bits(loads_pending),
 221                              PIPE_CLEAR_DEPTHSTENCIL,
 222                              &loads_pending);
 223         }
 224
 225 #if V3D_VERSION < 40
 226         /* The initial reload will be queued until we get the
 227          * tile coordinates.
 228          */
 229         if (loads_pending) {
 230                 cl_emit(cl, RELOAD_TILE_COLOUR_BUFFER, load) {
 231                         load.disable_colour_buffer_load =
 232                                 (~loads_pending &
 233                                  PIPE_CLEAR_COLOR_BUFFERS) >>
 234                                 PIPE_FIRST_COLOR_BUFFER_BIT;
 235                         load.enable_z_load =
 236                                 loads_pending & PIPE_CLEAR_DEPTH;
 237                         load.enable_stencil_load =
 238                                 loads_pending & PIPE_CLEAR_STENCIL;
 239                 }
 240         }
 241 #else /* V3D_VERSION >= 40 */
 242         assert(!loads_pending);
 243         cl_emit(cl, END_OF_LOADS, end);
 244 #endif
 245 }
 246
 247 static void
 248 vc5_rcl_emit_stores(struct vc5_job *job, struct vc5_cl *cl)
 249 {
 250         MAYBE_UNUSED bool needs_color_clear = job->cleared & PIPE_CLEAR_COLOR_BUFFERS;
 251         MAYBE_UNUSED bool needs_z_clear = job->cleared & PIPE_CLEAR_DEPTH;
 252         MAYBE_UNUSED bool needs_s_clear = job->cleared & PIPE_CLEAR_STENCIL;
 253
 254         /* For clearing color in a TLB general on V3D 3.3:
 255          *
 256          * - NONE buffer store clears all TLB color buffers.
 257          * - color buffer store clears just the TLB color buffer being stored.
 258          * - Z/S buffers store may not clear the TLB color buffer.
 259          *
 260          * And on V3D 4.1, we only have one flag for "clear the buffer being
 261          * stored" in the general packet, and a separate packet to clear all
 262          * color TLB buffers.
 263          *
 264          * As a result, we only bother flagging TLB color clears in a general
 265          * packet when we don't have to emit a separate packet to clear all
 266          * TLB color buffers.
 267          */
 268         bool general_color_clear = (needs_color_clear &&
 269                                     (job->cleared & PIPE_CLEAR_COLOR_BUFFERS) ==
 270                                     (job->resolve & PIPE_CLEAR_COLOR_BUFFERS));
 271
 272         uint32_t stores_pending = job->resolve;
 273
 274         /* For V3D 4.1, use general stores for all TLB stores.
 275          *
 276          * For V3D 3.3, we only use general stores to do raw stores for any
 277          * MSAA surfaces.  These output UIF tiled images where each 4x MSAA
 278          * pixel is a 2x2 quad, and the format will be that of the
 279          * internal_type/internal_bpp, rather than the format from GL's
 280          * perspective.  Non-MSAA surfaces will use
 281          * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
 282          */
 283         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 284                 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
 285                 if (!(job->resolve & bit))
 286                         continue;
 287
 288                 struct pipe_surface *psurf = job->cbufs[i];
 289                 if (!psurf ||
 290                     (V3D_VERSION < 40 && psurf->texture->nr_samples <= 1)) {
 291                         continue;
 292                 }
 293
 294                 store_general(job, cl, psurf, RENDER_TARGET_0 + i, bit,
 295                               &stores_pending, general_color_clear);
 296         }
 297
 298         if (job->resolve & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
 299             !(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
 300                 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
 301                 if (rsc->separate_stencil) {
 302                         if (job->resolve & PIPE_CLEAR_DEPTH) {
 303                                 store_general(job, cl, job->zsbuf, Z,
 304                                               PIPE_CLEAR_DEPTH,
 305                                               &stores_pending,
 306                                               general_color_clear);
 307                         }
 308
 309                         if (job->resolve & PIPE_CLEAR_STENCIL) {
 310                                 store_general(job, cl, job->zsbuf, STENCIL,
 311                                               PIPE_CLEAR_STENCIL,
 312                                               &stores_pending,
 313                                               general_color_clear);
 314                         }
 315                 } else {
 316                         store_general(job, cl, job->zsbuf,
 317                                       zs_buffer_from_pipe_bits(job->resolve),
 318                                       job->resolve & PIPE_CLEAR_DEPTHSTENCIL,
 319                                       &stores_pending, general_color_clear);
 320                 }
 321         }
 322
 323         if (stores_pending) {
 324 #if V3D_VERSION < 40
 325                 cl_emit(cl, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
 326
 327                         store.disable_color_buffer_write =
 328                                 (~stores_pending >>
 329                                  PIPE_FIRST_COLOR_BUFFER_BIT) & 0xf;
 330                         store.enable_z_write = stores_pending & PIPE_CLEAR_DEPTH;
 331                         store.enable_stencil_write = stores_pending & PIPE_CLEAR_STENCIL;
 332
 333                         /* Note that when set this will clear all of the color
 334                          * buffers.
 335                          */
 336                         store.disable_colour_buffers_clear_on_write =
 337                                 !needs_color_clear;
 338                         store.disable_z_buffer_clear_on_write =
 339                                 !needs_z_clear;
 340                         store.disable_stencil_buffer_clear_on_write =
 341                                 !needs_s_clear;
 342                 };
 343 #else /* V3D_VERSION >= 40 */
 344                 unreachable("All color buffers should have been stored.");
 345 #endif /* V3D_VERSION >= 40 */
 346         } else if (needs_color_clear && !general_color_clear) {
 347                 /* If we didn't do our color clears in the general packet,
 348                  * then emit a packet to clear all the TLB color buffers now.
 349                  */
 350 #if V3D_VERSION < 40
 351                 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
 352                         store.buffer_to_store = NONE;
 353                 }
 354 #else /* V3D_VERSION >= 40 */
 355                 cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
 356                         clear.clear_all_render_targets = true;
 357                 }
 358 #endif /* V3D_VERSION >= 40 */
 359         }
 360 }
 361
 362 static void
 363 vc5_rcl_emit_generic_per_tile_list(struct vc5_job *job, int last_cbuf)
 364 {
 365         /* Emit the generic list in our indirect state -- the rcl will just
 366          * have pointers into it.
 367          */
 368         struct vc5_cl *cl = &job->indirect;
 369         vc5_cl_ensure_space(cl, 200, 1);
 370         struct vc5_cl_reloc tile_list_start = cl_get_address(cl);
 371
 372         if (V3D_VERSION >= 40) {
 373                 /* V3D 4.x only requires a single tile coordinates, and
 374                  * END_OF_LOADS switches us between loading and rendering.
 375                  */
 376                 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
 377         }
 378
 379         vc5_rcl_emit_loads(job, cl);
 380
 381         if (V3D_VERSION < 40) {
 382                 /* Tile Coordinates triggers the last reload and sets where
 383                  * the stores go. There must be one per store packet.
 384                  */
 385                 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
 386         }
 387
 388         /* The binner starts out writing tiles assuming that the initial mode
 389          * is triangles, so make sure that's the case.
 390          */
 391         cl_emit(cl, PRIMITIVE_LIST_FORMAT, fmt) {
 392                 fmt.data_type = LIST_INDEXED;
 393                 fmt.primitive_type = LIST_TRIANGLES;
 394         }
 395
 396         cl_emit(cl, BRANCH_TO_IMPLICIT_TILE_LIST, branch);
 397
 398         vc5_rcl_emit_stores(job, cl);
 399
 400 #if V3D_VERSION >= 40
 401         cl_emit(cl, END_OF_TILE_MARKER, end);
 402 #endif
 403
 404         cl_emit(cl, RETURN_FROM_SUB_LIST, ret);
 405
 406         cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
 407                 branch.start = tile_list_start;
 408                 branch.end = cl_get_address(cl);
 409         }
 410 }
 411
 412 #if V3D_VERSION >= 40
 413 static void
 414 v3d_setup_render_target(struct vc5_job *job, int cbuf,
 415                         uint32_t *rt_bpp, uint32_t *rt_type, uint32_t *rt_clamp)
 416 {
 417         if (!job->cbufs[cbuf])
 418                 return;
 419
 420         struct vc5_surface *surf = vc5_surface(job->cbufs[cbuf]);
 421         *rt_bpp = surf->internal_bpp;
 422         *rt_type = surf->internal_type;
 423         *rt_clamp = V3D_RENDER_TARGET_CLAMP_NONE;
 424 }
 425
 426 #else /* V3D_VERSION < 40 */
 427
 428 static void
 429 v3d_emit_z_stencil_config(struct vc5_job *job, struct vc5_surface *surf,
 430                           struct vc5_resource *rsc, bool is_separate_stencil)
 431 {
 432         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG, zs) {
 433                 zs.address = cl_address(rsc->bo, surf->offset);
 434
 435                 if (!is_separate_stencil) {
 436                         zs.internal_type = surf->internal_type;
 437                         zs.output_image_format = surf->format;
 438                 } else {
 439                         zs.z_stencil_id = 1; /* Separate stencil */
 440                 }
 441
 442                 zs.padded_height_of_output_image_in_uif_blocks =
 443                         surf->padded_height_of_output_image_in_uif_blocks;
 444
 445                 assert(surf->tiling != VC5_TILING_RASTER);
 446                 zs.memory_format = surf->tiling;
 447         }
 448
 449         if (job->resolve & (is_separate_stencil ?
 450                             PIPE_CLEAR_STENCIL :
 451                             PIPE_CLEAR_DEPTHSTENCIL)) {
 452                 rsc->writes++;
 453         }
 454 }
 455 #endif /* V3D_VERSION < 40 */
 456
 457 #define div_round_up(a, b) (((a) + (b) - 1) / b)
 458
 459 void
 460 v3dX(emit_rcl)(struct vc5_job *job)
 461 {
 462         /* The RCL list should be empty. */
 463         assert(!job->rcl.bo);
 464
 465         vc5_cl_ensure_space_with_branch(&job->rcl, 200 + 256 *
 466                                         cl_packet_length(SUPERTILE_COORDINATES));
 467         job->submit.rcl_start = job->rcl.bo->offset;
 468         vc5_job_add_bo(job, job->rcl.bo);
 469
 470         int nr_cbufs = 0;
 471         for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
 472                 if (job->cbufs[i])
 473                         nr_cbufs = i + 1;
 474         }
 475
 476         /* Comon config must be the first TILE_RENDERING_MODE_CONFIGURATION
 477          * and Z_STENCIL_CLEAR_VALUES must be last.  The ones in between are
 478          * optional updates to the previous HW state.
 479          */
 480         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION,
 481                 config) {
 482 #if V3D_VERSION < 40
 483                 config.enable_z_store = job->resolve & PIPE_CLEAR_DEPTH;
 484                 config.enable_stencil_store = job->resolve & PIPE_CLEAR_STENCIL;
 485 #else /* V3D_VERSION >= 40 */
 486                 if (job->zsbuf) {
 487                         struct vc5_surface *surf = vc5_surface(job->zsbuf);
 488                         config.internal_depth_type = surf->internal_type;
 489                 }
 490 #endif /* V3D_VERSION >= 40 */
 491
 492                 /* XXX: Early D/S clear */
 493
 494                 switch (job->first_ez_state) {
 495                 case VC5_EZ_UNDECIDED:
 496                 case VC5_EZ_LT_LE:
 497                         config.early_z_disable = false;
 498                         config.early_z_test_and_update_direction =
 499                                 EARLY_Z_DIRECTION_LT_LE;
 500                         break;
 501                 case VC5_EZ_GT_GE:
 502                         config.early_z_disable = false;
 503                         config.early_z_test_and_update_direction =
 504                                 EARLY_Z_DIRECTION_GT_GE;
 505                         break;
 506                 case VC5_EZ_DISABLED:
 507                         config.early_z_disable = true;
 508                 }
 509
 510                 config.image_width_pixels = job->draw_width;
 511                 config.image_height_pixels = job->draw_height;
 512
 513                 config.number_of_render_targets_minus_1 =
 514                         MAX2(nr_cbufs, 1) - 1;
 515
 516                 config.multisample_mode_4x = job->msaa;
 517
 518                 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
 519         }
 520
 521         for (int i = 0; i < nr_cbufs; i++) {
 522                 struct pipe_surface *psurf = job->cbufs[i];
 523                 if (!psurf)
 524                         continue;
 525                 struct vc5_surface *surf = vc5_surface(psurf);
 526                 struct vc5_resource *rsc = vc5_resource(psurf->texture);
 527
 528                 MAYBE_UNUSED uint32_t config_pad = 0;
 529                 uint32_t clear_pad = 0;
 530
 531                 /* XXX: Set the pad for raster. */
 532                 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
 533                     surf->tiling == VC5_TILING_UIF_XOR) {
 534                         int uif_block_height = vc5_utile_height(rsc->cpp) * 2;
 535                         uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
 536                                                            uif_block_height);
 537                         if (surf->padded_height_of_output_image_in_uif_blocks -
 538                             implicit_padded_height < 15) {
 539                                 config_pad = (surf->padded_height_of_output_image_in_uif_blocks -
 540                                               implicit_padded_height);
 541                         } else {
 542                                 config_pad = 15;
 543                                 clear_pad = surf->padded_height_of_output_image_in_uif_blocks;
 544                         }
 545                 }
 546
 547 #if V3D_VERSION < 40
 548                 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
 549                         rt.address = cl_address(rsc->bo, surf->offset);
 550                         rt.internal_type = surf->internal_type;
 551                         rt.output_image_format = surf->format;
 552                         rt.memory_format = surf->tiling;
 553                         rt.internal_bpp = surf->internal_bpp;
 554                         rt.render_target_number = i;
 555                         rt.pad = config_pad;
 556
 557                         if (job->resolve & PIPE_CLEAR_COLOR0 << i)
 558                                 rsc->writes++;
 559                 }
 560 #endif /* V3D_VERSION < 40 */
 561
 562                 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1,
 563                         clear) {
 564                         clear.clear_color_low_32_bits = job->clear_color[i][0];
 565                         clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
 566                         clear.render_target_number = i;
 567                 };
 568
 569                 if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
 570                         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2,
 571                                 clear) {
 572                                 clear.clear_color_mid_low_32_bits =
 573                                         ((job->clear_color[i][1] >> 24) |
 574                                          (job->clear_color[i][2] << 8));
 575                                 clear.clear_color_mid_high_24_bits =
 576                                         ((job->clear_color[i][2] >> 24) |
 577                                          ((job->clear_color[i][3] & 0xffff) << 8));
 578                                 clear.render_target_number = i;
 579                         };
 580                 }
 581
 582                 if (surf->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
 583                         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
 584                                 clear) {
 585                                 clear.uif_padded_height_in_uif_blocks = clear_pad;
 586                                 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
 587                                 clear.render_target_number = i;
 588                         };
 589                 }
 590         }
 591
 592 #if V3D_VERSION >= 40
 593         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
 594                 v3d_setup_render_target(job, 0,
 595                                         &rt.render_target_0_internal_bpp,
 596                                         &rt.render_target_0_internal_type,
 597                                         &rt.render_target_0_clamp);
 598                 v3d_setup_render_target(job, 1,
 599                                         &rt.render_target_1_internal_bpp,
 600                                         &rt.render_target_1_internal_type,
 601                                         &rt.render_target_1_clamp);
 602                 v3d_setup_render_target(job, 2,
 603                                         &rt.render_target_2_internal_bpp,
 604                                         &rt.render_target_2_internal_type,
 605                                         &rt.render_target_2_clamp);
 606                 v3d_setup_render_target(job, 3,
 607                                         &rt.render_target_3_internal_bpp,
 608                                         &rt.render_target_3_internal_type,
 609                                         &rt.render_target_3_clamp);
 610         }
 611 #endif
 612
 613 #if V3D_VERSION < 40
 614         /* TODO: Don't bother emitting if we don't load/clear Z/S. */
 615         if (job->zsbuf) {
 616                 struct pipe_surface *psurf = job->zsbuf;
 617                 struct vc5_surface *surf = vc5_surface(psurf);
 618                 struct vc5_resource *rsc = vc5_resource(psurf->texture);
 619
 620                 v3d_emit_z_stencil_config(job, surf, rsc, false);
 621
 622                 /* Emit the separate stencil packet if we have a resource for
 623                  * it.  The HW will only load/store this buffer if the
 624                  * Z/Stencil config doesn't have stencil in its format.
 625                  */
 626                 if (surf->separate_stencil) {
 627                         v3d_emit_z_stencil_config(job,
 628                                                   vc5_surface(surf->separate_stencil),
 629                                                   rsc->separate_stencil, true);
 630                 }
 631         }
 632 #endif /* V3D_VERSION < 40 */
 633
 634         /* Ends rendering mode config. */
 635         cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
 636                 clear) {
 637                 clear.z_clear_value = job->clear_z;
 638                 clear.stencil_vg_mask_clear_value = job->clear_s;
 639         };
 640
 641         /* Always set initial block size before the first branch, which needs
 642          * to match the value from binning mode config.
 643          */
 644         cl_emit(&job->rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
 645                 init.use_auto_chained_tile_lists = true;
 646                 init.size_of_first_block_in_chained_tile_lists =
 647                         TILE_ALLOCATION_BLOCK_SIZE_64B;
 648         }
 649
 650         uint32_t supertile_w = 1, supertile_h = 1;
 651
 652         /* If doing multicore binning, we would need to initialize each core's
 653          * tile list here.
 654          */
 655         cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
 656                 list.address = cl_address(job->tile_alloc, 0);
 657         }
 658
 659         cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION, config) {
 660                 uint32_t frame_w_in_supertiles, frame_h_in_supertiles;
 661                 const uint32_t max_supertiles = 256;
 662
 663                 /* Size up our supertiles until we get under the limit. */
 664                 for (;;) {
 665                         frame_w_in_supertiles = div_round_up(job->draw_tiles_x,
 666                                                              supertile_w);
 667                         frame_h_in_supertiles = div_round_up(job->draw_tiles_y,
 668                                                              supertile_h);
 669                         if (frame_w_in_supertiles * frame_h_in_supertiles <
 670                             max_supertiles) {
 671                                 break;
 672                         }
 673
 674                         if (supertile_w < supertile_h)
 675                                 supertile_w++;
 676                         else
 677                                 supertile_h++;
 678                 }
 679
 680                 config.total_frame_width_in_tiles = job->draw_tiles_x;
 681                 config.total_frame_height_in_tiles = job->draw_tiles_y;
 682
 683                 config.supertile_width_in_tiles_minus_1 = supertile_w - 1;
 684                 config.supertile_height_in_tiles_minus_1 = supertile_h - 1;
 685
 686                 config.total_frame_width_in_supertiles = frame_w_in_supertiles;
 687                 config.total_frame_height_in_supertiles = frame_h_in_supertiles;
 688         }
 689
 690         /* Start by clearing the tile buffer. */
 691         cl_emit(&job->rcl, TILE_COORDINATES, coords) {
 692                 coords.tile_column_number = 0;
 693                 coords.tile_row_number = 0;
 694         }
 695
 696 #if V3D_VERSION < 40
 697         cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
 698                 store.buffer_to_store = NONE;
 699         }
 700 #else
 701         cl_emit(&job->rcl, END_OF_LOADS, end);
 702         cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
 703                 store.buffer_to_store = NONE;
 704         }
 705         cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) {
 706                 clear.clear_z_stencil_buffer = true;
 707                 clear.clear_all_render_targets = true;
 708         }
 709         cl_emit(&job->rcl, END_OF_TILE_MARKER, end);
 710 #endif
 711
 712         cl_emit(&job->rcl, FLUSH_VCD_CACHE, flush);
 713
 714         vc5_rcl_emit_generic_per_tile_list(job, nr_cbufs - 1);
 715
 716         cl_emit(&job->rcl, WAIT_ON_SEMAPHORE, sem);
 717
 718         /* XXX: Use Morton order */
 719         uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
 720         uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
 721         uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
 722         uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
 723
 724         uint32_t max_x_supertile = 0;
 725         uint32_t max_y_supertile = 0;
 726         if (job->draw_max_x != 0 && job->draw_max_y != 0) {
 727                 max_x_supertile = (job->draw_max_x - 1) / supertile_w_in_pixels;
 728                 max_y_supertile = (job->draw_max_y - 1) / supertile_h_in_pixels;
 729         }
 730
 731         for (int y = min_y_supertile; y <= max_y_supertile; y++) {
 732                 for (int x = min_x_supertile; x <= max_x_supertile; x++) {
 733                         cl_emit(&job->rcl, SUPERTILE_COORDINATES, coords) {
 734                                 coords.column_number_in_supertiles = x;
 735                                 coords.row_number_in_supertiles = y;
 736                         }
 737                 }
 738         }
 739
 740         cl_emit(&job->rcl, END_OF_RENDERING, end);
 741 }