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[mesa.git] / src / gallium / drivers / vc5 / vc5_rcl.c
1 /*
2 * Copyright © 2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/u_format.h"
25 #include "vc5_context.h"
26 #include "vc5_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
29
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
31 PIPE_CLEAR_COLOR1 | \
32 PIPE_CLEAR_COLOR2 | \
33 PIPE_CLEAR_COLOR3) \
34
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
36
37 static void
38 load_general(struct vc5_cl *cl, struct pipe_surface *psurf, int buffer)
39 {
40 struct vc5_surface *surf = vc5_surface(psurf);
41 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
42 if (separate_stencil) {
43 psurf = surf->separate_stencil;
44 surf = vc5_surface(psurf);
45 }
46
47 struct vc5_resource *rsc = vc5_resource(psurf->texture);
48
49 cl_emit(cl, LOAD_TILE_BUFFER_GENERAL, load) {
50 load.buffer_to_load = buffer;
51 load.address = cl_address(rsc->bo, surf->offset);
52
53 #if V3D_VERSION >= 40
54 load.memory_format = surf->tiling;
55 if (separate_stencil)
56 load.input_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
57 else
58 load.input_image_format = surf->format;
59
60 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
61 surf->tiling == VC5_TILING_UIF_XOR) {
62 load.height_in_ub_or_stride =
63 surf->padded_height_of_output_image_in_uif_blocks;
64 } else if (surf->tiling == VC5_TILING_RASTER) {
65 struct vc5_resource_slice *slice =
66 &rsc->slices[psurf->u.tex.level];
67 load.height_in_ub_or_stride = slice->stride;
68 }
69
70 /* XXX: MSAA */
71 #else /* V3D_VERSION < 40 */
72 /* Can't do raw ZSTENCIL loads -- need to load/store them to
73 * separate buffers for Z and stencil.
74 */
75 assert(buffer != ZSTENCIL);
76 load.raw_mode = true;
77 load.padded_height_of_output_image_in_uif_blocks =
78 surf->padded_height_of_output_image_in_uif_blocks;
79 #endif /* V3D_VERSION < 40 */
80 }
81 }
82
83 static void
84 store_general(struct vc5_job *job,
85 struct vc5_cl *cl, struct pipe_surface *psurf, int buffer,
86 int pipe_bit, bool last_store, bool general_color_clear)
87 {
88 struct vc5_surface *surf = vc5_surface(psurf);
89 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
90 if (separate_stencil) {
91 psurf = surf->separate_stencil;
92 surf = vc5_surface(psurf);
93 }
94
95 struct vc5_resource *rsc = vc5_resource(psurf->texture);
96
97 rsc->writes++;
98
99 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
100 store.buffer_to_store = buffer;
101 store.address = cl_address(rsc->bo, surf->offset);
102
103 #if V3D_VERSION >= 40
104 store.clear_buffer_being_stored =
105 ((job->cleared & pipe_bit) &&
106 (general_color_clear ||
107 !(pipe_bit & PIPE_CLEAR_COLOR_BUFFERS)));
108
109 if (separate_stencil)
110 store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
111 else
112 store.output_image_format = surf->format;
113
114 store.memory_format = surf->tiling;
115
116 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
117 surf->tiling == VC5_TILING_UIF_XOR) {
118 store.height_in_ub_or_stride =
119 surf->padded_height_of_output_image_in_uif_blocks;
120 } else if (surf->tiling == VC5_TILING_RASTER) {
121 struct vc5_resource_slice *slice =
122 &rsc->slices[psurf->u.tex.level];
123 store.height_in_ub_or_stride = slice->stride;
124 }
125 #else /* V3D_VERSION < 40 */
126 /* Can't do raw ZSTENCIL stores -- need to load/store them to
127 * separate buffers for Z and stencil.
128 */
129 assert(buffer != ZSTENCIL);
130 store.raw_mode = true;
131 if (!last_store) {
132 store.disable_colour_buffers_clear_on_write = true;
133 store.disable_z_buffer_clear_on_write = true;
134 store.disable_stencil_buffer_clear_on_write = true;
135 } else {
136 store.disable_colour_buffers_clear_on_write =
137 !(((pipe_bit & PIPE_CLEAR_COLOR_BUFFERS) &&
138 general_color_clear &&
139 (job->cleared & pipe_bit)));
140 store.disable_z_buffer_clear_on_write =
141 !(job->cleared & PIPE_CLEAR_DEPTH);
142 store.disable_stencil_buffer_clear_on_write =
143 !(job->cleared & PIPE_CLEAR_STENCIL);
144 }
145 store.padded_height_of_output_image_in_uif_blocks =
146 surf->padded_height_of_output_image_in_uif_blocks;
147 #endif /* V3D_VERSION < 40 */
148 }
149 }
150
151 static int
152 zs_buffer_from_pipe_bits(int pipe_clear_bits)
153 {
154 switch (pipe_clear_bits & PIPE_CLEAR_DEPTHSTENCIL) {
155 case PIPE_CLEAR_DEPTHSTENCIL:
156 return ZSTENCIL;
157 case PIPE_CLEAR_DEPTH:
158 return Z;
159 case PIPE_CLEAR_STENCIL:
160 return STENCIL;
161 default:
162 return NONE;
163 }
164 }
165
166 /* The HW queues up the load until the tile coordinates show up, but can only
167 * track one at a time. If we need to do more than one load, then we need to
168 * flush out the previous load by emitting the tile coordinates and doing a
169 * dummy store.
170 */
171 static void
172 flush_last_load(struct vc5_cl *cl)
173 {
174 if (V3D_VERSION >= 40)
175 return;
176
177 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
178 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
179 store.buffer_to_store = NONE;
180 }
181 }
182
183 static void
184 vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
185 {
186 uint32_t read_but_not_cleared = job->resolve & ~job->cleared;
187
188 for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
189 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
190 if (!(read_but_not_cleared & bit))
191 continue;
192
193 struct pipe_surface *psurf = job->cbufs[i];
194 if (!psurf || (V3D_VERSION < 40 &&
195 psurf->texture->nr_samples <= 1)) {
196 continue;
197 }
198
199 load_general(cl, psurf, RENDER_TARGET_0 + i);
200 read_but_not_cleared &= ~bit;
201
202 if (read_but_not_cleared)
203 flush_last_load(cl);
204 }
205
206 if (read_but_not_cleared & PIPE_CLEAR_DEPTHSTENCIL &&
207 (V3D_VERSION >= 40 ||
208 (job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
209 load_general(cl, job->zsbuf,
210 zs_buffer_from_pipe_bits(read_but_not_cleared));
211 read_but_not_cleared &= ~PIPE_CLEAR_DEPTHSTENCIL;
212 if (read_but_not_cleared)
213 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
214 }
215
216 #if V3D_VERSION < 40
217 /* The initial reload will be queued until we get the
218 * tile coordinates.
219 */
220 if (read_but_not_cleared) {
221 cl_emit(cl, RELOAD_TILE_COLOUR_BUFFER, load) {
222 load.disable_colour_buffer_load =
223 (~read_but_not_cleared &
224 PIPE_CLEAR_COLOR_BUFFERS) >>
225 PIPE_FIRST_COLOR_BUFFER_BIT;
226 load.enable_z_load =
227 read_but_not_cleared & PIPE_CLEAR_DEPTH;
228 load.enable_stencil_load =
229 read_but_not_cleared & PIPE_CLEAR_STENCIL;
230 }
231 }
232 #else /* V3D_VERSION >= 40 */
233 assert(!read_but_not_cleared);
234 cl_emit(cl, END_OF_LOADS, end);
235 #endif
236 }
237
238 static void
239 vc5_rcl_emit_stores(struct vc5_job *job, struct vc5_cl *cl)
240 {
241 MAYBE_UNUSED bool needs_color_clear = job->cleared & PIPE_CLEAR_COLOR_BUFFERS;
242 MAYBE_UNUSED bool needs_z_clear = job->cleared & PIPE_CLEAR_DEPTH;
243 MAYBE_UNUSED bool needs_s_clear = job->cleared & PIPE_CLEAR_STENCIL;
244
245 /* For clearing color in a TLB general on V3D 3.3:
246 *
247 * - NONE buffer store clears all TLB color buffers.
248 * - color buffer store clears just the TLB color buffer being stored.
249 * - Z/S buffers store may not clear the TLB color buffer.
250 *
251 * And on V3D 4.1, we only have one flag for "clear the buffer being
252 * stored" in the general packet, and a separate packet to clear all
253 * color TLB buffers.
254 *
255 * As a result, we only bother flagging TLB color clears in a general
256 * packet when we don't have to emit a separate packet to clear all
257 * TLB color buffers.
258 */
259 bool general_color_clear = (needs_color_clear &&
260 (job->cleared & PIPE_CLEAR_COLOR_BUFFERS) ==
261 (job->resolve & PIPE_CLEAR_COLOR_BUFFERS));
262
263 uint32_t stores_pending = job->resolve;
264
265 /* For V3D 4.1, use general stores for all TLB stores.
266 *
267 * For V3D 3.3, we only use general stores to do raw stores for any
268 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
269 * pixel is a 2x2 quad, and the format will be that of the
270 * internal_type/internal_bpp, rather than the format from GL's
271 * perspective. Non-MSAA surfaces will use
272 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
273 */
274 for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
275 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
276 if (!(job->resolve & bit))
277 continue;
278
279 struct pipe_surface *psurf = job->cbufs[i];
280 if (!psurf ||
281 (V3D_VERSION < 40 && psurf->texture->nr_samples <= 1)) {
282 continue;
283 }
284
285 stores_pending &= ~bit;
286 store_general(job, cl, psurf, RENDER_TARGET_0 + i, bit,
287 !stores_pending, general_color_clear);
288 if (V3D_VERSION < 40 && stores_pending)
289 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
290 }
291
292 if (job->resolve & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
293 !(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
294 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
295 if (rsc->separate_stencil) {
296 if (job->resolve & PIPE_CLEAR_DEPTH) {
297 stores_pending &= ~PIPE_CLEAR_DEPTH;
298 store_general(job, cl, job->zsbuf, Z,
299 PIPE_CLEAR_DEPTH,
300 !stores_pending,
301 general_color_clear);
302 if (V3D_VERSION < 40 && stores_pending) {
303 cl_emit(cl, TILE_COORDINATES_IMPLICIT,
304 coords);
305 }
306 }
307
308 if (job->resolve & PIPE_CLEAR_STENCIL) {
309 stores_pending &= ~PIPE_CLEAR_STENCIL;
310 store_general(job, cl, job->zsbuf, STENCIL,
311 PIPE_CLEAR_STENCIL,
312 !stores_pending,
313 general_color_clear);
314 if (V3D_VERSION < 40 && stores_pending) {
315 cl_emit(cl, TILE_COORDINATES_IMPLICIT,
316 coords);
317 }
318 }
319 } else {
320 stores_pending &= ~PIPE_CLEAR_DEPTHSTENCIL;
321 store_general(job, cl, job->zsbuf,
322 zs_buffer_from_pipe_bits(job->resolve),
323 job->resolve & PIPE_CLEAR_DEPTHSTENCIL,
324 !stores_pending, general_color_clear);
325 if (V3D_VERSION < 40 && stores_pending) {
326 cl_emit(cl, TILE_COORDINATES_IMPLICIT,
327 coords);
328 }
329 }
330 }
331
332 if (stores_pending) {
333 #if V3D_VERSION < 40
334 cl_emit(cl, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
335
336 store.disable_color_buffer_write =
337 (~stores_pending >>
338 PIPE_FIRST_COLOR_BUFFER_BIT) & 0xf;
339 store.enable_z_write = stores_pending & PIPE_CLEAR_DEPTH;
340 store.enable_stencil_write = stores_pending & PIPE_CLEAR_STENCIL;
341
342 /* Note that when set this will clear all of the color
343 * buffers.
344 */
345 store.disable_colour_buffers_clear_on_write =
346 !needs_color_clear;
347 store.disable_z_buffer_clear_on_write =
348 !needs_z_clear;
349 store.disable_stencil_buffer_clear_on_write =
350 !needs_s_clear;
351 };
352 #else /* V3D_VERSION >= 40 */
353 unreachable("All color buffers should have been stored.");
354 #endif /* V3D_VERSION >= 40 */
355 } else if (needs_color_clear && !general_color_clear) {
356 /* If we didn't do our color clears in the general packet,
357 * then emit a packet to clear all the TLB color buffers now.
358 */
359 #if V3D_VERSION < 40
360 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
361 store.buffer_to_store = NONE;
362 }
363 #else /* V3D_VERSION >= 40 */
364 cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
365 clear.clear_all_render_targets = true;
366 }
367 #endif /* V3D_VERSION >= 40 */
368 }
369 }
370
371 static void
372 vc5_rcl_emit_generic_per_tile_list(struct vc5_job *job, int last_cbuf)
373 {
374 /* Emit the generic list in our indirect state -- the rcl will just
375 * have pointers into it.
376 */
377 struct vc5_cl *cl = &job->indirect;
378 vc5_cl_ensure_space(cl, 200, 1);
379 struct vc5_cl_reloc tile_list_start = cl_get_address(cl);
380
381 if (V3D_VERSION >= 40) {
382 /* V3D 4.x only requires a single tile coordinates, and
383 * END_OF_LOADS switches us between loading and rendering.
384 */
385 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
386 }
387
388 vc5_rcl_emit_loads(job, cl);
389
390 if (V3D_VERSION < 40) {
391 /* Tile Coordinates triggers the last reload and sets where
392 * the stores go. There must be one per store packet.
393 */
394 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
395 }
396
397 /* The binner starts out writing tiles assuming that the initial mode
398 * is triangles, so make sure that's the case.
399 */
400 cl_emit(cl, PRIMITIVE_LIST_FORMAT, fmt) {
401 fmt.data_type = LIST_INDEXED;
402 fmt.primitive_type = LIST_TRIANGLES;
403 }
404
405 cl_emit(cl, BRANCH_TO_IMPLICIT_TILE_LIST, branch);
406
407 vc5_rcl_emit_stores(job, cl);
408
409 #if V3D_VERSION >= 40
410 cl_emit(cl, END_OF_TILE_MARKER, end);
411 #endif
412
413 cl_emit(cl, RETURN_FROM_SUB_LIST, ret);
414
415 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
416 branch.start = tile_list_start;
417 branch.end = cl_get_address(cl);
418 }
419 }
420
421 #if V3D_VERSION >= 40
422 static void
423 v3d_setup_render_target(struct vc5_job *job, int cbuf,
424 uint32_t *rt_bpp, uint32_t *rt_type, uint32_t *rt_clamp)
425 {
426 if (!job->cbufs[cbuf])
427 return;
428
429 struct vc5_surface *surf = vc5_surface(job->cbufs[cbuf]);
430 *rt_bpp = surf->internal_bpp;
431 *rt_type = surf->internal_type;
432 *rt_clamp = V3D_RENDER_TARGET_CLAMP_NONE;
433 }
434
435 #else /* V3D_VERSION < 40 */
436
437 static void
438 v3d_emit_z_stencil_config(struct vc5_job *job, struct vc5_surface *surf,
439 struct vc5_resource *rsc, bool is_separate_stencil)
440 {
441 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG, zs) {
442 zs.address = cl_address(rsc->bo, surf->offset);
443
444 if (!is_separate_stencil) {
445 zs.internal_type = surf->internal_type;
446 zs.output_image_format = surf->format;
447 } else {
448 zs.z_stencil_id = 1; /* Separate stencil */
449 }
450
451 zs.padded_height_of_output_image_in_uif_blocks =
452 surf->padded_height_of_output_image_in_uif_blocks;
453
454 assert(surf->tiling != VC5_TILING_RASTER);
455 zs.memory_format = surf->tiling;
456 }
457
458 if (job->resolve & (is_separate_stencil ?
459 PIPE_CLEAR_STENCIL :
460 PIPE_CLEAR_DEPTHSTENCIL)) {
461 rsc->writes++;
462 }
463 }
464 #endif /* V3D_VERSION < 40 */
465
466 #define div_round_up(a, b) (((a) + (b) - 1) / b)
467
468 void
469 v3dX(emit_rcl)(struct vc5_job *job)
470 {
471 /* The RCL list should be empty. */
472 assert(!job->rcl.bo);
473
474 vc5_cl_ensure_space_with_branch(&job->rcl, 200 + 256 *
475 cl_packet_length(SUPERTILE_COORDINATES));
476 job->submit.rcl_start = job->rcl.bo->offset;
477 vc5_job_add_bo(job, job->rcl.bo);
478
479 int nr_cbufs = 0;
480 for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
481 if (job->cbufs[i])
482 nr_cbufs = i + 1;
483 }
484
485 /* Comon config must be the first TILE_RENDERING_MODE_CONFIGURATION
486 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
487 * optional updates to the previous HW state.
488 */
489 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION,
490 config) {
491 #if V3D_VERSION < 40
492 config.enable_z_store = job->resolve & PIPE_CLEAR_DEPTH;
493 config.enable_stencil_store = job->resolve & PIPE_CLEAR_STENCIL;
494 #else /* V3D_VERSION >= 40 */
495 if (job->zsbuf) {
496 struct vc5_surface *surf = vc5_surface(job->zsbuf);
497 config.internal_depth_type = surf->internal_type;
498 }
499 #endif /* V3D_VERSION >= 40 */
500
501 /* XXX: Early D/S clear */
502
503 switch (job->first_ez_state) {
504 case VC5_EZ_UNDECIDED:
505 case VC5_EZ_LT_LE:
506 config.early_z_disable = false;
507 config.early_z_test_and_update_direction =
508 EARLY_Z_DIRECTION_LT_LE;
509 break;
510 case VC5_EZ_GT_GE:
511 config.early_z_disable = false;
512 config.early_z_test_and_update_direction =
513 EARLY_Z_DIRECTION_GT_GE;
514 break;
515 case VC5_EZ_DISABLED:
516 config.early_z_disable = true;
517 }
518
519 config.image_width_pixels = job->draw_width;
520 config.image_height_pixels = job->draw_height;
521
522 config.number_of_render_targets_minus_1 =
523 MAX2(nr_cbufs, 1) - 1;
524
525 config.multisample_mode_4x = job->msaa;
526
527 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
528 }
529
530 for (int i = 0; i < nr_cbufs; i++) {
531 struct pipe_surface *psurf = job->cbufs[i];
532 if (!psurf)
533 continue;
534 struct vc5_surface *surf = vc5_surface(psurf);
535 struct vc5_resource *rsc = vc5_resource(psurf->texture);
536
537 MAYBE_UNUSED uint32_t config_pad = 0;
538 uint32_t clear_pad = 0;
539
540 /* XXX: Set the pad for raster. */
541 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
542 surf->tiling == VC5_TILING_UIF_XOR) {
543 int uif_block_height = vc5_utile_height(rsc->cpp) * 2;
544 uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
545 uif_block_height);
546 if (surf->padded_height_of_output_image_in_uif_blocks -
547 implicit_padded_height < 15) {
548 config_pad = (surf->padded_height_of_output_image_in_uif_blocks -
549 implicit_padded_height);
550 } else {
551 config_pad = 15;
552 clear_pad = surf->padded_height_of_output_image_in_uif_blocks;
553 }
554 }
555
556 #if V3D_VERSION < 40
557 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
558 rt.address = cl_address(rsc->bo, surf->offset);
559 rt.internal_type = surf->internal_type;
560 rt.output_image_format = surf->format;
561 rt.memory_format = surf->tiling;
562 rt.internal_bpp = surf->internal_bpp;
563 rt.render_target_number = i;
564 rt.pad = config_pad;
565
566 if (job->resolve & PIPE_CLEAR_COLOR0 << i)
567 rsc->writes++;
568 }
569 #endif /* V3D_VERSION < 40 */
570
571 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1,
572 clear) {
573 clear.clear_color_low_32_bits = job->clear_color[i][0];
574 clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
575 clear.render_target_number = i;
576 };
577
578 if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
579 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2,
580 clear) {
581 clear.clear_color_mid_low_32_bits =
582 ((job->clear_color[i][1] >> 24) |
583 (job->clear_color[i][2] << 8));
584 clear.clear_color_mid_high_24_bits =
585 ((job->clear_color[i][2] >> 24) |
586 ((job->clear_color[i][3] & 0xffff) << 8));
587 clear.render_target_number = i;
588 };
589 }
590
591 if (surf->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
592 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
593 clear) {
594 clear.uif_padded_height_in_uif_blocks = clear_pad;
595 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
596 clear.render_target_number = i;
597 };
598 }
599 }
600
601 #if V3D_VERSION >= 40
602 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
603 v3d_setup_render_target(job, 0,
604 &rt.render_target_0_internal_bpp,
605 &rt.render_target_0_internal_type,
606 &rt.render_target_0_clamp);
607 v3d_setup_render_target(job, 1,
608 &rt.render_target_1_internal_bpp,
609 &rt.render_target_1_internal_type,
610 &rt.render_target_1_clamp);
611 v3d_setup_render_target(job, 2,
612 &rt.render_target_2_internal_bpp,
613 &rt.render_target_2_internal_type,
614 &rt.render_target_2_clamp);
615 v3d_setup_render_target(job, 3,
616 &rt.render_target_3_internal_bpp,
617 &rt.render_target_3_internal_type,
618 &rt.render_target_3_clamp);
619 }
620 #endif
621
622 #if V3D_VERSION < 40
623 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
624 if (job->zsbuf) {
625 struct pipe_surface *psurf = job->zsbuf;
626 struct vc5_surface *surf = vc5_surface(psurf);
627 struct vc5_resource *rsc = vc5_resource(psurf->texture);
628
629 v3d_emit_z_stencil_config(job, surf, rsc, false);
630
631 /* Emit the separate stencil packet if we have a resource for
632 * it. The HW will only load/store this buffer if the
633 * Z/Stencil config doesn't have stencil in its format.
634 */
635 if (surf->separate_stencil) {
636 v3d_emit_z_stencil_config(job,
637 vc5_surface(surf->separate_stencil),
638 rsc->separate_stencil, true);
639 }
640 }
641 #endif /* V3D_VERSION < 40 */
642
643 /* Ends rendering mode config. */
644 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
645 clear) {
646 clear.z_clear_value = job->clear_z;
647 clear.stencil_vg_mask_clear_value = job->clear_s;
648 };
649
650 /* Always set initial block size before the first branch, which needs
651 * to match the value from binning mode config.
652 */
653 cl_emit(&job->rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
654 init.use_auto_chained_tile_lists = true;
655 init.size_of_first_block_in_chained_tile_lists =
656 TILE_ALLOCATION_BLOCK_SIZE_64B;
657 }
658
659 uint32_t supertile_w = 1, supertile_h = 1;
660
661 /* If doing multicore binning, we would need to initialize each core's
662 * tile list here.
663 */
664 cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
665 list.address = cl_address(job->tile_alloc, 0);
666 }
667
668 cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION, config) {
669 uint32_t frame_w_in_supertiles, frame_h_in_supertiles;
670 const uint32_t max_supertiles = 256;
671
672 /* Size up our supertiles until we get under the limit. */
673 for (;;) {
674 frame_w_in_supertiles = div_round_up(job->draw_tiles_x,
675 supertile_w);
676 frame_h_in_supertiles = div_round_up(job->draw_tiles_y,
677 supertile_h);
678 if (frame_w_in_supertiles * frame_h_in_supertiles <
679 max_supertiles) {
680 break;
681 }
682
683 if (supertile_w < supertile_h)
684 supertile_w++;
685 else
686 supertile_h++;
687 }
688
689 config.total_frame_width_in_tiles = job->draw_tiles_x;
690 config.total_frame_height_in_tiles = job->draw_tiles_y;
691
692 config.supertile_width_in_tiles_minus_1 = supertile_w - 1;
693 config.supertile_height_in_tiles_minus_1 = supertile_h - 1;
694
695 config.total_frame_width_in_supertiles = frame_w_in_supertiles;
696 config.total_frame_height_in_supertiles = frame_h_in_supertiles;
697 }
698
699 /* Start by clearing the tile buffer. */
700 cl_emit(&job->rcl, TILE_COORDINATES, coords) {
701 coords.tile_column_number = 0;
702 coords.tile_row_number = 0;
703 }
704
705 #if V3D_VERSION < 40
706 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
707 store.buffer_to_store = NONE;
708 }
709 #else
710 cl_emit(&job->rcl, END_OF_LOADS, end);
711 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
712 store.buffer_to_store = NONE;
713 }
714 cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) {
715 clear.clear_z_stencil_buffer = true;
716 clear.clear_all_render_targets = true;
717 }
718 cl_emit(&job->rcl, END_OF_TILE_MARKER, end);
719 #endif
720
721 cl_emit(&job->rcl, FLUSH_VCD_CACHE, flush);
722
723 vc5_rcl_emit_generic_per_tile_list(job, nr_cbufs - 1);
724
725 cl_emit(&job->rcl, WAIT_ON_SEMAPHORE, sem);
726
727 /* XXX: Use Morton order */
728 uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
729 uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
730 uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
731 uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
732
733 uint32_t max_x_supertile = 0;
734 uint32_t max_y_supertile = 0;
735 if (job->draw_max_x != 0 && job->draw_max_y != 0) {
736 max_x_supertile = (job->draw_max_x - 1) / supertile_w_in_pixels;
737 max_y_supertile = (job->draw_max_y - 1) / supertile_h_in_pixels;
738 }
739
740 for (int y = min_y_supertile; y <= max_y_supertile; y++) {
741 for (int x = min_x_supertile; x <= max_x_supertile; x++) {
742 cl_emit(&job->rcl, SUPERTILE_COORDINATES, coords) {
743 coords.column_number_in_supertiles = x;
744 coords.row_number_in_supertiles = y;
745 }
746 }
747 }
748
749 cl_emit(&job->rcl, END_OF_RENDERING, end);
750 }