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[mesa.git] / src / gallium / drivers / vc5 / vc5_rcl.c
1 /*
2 * Copyright © 2017 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "util/u_format.h"
25 #include "vc5_context.h"
26 #include "vc5_tiling.h"
27 #include "broadcom/common/v3d_macros.h"
28 #include "broadcom/cle/v3dx_pack.h"
29
30 #define PIPE_CLEAR_COLOR_BUFFERS (PIPE_CLEAR_COLOR0 | \
31 PIPE_CLEAR_COLOR1 | \
32 PIPE_CLEAR_COLOR2 | \
33 PIPE_CLEAR_COLOR3) \
34
35 #define PIPE_FIRST_COLOR_BUFFER_BIT (ffs(PIPE_CLEAR_COLOR0) - 1)
36
37 static void
38 load_general(struct vc5_cl *cl, struct pipe_surface *psurf, int buffer)
39 {
40 struct vc5_surface *surf = vc5_surface(psurf);
41 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
42 if (separate_stencil) {
43 psurf = surf->separate_stencil;
44 surf = vc5_surface(psurf);
45 }
46
47 struct vc5_resource *rsc = vc5_resource(psurf->texture);
48
49 cl_emit(cl, LOAD_TILE_BUFFER_GENERAL, load) {
50 load.buffer_to_load = buffer;
51 load.address = cl_address(rsc->bo, surf->offset);
52
53 #if V3D_VERSION >= 40
54 load.memory_format = surf->tiling;
55 if (separate_stencil)
56 load.input_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
57 else
58 load.input_image_format = surf->format;
59
60 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
61 surf->tiling == VC5_TILING_UIF_XOR) {
62 load.height_in_ub_or_stride =
63 surf->padded_height_of_output_image_in_uif_blocks;
64 } else if (surf->tiling == VC5_TILING_RASTER) {
65 struct vc5_resource_slice *slice =
66 &rsc->slices[psurf->u.tex.level];
67 load.height_in_ub_or_stride = slice->stride;
68 }
69
70 /* XXX: MSAA */
71 #else /* V3D_VERSION < 40 */
72 load.raw_mode = true;
73 load.padded_height_of_output_image_in_uif_blocks =
74 surf->padded_height_of_output_image_in_uif_blocks;
75 #endif /* V3D_VERSION < 40 */
76 }
77 }
78
79 static void
80 store_general(struct vc5_job *job,
81 struct vc5_cl *cl, struct pipe_surface *psurf, int buffer,
82 int pipe_bit, bool last_store, bool general_color_clear)
83 {
84 struct vc5_surface *surf = vc5_surface(psurf);
85 bool separate_stencil = surf->separate_stencil && buffer == STENCIL;
86 if (separate_stencil) {
87 psurf = surf->separate_stencil;
88 surf = vc5_surface(psurf);
89 }
90
91 struct vc5_resource *rsc = vc5_resource(psurf->texture);
92
93 rsc->writes++;
94
95 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
96 store.buffer_to_store = buffer;
97 store.address = cl_address(rsc->bo, surf->offset);
98
99 #if V3D_VERSION >= 40
100 store.clear_buffer_being_stored =
101 ((job->cleared & pipe_bit) &&
102 (general_color_clear ||
103 !(pipe_bit & PIPE_CLEAR_COLOR_BUFFERS)));
104
105 if (separate_stencil)
106 store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
107 else
108 store.output_image_format = surf->format;
109
110 store.memory_format = surf->tiling;
111
112 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
113 surf->tiling == VC5_TILING_UIF_XOR) {
114 store.height_in_ub_or_stride =
115 surf->padded_height_of_output_image_in_uif_blocks;
116 } else if (surf->tiling == VC5_TILING_RASTER) {
117 struct vc5_resource_slice *slice =
118 &rsc->slices[psurf->u.tex.level];
119 store.height_in_ub_or_stride = slice->stride;
120 }
121 #else /* V3D_VERSION < 40 */
122 store.raw_mode = true;
123 if (!last_store) {
124 store.disable_colour_buffers_clear_on_write = true;
125 store.disable_z_buffer_clear_on_write = true;
126 store.disable_stencil_buffer_clear_on_write = true;
127 } else {
128 store.disable_colour_buffers_clear_on_write =
129 !(((pipe_bit & PIPE_CLEAR_COLOR_BUFFERS) &&
130 general_color_clear &&
131 (job->cleared & pipe_bit)));
132 store.disable_z_buffer_clear_on_write =
133 !(job->cleared & PIPE_CLEAR_DEPTH);
134 store.disable_stencil_buffer_clear_on_write =
135 !(job->cleared & PIPE_CLEAR_STENCIL);
136 }
137 store.padded_height_of_output_image_in_uif_blocks =
138 surf->padded_height_of_output_image_in_uif_blocks;
139 #endif /* V3D_VERSION < 40 */
140 }
141 }
142
143 static int
144 zs_buffer_from_pipe_bits(int pipe_clear_bits)
145 {
146 switch (pipe_clear_bits & PIPE_CLEAR_DEPTHSTENCIL) {
147 case PIPE_CLEAR_DEPTHSTENCIL:
148 return ZSTENCIL;
149 case PIPE_CLEAR_DEPTH:
150 return Z;
151 case PIPE_CLEAR_STENCIL:
152 return STENCIL;
153 default:
154 return NONE;
155 }
156 }
157
158 /* The HW queues up the load until the tile coordinates show up, but can only
159 * track one at a time. If we need to do more than one load, then we need to
160 * flush out the previous load by emitting the tile coordinates and doing a
161 * dummy store.
162 */
163 static void
164 flush_last_load(struct vc5_cl *cl)
165 {
166 if (V3D_VERSION >= 40)
167 return;
168
169 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
170 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
171 store.buffer_to_store = NONE;
172 }
173 }
174
175 static void
176 vc5_rcl_emit_loads(struct vc5_job *job, struct vc5_cl *cl)
177 {
178 uint32_t read_but_not_cleared = job->resolve & ~job->cleared;
179
180 for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
181 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
182 if (!(read_but_not_cleared & bit))
183 continue;
184
185 struct pipe_surface *psurf = job->cbufs[i];
186 if (!psurf || (V3D_VERSION < 40 &&
187 psurf->texture->nr_samples <= 1)) {
188 continue;
189 }
190
191 load_general(cl, psurf, RENDER_TARGET_0 + i);
192 read_but_not_cleared &= ~bit;
193
194 if (read_but_not_cleared)
195 flush_last_load(cl);
196 }
197
198 if (read_but_not_cleared & PIPE_CLEAR_DEPTHSTENCIL &&
199 (V3D_VERSION >= 40 ||
200 (job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
201 load_general(cl, job->zsbuf,
202 zs_buffer_from_pipe_bits(read_but_not_cleared));
203 read_but_not_cleared &= ~PIPE_CLEAR_DEPTHSTENCIL;
204 if (read_but_not_cleared)
205 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
206 }
207
208 #if V3D_VERSION < 40
209 /* The initial reload will be queued until we get the
210 * tile coordinates.
211 */
212 if (read_but_not_cleared) {
213 cl_emit(cl, RELOAD_TILE_COLOUR_BUFFER, load) {
214 load.disable_colour_buffer_load =
215 (~read_but_not_cleared &
216 PIPE_CLEAR_COLOR_BUFFERS) >>
217 PIPE_FIRST_COLOR_BUFFER_BIT;
218 load.enable_z_load =
219 read_but_not_cleared & PIPE_CLEAR_DEPTH;
220 load.enable_stencil_load =
221 read_but_not_cleared & PIPE_CLEAR_STENCIL;
222 }
223 }
224 #else /* V3D_VERSION >= 40 */
225 assert(!read_but_not_cleared);
226 cl_emit(cl, END_OF_LOADS, end);
227 #endif
228 }
229
230 static void
231 vc5_rcl_emit_stores(struct vc5_job *job, struct vc5_cl *cl)
232 {
233 MAYBE_UNUSED bool needs_color_clear = job->cleared & PIPE_CLEAR_COLOR_BUFFERS;
234 MAYBE_UNUSED bool needs_z_clear = job->cleared & PIPE_CLEAR_DEPTH;
235 MAYBE_UNUSED bool needs_s_clear = job->cleared & PIPE_CLEAR_STENCIL;
236
237 /* For clearing color in a TLB general on V3D 3.3:
238 *
239 * - NONE buffer store clears all TLB color buffers.
240 * - color buffer store clears just the TLB color buffer being stored.
241 * - Z/S buffers store may not clear the TLB color buffer.
242 *
243 * And on V3D 4.1, we only have one flag for "clear the buffer being
244 * stored" in the general packet, and a separate packet to clear all
245 * color TLB buffers.
246 *
247 * As a result, we only bother flagging TLB color clears in a general
248 * packet when we don't have to emit a separate packet to clear all
249 * TLB color buffers.
250 */
251 bool general_color_clear = (needs_color_clear &&
252 (job->cleared & PIPE_CLEAR_COLOR_BUFFERS) ==
253 (job->resolve & PIPE_CLEAR_COLOR_BUFFERS));
254
255 uint32_t stores_pending = job->resolve;
256
257 /* For V3D 4.1, use general stores for all TLB stores.
258 *
259 * For V3D 3.3, we only use general stores to do raw stores for any
260 * MSAA surfaces. These output UIF tiled images where each 4x MSAA
261 * pixel is a 2x2 quad, and the format will be that of the
262 * internal_type/internal_bpp, rather than the format from GL's
263 * perspective. Non-MSAA surfaces will use
264 * STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED.
265 */
266 for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
267 uint32_t bit = PIPE_CLEAR_COLOR0 << i;
268 if (!(job->resolve & bit))
269 continue;
270
271 struct pipe_surface *psurf = job->cbufs[i];
272 if (!psurf ||
273 (V3D_VERSION < 40 && psurf->texture->nr_samples <= 1)) {
274 continue;
275 }
276
277 stores_pending &= ~bit;
278 store_general(job, cl, psurf, RENDER_TARGET_0 + i, bit,
279 !stores_pending, general_color_clear);
280 if (V3D_VERSION < 40 && stores_pending)
281 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
282 }
283
284 if (job->resolve & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
285 !(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
286 stores_pending &= ~PIPE_CLEAR_DEPTHSTENCIL;
287
288 struct vc5_resource *rsc = vc5_resource(job->zsbuf->texture);
289 if (rsc->separate_stencil) {
290 if (job->resolve & PIPE_CLEAR_DEPTH) {
291 store_general(job, cl, job->zsbuf, Z,
292 PIPE_CLEAR_DEPTH,
293 !stores_pending,
294 general_color_clear);
295 }
296 if (job->resolve & PIPE_CLEAR_STENCIL) {
297 store_general(job, cl, job->zsbuf, STENCIL,
298 PIPE_CLEAR_STENCIL,
299 !stores_pending,
300 general_color_clear);
301 }
302 } else {
303 store_general(job, cl, job->zsbuf,
304 zs_buffer_from_pipe_bits(job->resolve),
305 job->resolve & PIPE_CLEAR_DEPTHSTENCIL,
306 !stores_pending, general_color_clear);
307 }
308
309 if (V3D_VERSION < 40 && stores_pending)
310 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
311 }
312
313 if (stores_pending) {
314 #if V3D_VERSION < 40
315 cl_emit(cl, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
316
317 store.disable_color_buffer_write =
318 (~stores_pending >>
319 PIPE_FIRST_COLOR_BUFFER_BIT) & 0xf;
320 store.enable_z_write = stores_pending & PIPE_CLEAR_DEPTH;
321 store.enable_stencil_write = stores_pending & PIPE_CLEAR_STENCIL;
322
323 /* Note that when set this will clear all of the color
324 * buffers.
325 */
326 store.disable_colour_buffers_clear_on_write =
327 !needs_color_clear;
328 store.disable_z_buffer_clear_on_write =
329 !needs_z_clear;
330 store.disable_stencil_buffer_clear_on_write =
331 !needs_s_clear;
332 };
333 #else /* V3D_VERSION >= 40 */
334 unreachable("All color buffers should have been stored.");
335 #endif /* V3D_VERSION >= 40 */
336 } else if (needs_color_clear && !general_color_clear) {
337 /* If we didn't do our color clears in the general packet,
338 * then emit a packet to clear all the TLB color buffers now.
339 */
340 #if V3D_VERSION < 40
341 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
342 store.buffer_to_store = NONE;
343 }
344 #else /* V3D_VERSION >= 40 */
345 cl_emit(cl, CLEAR_TILE_BUFFERS, clear) {
346 clear.clear_all_render_targets = true;
347 }
348 #endif /* V3D_VERSION >= 40 */
349 }
350 }
351
352 static void
353 vc5_rcl_emit_generic_per_tile_list(struct vc5_job *job, int last_cbuf)
354 {
355 /* Emit the generic list in our indirect state -- the rcl will just
356 * have pointers into it.
357 */
358 struct vc5_cl *cl = &job->indirect;
359 vc5_cl_ensure_space(cl, 200, 1);
360 struct vc5_cl_reloc tile_list_start = cl_get_address(cl);
361
362 if (V3D_VERSION >= 40) {
363 /* V3D 4.x only requires a single tile coordinates, and
364 * END_OF_LOADS switches us between loading and rendering.
365 */
366 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
367 }
368
369 vc5_rcl_emit_loads(job, cl);
370
371 if (V3D_VERSION < 40) {
372 /* Tile Coordinates triggers the last reload and sets where
373 * the stores go. There must be one per store packet.
374 */
375 cl_emit(cl, TILE_COORDINATES_IMPLICIT, coords);
376 }
377
378 /* The binner starts out writing tiles assuming that the initial mode
379 * is triangles, so make sure that's the case.
380 */
381 cl_emit(cl, PRIMITIVE_LIST_FORMAT, fmt) {
382 fmt.data_type = LIST_INDEXED;
383 fmt.primitive_type = LIST_TRIANGLES;
384 }
385
386 cl_emit(cl, BRANCH_TO_IMPLICIT_TILE_LIST, branch);
387
388 vc5_rcl_emit_stores(job, cl);
389
390 #if V3D_VERSION >= 40
391 cl_emit(cl, END_OF_TILE_MARKER, end);
392 #endif
393
394 cl_emit(cl, RETURN_FROM_SUB_LIST, ret);
395
396 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
397 branch.start = tile_list_start;
398 branch.end = cl_get_address(cl);
399 }
400 }
401
402 #if V3D_VERSION >= 40
403 static void
404 v3d_setup_render_target(struct vc5_job *job, int cbuf,
405 uint32_t *rt_bpp, uint32_t *rt_type, uint32_t *rt_clamp)
406 {
407 if (!job->cbufs[cbuf])
408 return;
409
410 struct vc5_surface *surf = vc5_surface(job->cbufs[cbuf]);
411 *rt_bpp = surf->internal_bpp;
412 *rt_type = surf->internal_type;
413 *rt_clamp = V3D_RENDER_TARGET_CLAMP_NONE;
414 }
415
416 #else /* V3D_VERSION < 40 */
417
418 static void
419 v3d_emit_z_stencil_config(struct vc5_job *job, struct vc5_surface *surf,
420 struct vc5_resource *rsc, bool is_separate_stencil)
421 {
422 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CONFIG, zs) {
423 zs.address = cl_address(rsc->bo, surf->offset);
424
425 if (!is_separate_stencil) {
426 zs.internal_type = surf->internal_type;
427 zs.output_image_format = surf->format;
428 } else {
429 zs.z_stencil_id = 1; /* Separate stencil */
430 }
431
432 zs.padded_height_of_output_image_in_uif_blocks =
433 surf->padded_height_of_output_image_in_uif_blocks;
434
435 assert(surf->tiling != VC5_TILING_RASTER);
436 zs.memory_format = surf->tiling;
437 }
438
439 if (job->resolve & (is_separate_stencil ?
440 PIPE_CLEAR_STENCIL :
441 PIPE_CLEAR_DEPTHSTENCIL)) {
442 rsc->writes++;
443 }
444 }
445 #endif /* V3D_VERSION < 40 */
446
447 #define div_round_up(a, b) (((a) + (b) - 1) / b)
448
449 void
450 v3dX(emit_rcl)(struct vc5_job *job)
451 {
452 /* The RCL list should be empty. */
453 assert(!job->rcl.bo);
454
455 vc5_cl_ensure_space_with_branch(&job->rcl, 200 + 256 *
456 cl_packet_length(SUPERTILE_COORDINATES));
457 job->submit.rcl_start = job->rcl.bo->offset;
458 vc5_job_add_bo(job, job->rcl.bo);
459
460 int nr_cbufs = 0;
461 for (int i = 0; i < VC5_MAX_DRAW_BUFFERS; i++) {
462 if (job->cbufs[i])
463 nr_cbufs = i + 1;
464 }
465
466 /* Comon config must be the first TILE_RENDERING_MODE_CONFIGURATION
467 * and Z_STENCIL_CLEAR_VALUES must be last. The ones in between are
468 * optional updates to the previous HW state.
469 */
470 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION,
471 config) {
472 #if V3D_VERSION < 40
473 config.enable_z_store = job->resolve & PIPE_CLEAR_DEPTH;
474 config.enable_stencil_store = job->resolve & PIPE_CLEAR_STENCIL;
475 #else /* V3D_VERSION >= 40 */
476 if (job->zsbuf) {
477 struct vc5_surface *surf = vc5_surface(job->zsbuf);
478 config.internal_depth_type = surf->internal_type;
479 }
480 #endif /* V3D_VERSION >= 40 */
481
482 /* XXX: Early D/S clear */
483
484 config.early_z_disable = !job->uses_early_z;
485
486 config.image_width_pixels = job->draw_width;
487 config.image_height_pixels = job->draw_height;
488
489 config.number_of_render_targets_minus_1 =
490 MAX2(nr_cbufs, 1) - 1;
491
492 config.multisample_mode_4x = job->msaa;
493
494 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
495 }
496
497 for (int i = 0; i < nr_cbufs; i++) {
498 struct pipe_surface *psurf = job->cbufs[i];
499 if (!psurf)
500 continue;
501 struct vc5_surface *surf = vc5_surface(psurf);
502 struct vc5_resource *rsc = vc5_resource(psurf->texture);
503
504 MAYBE_UNUSED uint32_t config_pad = 0;
505 uint32_t clear_pad = 0;
506
507 /* XXX: Set the pad for raster. */
508 if (surf->tiling == VC5_TILING_UIF_NO_XOR ||
509 surf->tiling == VC5_TILING_UIF_XOR) {
510 int uif_block_height = vc5_utile_height(rsc->cpp) * 2;
511 uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
512 uif_block_height);
513 if (surf->padded_height_of_output_image_in_uif_blocks -
514 implicit_padded_height < 15) {
515 config_pad = (surf->padded_height_of_output_image_in_uif_blocks -
516 implicit_padded_height);
517 } else {
518 config_pad = 15;
519 clear_pad = surf->padded_height_of_output_image_in_uif_blocks;
520 }
521 }
522
523 #if V3D_VERSION < 40
524 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
525 rt.address = cl_address(rsc->bo, surf->offset);
526 rt.internal_type = surf->internal_type;
527 rt.output_image_format = surf->format;
528 rt.memory_format = surf->tiling;
529 rt.internal_bpp = surf->internal_bpp;
530 rt.render_target_number = i;
531 rt.pad = config_pad;
532
533 if (job->resolve & PIPE_CLEAR_COLOR0 << i)
534 rsc->writes++;
535 }
536 #endif /* V3D_VERSION < 40 */
537
538 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1,
539 clear) {
540 clear.clear_color_low_32_bits = job->clear_color[i][0];
541 clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
542 clear.render_target_number = i;
543 };
544
545 if (surf->internal_bpp >= V3D_INTERNAL_BPP_64) {
546 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2,
547 clear) {
548 clear.clear_color_mid_low_32_bits =
549 ((job->clear_color[i][1] >> 24) |
550 (job->clear_color[i][2] << 8));
551 clear.clear_color_mid_high_24_bits =
552 ((job->clear_color[i][2] >> 24) |
553 ((job->clear_color[i][3] & 0xffff) << 8));
554 clear.render_target_number = i;
555 };
556 }
557
558 if (surf->internal_bpp >= V3D_INTERNAL_BPP_128 || clear_pad) {
559 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3,
560 clear) {
561 clear.uif_padded_height_in_uif_blocks = clear_pad;
562 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
563 clear.render_target_number = i;
564 };
565 }
566 }
567
568 #if V3D_VERSION >= 40
569 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) {
570 v3d_setup_render_target(job, 0,
571 &rt.render_target_0_internal_bpp,
572 &rt.render_target_0_internal_type,
573 &rt.render_target_0_clamp);
574 v3d_setup_render_target(job, 1,
575 &rt.render_target_1_internal_bpp,
576 &rt.render_target_1_internal_type,
577 &rt.render_target_1_clamp);
578 v3d_setup_render_target(job, 2,
579 &rt.render_target_2_internal_bpp,
580 &rt.render_target_2_internal_type,
581 &rt.render_target_2_clamp);
582 v3d_setup_render_target(job, 3,
583 &rt.render_target_3_internal_bpp,
584 &rt.render_target_3_internal_type,
585 &rt.render_target_3_clamp);
586 }
587 #endif
588
589 #if V3D_VERSION < 40
590 /* TODO: Don't bother emitting if we don't load/clear Z/S. */
591 if (job->zsbuf) {
592 struct pipe_surface *psurf = job->zsbuf;
593 struct vc5_surface *surf = vc5_surface(psurf);
594 struct vc5_resource *rsc = vc5_resource(psurf->texture);
595
596 v3d_emit_z_stencil_config(job, surf, rsc, false);
597
598 /* Emit the separate stencil packet if we have a resource for
599 * it. The HW will only load/store this buffer if the
600 * Z/Stencil config doesn't have stencil in its format.
601 */
602 if (surf->separate_stencil) {
603 v3d_emit_z_stencil_config(job,
604 vc5_surface(surf->separate_stencil),
605 rsc->separate_stencil, true);
606 }
607 }
608 #endif /* V3D_VERSION < 40 */
609
610 /* Ends rendering mode config. */
611 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_Z_STENCIL_CLEAR_VALUES,
612 clear) {
613 clear.z_clear_value = job->clear_z;
614 clear.stencil_vg_mask_clear_value = job->clear_s;
615 };
616
617 /* Always set initial block size before the first branch, which needs
618 * to match the value from binning mode config.
619 */
620 cl_emit(&job->rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
621 init.use_auto_chained_tile_lists = true;
622 init.size_of_first_block_in_chained_tile_lists =
623 TILE_ALLOCATION_BLOCK_SIZE_64B;
624 }
625
626 uint32_t supertile_w = 1, supertile_h = 1;
627
628 /* If doing multicore binning, we would need to initialize each core's
629 * tile list here.
630 */
631 cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
632 list.address = cl_address(job->tile_alloc, 0);
633 }
634
635 cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CONFIGURATION, config) {
636 uint32_t frame_w_in_supertiles, frame_h_in_supertiles;
637 const uint32_t max_supertiles = 256;
638
639 /* Size up our supertiles until we get under the limit. */
640 for (;;) {
641 frame_w_in_supertiles = div_round_up(job->draw_tiles_x,
642 supertile_w);
643 frame_h_in_supertiles = div_round_up(job->draw_tiles_y,
644 supertile_h);
645 if (frame_w_in_supertiles * frame_h_in_supertiles <
646 max_supertiles) {
647 break;
648 }
649
650 if (supertile_w < supertile_h)
651 supertile_w++;
652 else
653 supertile_h++;
654 }
655
656 config.total_frame_width_in_tiles = job->draw_tiles_x;
657 config.total_frame_height_in_tiles = job->draw_tiles_y;
658
659 config.supertile_width_in_tiles_minus_1 = supertile_w - 1;
660 config.supertile_height_in_tiles_minus_1 = supertile_h - 1;
661
662 config.total_frame_width_in_supertiles = frame_w_in_supertiles;
663 config.total_frame_height_in_supertiles = frame_h_in_supertiles;
664 }
665
666 /* Start by clearing the tile buffer. */
667 cl_emit(&job->rcl, TILE_COORDINATES, coords) {
668 coords.tile_column_number = 0;
669 coords.tile_row_number = 0;
670 }
671
672 #if V3D_VERSION < 40
673 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
674 store.buffer_to_store = NONE;
675 }
676 #else
677 cl_emit(&job->rcl, END_OF_LOADS, end);
678 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
679 store.buffer_to_store = NONE;
680 }
681 cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) {
682 clear.clear_z_stencil_buffer = true;
683 clear.clear_all_render_targets = true;
684 }
685 cl_emit(&job->rcl, END_OF_TILE_MARKER, end);
686 #endif
687
688 cl_emit(&job->rcl, FLUSH_VCD_CACHE, flush);
689
690 vc5_rcl_emit_generic_per_tile_list(job, nr_cbufs - 1);
691
692 cl_emit(&job->rcl, WAIT_ON_SEMAPHORE, sem);
693
694 /* XXX: Use Morton order */
695 uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
696 uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
697 uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
698 uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
699 uint32_t max_x_supertile = (job->draw_max_x - 1) / supertile_w_in_pixels;
700 uint32_t max_y_supertile = (job->draw_max_y - 1) / supertile_h_in_pixels;
701
702 for (int y = min_y_supertile; y <= max_y_supertile; y++) {
703 for (int x = min_x_supertile; x <= max_x_supertile; x++) {
704 cl_emit(&job->rcl, SUPERTILE_COORDINATES, coords) {
705 coords.column_number_in_supertiles = x;
706 coords.row_number_in_supertiles = y;
707 }
708 }
709 }
710
711 cl_emit(&job->rcl, END_OF_RENDERING, end);
712 }