src/gallium/drivers/vc5/vc5_resource.c

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #include "pipe/p_defines.h"
  26 #include "util/u_blit.h"
  27 #include "util/u_memory.h"
  28 #include "util/u_format.h"
  29 #include "util/u_inlines.h"
  30 #include "util/u_surface.h"
  31 #include "util/u_transfer_helper.h"
  32 #include "util/u_upload_mgr.h"
  33 #include "util/u_format_zs.h"
  34
  35 #include "drm_fourcc.h"
  36 #include "vc5_screen.h"
  37 #include "vc5_context.h"
  38 #include "vc5_resource.h"
  39 #include "vc5_tiling.h"
  40 #include "broadcom/cle/v3d_packet_v33_pack.h"
  41
  42 static void
  43 vc5_debug_resource_layout(struct vc5_resource *rsc, const char *caller)
  44 {
  45         if (!(V3D_DEBUG & V3D_DEBUG_SURFACE))
  46                 return;
  47
  48         struct pipe_resource *prsc = &rsc->base;
  49
  50         if (prsc->target == PIPE_BUFFER) {
  51                 fprintf(stderr,
  52                         "rsc %s %p (format %s), %dx%d buffer @0x%08x-0x%08x\n",
  53                         caller, rsc,
  54                         util_format_short_name(prsc->format),
  55                         prsc->width0, prsc->height0,
  56                         rsc->bo->offset,
  57                         rsc->bo->offset + rsc->bo->size - 1);
  58                 return;
  59         }
  60
  61         static const char *const tiling_descriptions[] = {
  62                 [VC5_TILING_RASTER] = "R",
  63                 [VC5_TILING_LINEARTILE] = "LT",
  64                 [VC5_TILING_UBLINEAR_1_COLUMN] = "UB1",
  65                 [VC5_TILING_UBLINEAR_2_COLUMN] = "UB2",
  66                 [VC5_TILING_UIF_NO_XOR] = "UIF",
  67                 [VC5_TILING_UIF_XOR] = "UIF^",
  68         };
  69
  70         for (int i = 0; i <= prsc->last_level; i++) {
  71                 struct vc5_resource_slice *slice = &rsc->slices[i];
  72
  73                 int level_width = slice->stride / rsc->cpp;
  74                 int level_height = slice->padded_height;
  75                 int level_depth =
  76                         u_minify(util_next_power_of_two(prsc->depth0), i);
  77
  78                 fprintf(stderr,
  79                         "rsc %s %p (format %s), %dx%d: "
  80                         "level %d (%s) %dx%dx%d -> %dx%dx%d, stride %d@0x%08x\n",
  81                         caller, rsc,
  82                         util_format_short_name(prsc->format),
  83                         prsc->width0, prsc->height0,
  84                         i, tiling_descriptions[slice->tiling],
  85                         u_minify(prsc->width0, i),
  86                         u_minify(prsc->height0, i),
  87                         u_minify(prsc->depth0, i),
  88                         level_width,
  89                         level_height,
  90                         level_depth,
  91                         slice->stride,
  92                         rsc->bo->offset + slice->offset);
  93         }
  94 }
  95
  96 static bool
  97 vc5_resource_bo_alloc(struct vc5_resource *rsc)
  98 {
  99         struct pipe_resource *prsc = &rsc->base;
 100         struct pipe_screen *pscreen = prsc->screen;
 101         struct vc5_bo *bo;
 102
 103         bo = vc5_bo_alloc(vc5_screen(pscreen), rsc->size, "resource");
 104         if (bo) {
 105                 vc5_bo_unreference(&rsc->bo);
 106                 rsc->bo = bo;
 107                 vc5_debug_resource_layout(rsc, "alloc");
 108                 return true;
 109         } else {
 110                 return false;
 111         }
 112 }
 113
 114 static void
 115 vc5_resource_transfer_unmap(struct pipe_context *pctx,
 116                             struct pipe_transfer *ptrans)
 117 {
 118         struct vc5_context *vc5 = vc5_context(pctx);
 119         struct vc5_transfer *trans = vc5_transfer(ptrans);
 120
 121         if (trans->map) {
 122                 struct vc5_resource *rsc = vc5_resource(ptrans->resource);
 123                 struct vc5_resource_slice *slice = &rsc->slices[ptrans->level];
 124
 125                 if (ptrans->usage & PIPE_TRANSFER_WRITE) {
 126                         for (int z = 0; z < ptrans->box.depth; z++) {
 127                                 void *dst = rsc->bo->map +
 128                                         vc5_layer_offset(&rsc->base,
 129                                                          ptrans->level,
 130                                                          ptrans->box.z + z);
 131                                 vc5_store_tiled_image(dst,
 132                                                       slice->stride,
 133                                                       (trans->map +
 134                                                        ptrans->stride *
 135                                                        ptrans->box.height * z),
 136                                                       ptrans->stride,
 137                                                       slice->tiling, rsc->cpp,
 138                                                       slice->padded_height,
 139                                                       &ptrans->box);
 140                         }
 141                 }
 142                 free(trans->map);
 143         }
 144
 145         pipe_resource_reference(&ptrans->resource, NULL);
 146         slab_free(&vc5->transfer_pool, ptrans);
 147 }
 148
 149 static void *
 150 vc5_resource_transfer_map(struct pipe_context *pctx,
 151                           struct pipe_resource *prsc,
 152                           unsigned level, unsigned usage,
 153                           const struct pipe_box *box,
 154                           struct pipe_transfer **pptrans)
 155 {
 156         struct vc5_context *vc5 = vc5_context(pctx);
 157         struct vc5_resource *rsc = vc5_resource(prsc);
 158         struct vc5_transfer *trans;
 159         struct pipe_transfer *ptrans;
 160         enum pipe_format format = prsc->format;
 161         char *buf;
 162
 163         /* MSAA maps should have been handled by u_transfer_helper. */
 164         assert(prsc->nr_samples <= 1);
 165
 166         /* Upgrade DISCARD_RANGE to WHOLE_RESOURCE if the whole resource is
 167          * being mapped.
 168          */
 169         if ((usage & PIPE_TRANSFER_DISCARD_RANGE) &&
 170             !(usage & PIPE_TRANSFER_UNSYNCHRONIZED) &&
 171             !(prsc->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) &&
 172             prsc->last_level == 0 &&
 173             prsc->width0 == box->width &&
 174             prsc->height0 == box->height &&
 175             prsc->depth0 == box->depth &&
 176             prsc->array_size == 1 &&
 177             rsc->bo->private) {
 178                 usage |= PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE;
 179         }
 180
 181         if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
 182                 if (vc5_resource_bo_alloc(rsc)) {
 183                         /* If it might be bound as one of our vertex buffers
 184                          * or UBOs, make sure we re-emit vertex buffer state
 185                          * or uniforms.
 186                          */
 187                         if (prsc->bind & PIPE_BIND_VERTEX_BUFFER)
 188                                 vc5->dirty |= VC5_DIRTY_VTXBUF;
 189                         if (prsc->bind & PIPE_BIND_CONSTANT_BUFFER)
 190                                 vc5->dirty |= VC5_DIRTY_CONSTBUF;
 191                 } else {
 192                         /* If we failed to reallocate, flush users so that we
 193                          * don't violate any syncing requirements.
 194                          */
 195                         vc5_flush_jobs_reading_resource(vc5, prsc);
 196                 }
 197         } else if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
 198                 /* If we're writing and the buffer is being used by the CL, we
 199                  * have to flush the CL first.  If we're only reading, we need
 200                  * to flush if the CL has written our buffer.
 201                  */
 202                 if (usage & PIPE_TRANSFER_WRITE)
 203                         vc5_flush_jobs_reading_resource(vc5, prsc);
 204                 else
 205                         vc5_flush_jobs_writing_resource(vc5, prsc);
 206         }
 207
 208         if (usage & PIPE_TRANSFER_WRITE) {
 209                 rsc->writes++;
 210                 rsc->initialized_buffers = ~0;
 211         }
 212
 213         trans = slab_alloc(&vc5->transfer_pool);
 214         if (!trans)
 215                 return NULL;
 216
 217         /* XXX: Handle DONTBLOCK, DISCARD_RANGE, PERSISTENT, COHERENT. */
 218
 219         /* slab_alloc_st() doesn't zero: */
 220         memset(trans, 0, sizeof(*trans));
 221         ptrans = &trans->base;
 222
 223         pipe_resource_reference(&ptrans->resource, prsc);
 224         ptrans->level = level;
 225         ptrans->usage = usage;
 226         ptrans->box = *box;
 227
 228         /* Note that the current kernel implementation is synchronous, so no
 229          * need to do syncing stuff here yet.
 230          */
 231
 232         if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
 233                 buf = vc5_bo_map_unsynchronized(rsc->bo);
 234         else
 235                 buf = vc5_bo_map(rsc->bo);
 236         if (!buf) {
 237                 fprintf(stderr, "Failed to map bo\n");
 238                 goto fail;
 239         }
 240
 241         *pptrans = ptrans;
 242
 243         /* Our load/store routines work on entire compressed blocks. */
 244         ptrans->box.x /= util_format_get_blockwidth(format);
 245         ptrans->box.y /= util_format_get_blockheight(format);
 246         ptrans->box.width = DIV_ROUND_UP(ptrans->box.width,
 247                                          util_format_get_blockwidth(format));
 248         ptrans->box.height = DIV_ROUND_UP(ptrans->box.height,
 249                                           util_format_get_blockheight(format));
 250
 251         struct vc5_resource_slice *slice = &rsc->slices[level];
 252         if (rsc->tiled) {
 253                 /* No direct mappings of tiled, since we need to manually
 254                  * tile/untile.
 255                  */
 256                 if (usage & PIPE_TRANSFER_MAP_DIRECTLY)
 257                         return NULL;
 258
 259                 ptrans->stride = ptrans->box.width * rsc->cpp;
 260                 ptrans->layer_stride = ptrans->stride * ptrans->box.height;
 261
 262                 trans->map = malloc(ptrans->layer_stride * ptrans->box.depth);
 263
 264                 if (usage & PIPE_TRANSFER_READ) {
 265                         for (int z = 0; z < ptrans->box.depth; z++) {
 266                                 void *src = rsc->bo->map +
 267                                         vc5_layer_offset(&rsc->base,
 268                                                          ptrans->level,
 269                                                          ptrans->box.z + z);
 270                                 vc5_load_tiled_image((trans->map +
 271                                                       ptrans->stride *
 272                                                       ptrans->box.height * z),
 273                                                      ptrans->stride,
 274                                                      src,
 275                                                      slice->stride,
 276                                                      slice->tiling, rsc->cpp,
 277                                                      slice->padded_height,
 278                                              &ptrans->box);
 279                         }
 280                 }
 281                 return trans->map;
 282         } else {
 283                 ptrans->stride = slice->stride;
 284                 ptrans->layer_stride = ptrans->stride;
 285
 286                 return buf + slice->offset +
 287                         ptrans->box.y * ptrans->stride +
 288                         ptrans->box.x * rsc->cpp +
 289                         ptrans->box.z * rsc->cube_map_stride;
 290         }
 291
 292
 293 fail:
 294         vc5_resource_transfer_unmap(pctx, ptrans);
 295         return NULL;
 296 }
 297
 298 static void
 299 vc5_resource_destroy(struct pipe_screen *pscreen,
 300                      struct pipe_resource *prsc)
 301 {
 302         struct vc5_resource *rsc = vc5_resource(prsc);
 303
 304         vc5_bo_unreference(&rsc->bo);
 305         free(rsc);
 306 }
 307
 308 static boolean
 309 vc5_resource_get_handle(struct pipe_screen *pscreen,
 310                         struct pipe_context *pctx,
 311                         struct pipe_resource *prsc,
 312                         struct winsys_handle *whandle,
 313                         unsigned usage)
 314 {
 315         struct vc5_resource *rsc = vc5_resource(prsc);
 316         struct vc5_bo *bo = rsc->bo;
 317
 318         whandle->stride = rsc->slices[0].stride;
 319
 320         /* If we're passing some reference to our BO out to some other part of
 321          * the system, then we can't do any optimizations about only us being
 322          * the ones seeing it (like BO caching).
 323          */
 324         bo->private = false;
 325
 326         switch (whandle->type) {
 327         case DRM_API_HANDLE_TYPE_SHARED:
 328                 return vc5_bo_flink(bo, &whandle->handle);
 329         case DRM_API_HANDLE_TYPE_KMS:
 330                 whandle->handle = bo->handle;
 331                 return TRUE;
 332         case DRM_API_HANDLE_TYPE_FD:
 333                 whandle->handle = vc5_bo_get_dmabuf(bo);
 334                 return whandle->handle != -1;
 335         }
 336
 337         return FALSE;
 338 }
 339
 340 #define PAGE_UB_ROWS (VC5_UIFCFG_PAGE_SIZE / VC5_UIFBLOCK_ROW_SIZE)
 341 #define PAGE_UB_ROWS_TIMES_1_5 ((PAGE_UB_ROWS * 3) >> 1)
 342 #define PAGE_CACHE_UB_ROWS (VC5_PAGE_CACHE_SIZE / VC5_UIFBLOCK_ROW_SIZE)
 343 #define PAGE_CACHE_MINUS_1_5_UB_ROWS (PAGE_CACHE_UB_ROWS - PAGE_UB_ROWS_TIMES_1_5)
 344
 345 /**
 346  * Computes the HW's UIFblock padding for a given height/cpp.
 347  *
 348  * The goal of the padding is to keep pages of the same color (bank number) at
 349  * least half a page away from each other vertically when crossing between
 350  * between columns of UIF blocks.
 351  */
 352 static uint32_t
 353 vc5_get_ub_pad(struct vc5_resource *rsc, uint32_t height)
 354 {
 355         uint32_t utile_h = vc5_utile_height(rsc->cpp);
 356         uint32_t uif_block_h = utile_h * 2;
 357         uint32_t height_ub = height / uif_block_h;
 358
 359         uint32_t height_offset_in_pc = height_ub % PAGE_CACHE_UB_ROWS;
 360
 361         /* For the perfectly-aligned-for-UIF-XOR case, don't add any pad. */
 362         if (height_offset_in_pc == 0)
 363                 return 0;
 364
 365         /* Try padding up to where we're offset by at least half a page. */
 366         if (height_offset_in_pc < PAGE_UB_ROWS_TIMES_1_5) {
 367                 /* If we fit entirely in the page cache, don't pad. */
 368                 if (height_ub < PAGE_CACHE_UB_ROWS)
 369                         return 0;
 370                 else
 371                         return PAGE_UB_ROWS_TIMES_1_5 - height_offset_in_pc;
 372         }
 373
 374         /* If we're close to being aligned to page cache size, then round up
 375          * and rely on XOR.
 376          */
 377         if (height_offset_in_pc > PAGE_CACHE_MINUS_1_5_UB_ROWS)
 378                 return PAGE_CACHE_UB_ROWS - height_offset_in_pc;
 379
 380         /* Otherwise, we're far enough away (top and bottom) to not need any
 381          * padding.
 382          */
 383         return 0;
 384 }
 385
 386 static void
 387 vc5_setup_slices(struct vc5_resource *rsc)
 388 {
 389         struct pipe_resource *prsc = &rsc->base;
 390         uint32_t width = prsc->width0;
 391         uint32_t height = prsc->height0;
 392         uint32_t depth = prsc->depth0;
 393         /* Note that power-of-two padding is based on level 1.  These are not
 394          * equivalent to just util_next_power_of_two(dimension), because at a
 395          * level 0 dimension of 9, the level 1 power-of-two padded value is 4,
 396          * not 8.
 397          */
 398         uint32_t pot_width = 2 * util_next_power_of_two(u_minify(width, 1));
 399         uint32_t pot_height = 2 * util_next_power_of_two(u_minify(height, 1));
 400         uint32_t pot_depth = 2 * util_next_power_of_two(u_minify(depth, 1));
 401         uint32_t offset = 0;
 402         uint32_t utile_w = vc5_utile_width(rsc->cpp);
 403         uint32_t utile_h = vc5_utile_height(rsc->cpp);
 404         uint32_t uif_block_w = utile_w * 2;
 405         uint32_t uif_block_h = utile_h * 2;
 406         uint32_t block_width = util_format_get_blockwidth(prsc->format);
 407         uint32_t block_height = util_format_get_blockheight(prsc->format);
 408         bool msaa = prsc->nr_samples > 1;
 409         /* MSAA textures/renderbuffers are always laid out as single-level
 410          * UIF.
 411          */
 412         bool uif_top = msaa;
 413
 414         for (int i = prsc->last_level; i >= 0; i--) {
 415                 struct vc5_resource_slice *slice = &rsc->slices[i];
 416
 417                 uint32_t level_width, level_height, level_depth;
 418                 if (i < 2) {
 419                         level_width = u_minify(width, i);
 420                         level_height = u_minify(height, i);
 421                 } else {
 422                         level_width = u_minify(pot_width, i);
 423                         level_height = u_minify(pot_height, i);
 424                 }
 425                 if (i < 1)
 426                         level_depth = u_minify(depth, i);
 427                 else
 428                         level_depth = u_minify(pot_depth, i);
 429
 430                 if (msaa) {
 431                         level_width *= 2;
 432                         level_height *= 2;
 433                 }
 434
 435                 level_width = DIV_ROUND_UP(level_width, block_width);
 436                 level_height = DIV_ROUND_UP(level_height, block_height);
 437
 438                 if (!rsc->tiled) {
 439                         slice->tiling = VC5_TILING_RASTER;
 440                         if (prsc->target == PIPE_TEXTURE_1D)
 441                                 level_width = align(level_width, 64 / rsc->cpp);
 442                 } else {
 443                         if ((i != 0 || !uif_top) &&
 444                             (level_width <= utile_w ||
 445                              level_height <= utile_h)) {
 446                                 slice->tiling = VC5_TILING_LINEARTILE;
 447                                 level_width = align(level_width, utile_w);
 448                                 level_height = align(level_height, utile_h);
 449                         } else if ((i != 0 || !uif_top) &&
 450                                    level_width <= uif_block_w) {
 451                                 slice->tiling = VC5_TILING_UBLINEAR_1_COLUMN;
 452                                 level_width = align(level_width, uif_block_w);
 453                                 level_height = align(level_height, uif_block_h);
 454                         } else if ((i != 0 || !uif_top) &&
 455                                    level_width <= 2 * uif_block_w) {
 456                                 slice->tiling = VC5_TILING_UBLINEAR_2_COLUMN;
 457                                 level_width = align(level_width, 2 * uif_block_w);
 458                                 level_height = align(level_height, uif_block_h);
 459                         } else {
 460                                 /* We align the width to a 4-block column of
 461                                  * UIF blocks, but we only align height to UIF
 462                                  * blocks.
 463                                  */
 464                                 level_width = align(level_width,
 465                                                     4 * uif_block_w);
 466                                 level_height = align(level_height,
 467                                                      uif_block_h);
 468
 469                                 slice->ub_pad = vc5_get_ub_pad(rsc,
 470                                                                level_height);
 471                                 level_height += slice->ub_pad * uif_block_h;
 472
 473                                 /* If the padding set us to to be aligned to
 474                                  * the page cache size, then the HW will use
 475                                  * the XOR bit on odd columns to get us
 476                                  * perfectly misaligned
 477                                  */
 478                                 if ((level_height / uif_block_h) %
 479                                     (VC5_PAGE_CACHE_SIZE /
 480                                      VC5_UIFBLOCK_ROW_SIZE) == 0) {
 481                                         slice->tiling = VC5_TILING_UIF_XOR;
 482                                 } else {
 483                                         slice->tiling = VC5_TILING_UIF_NO_XOR;
 484                                 }
 485                         }
 486                 }
 487
 488                 slice->offset = offset;
 489                 slice->stride = level_width * rsc->cpp;
 490                 slice->padded_height = level_height;
 491                 slice->size = level_height * slice->stride;
 492
 493                 uint32_t slice_total_size = slice->size * level_depth;
 494
 495                 /* The HW aligns level 1's base to a page if any of level 1 or
 496                  * below could be UIF XOR.  The lower levels then inherit the
 497                  * alignment for as long as necesary, thanks to being power of
 498                  * two aligned.
 499                  */
 500                 if (i == 1 &&
 501                     level_width > 4 * uif_block_w &&
 502                     level_height > PAGE_CACHE_MINUS_1_5_UB_ROWS * uif_block_h) {
 503                         slice_total_size = align(slice_total_size,
 504                                                  VC5_UIFCFG_PAGE_SIZE);
 505                 }
 506
 507                 offset += slice_total_size;
 508
 509         }
 510         rsc->size = offset;
 511
 512         /* UIF/UBLINEAR levels need to be aligned to UIF-blocks, and LT only
 513          * needs to be aligned to utile boundaries.  Since tiles are laid out
 514          * from small to big in memory, we need to align the later UIF slices
 515          * to UIF blocks, if they were preceded by non-UIF-block-aligned LT
 516          * slices.
 517          *
 518          * We additionally align to 4k, which improves UIF XOR performance.
 519          */
 520         uint32_t page_align_offset = (align(rsc->slices[0].offset, 4096) -
 521                                       rsc->slices[0].offset);
 522         if (page_align_offset) {
 523                 rsc->size += page_align_offset;
 524                 for (int i = 0; i <= prsc->last_level; i++)
 525                         rsc->slices[i].offset += page_align_offset;
 526         }
 527
 528         /* Arrays and cube textures have a stride which is the distance from
 529          * one full mipmap tree to the next (64b aligned).  For 3D textures,
 530          * we need to program the stride between slices of miplevel 0.
 531          */
 532         if (prsc->target != PIPE_TEXTURE_3D) {
 533                 rsc->cube_map_stride = align(rsc->slices[0].offset +
 534                                              rsc->slices[0].size, 64);
 535                 rsc->size += rsc->cube_map_stride * (prsc->array_size - 1);
 536         } else {
 537                 rsc->cube_map_stride = rsc->slices[0].size;
 538         }
 539 }
 540
 541 uint32_t
 542 vc5_layer_offset(struct pipe_resource *prsc, uint32_t level, uint32_t layer)
 543 {
 544         struct vc5_resource *rsc = vc5_resource(prsc);
 545         struct vc5_resource_slice *slice = &rsc->slices[level];
 546
 547         if (prsc->target == PIPE_TEXTURE_3D)
 548                 return slice->offset + layer * slice->size;
 549         else
 550                 return slice->offset + layer * rsc->cube_map_stride;
 551 }
 552
 553 static struct vc5_resource *
 554 vc5_resource_setup(struct pipe_screen *pscreen,
 555                    const struct pipe_resource *tmpl)
 556 {
 557         struct vc5_screen *screen = vc5_screen(pscreen);
 558         struct vc5_resource *rsc = CALLOC_STRUCT(vc5_resource);
 559         if (!rsc)
 560                 return NULL;
 561         struct pipe_resource *prsc = &rsc->base;
 562
 563         *prsc = *tmpl;
 564
 565         pipe_reference_init(&prsc->reference, 1);
 566         prsc->screen = pscreen;
 567
 568         if (prsc->nr_samples <= 1 ||
 569             util_format_is_depth_or_stencil(prsc->format)) {
 570                 rsc->cpp = util_format_get_blocksize(prsc->format) *
 571                         MAX2(prsc->nr_samples, 1);
 572         } else {
 573                 assert(vc5_rt_format_supported(&screen->devinfo, prsc->format));
 574                 uint32_t output_image_format =
 575                         vc5_get_rt_format(&screen->devinfo, prsc->format);
 576                 uint32_t internal_type;
 577                 uint32_t internal_bpp;
 578                 vc5_get_internal_type_bpp_for_output_format(&screen->devinfo,
 579                                                             output_image_format,
 580                                                             &internal_type,
 581                                                             &internal_bpp);
 582                 switch (internal_bpp) {
 583                 case V3D_INTERNAL_BPP_32:
 584                         rsc->cpp = 4;
 585                         break;
 586                 case V3D_INTERNAL_BPP_64:
 587                         rsc->cpp = 8;
 588                         break;
 589                 case V3D_INTERNAL_BPP_128:
 590                         rsc->cpp = 16;
 591                         break;
 592                 }
 593         }
 594
 595         assert(rsc->cpp);
 596
 597         return rsc;
 598 }
 599
 600 static bool
 601 find_modifier(uint64_t needle, const uint64_t *haystack, int count)
 602 {
 603         int i;
 604
 605         for (i = 0; i < count; i++) {
 606                 if (haystack[i] == needle)
 607                         return true;
 608         }
 609
 610         return false;
 611 }
 612
 613 static struct pipe_resource *
 614 vc5_resource_create_with_modifiers(struct pipe_screen *pscreen,
 615                                    const struct pipe_resource *tmpl,
 616                                    const uint64_t *modifiers,
 617                                    int count)
 618 {
 619         bool linear_ok = find_modifier(DRM_FORMAT_MOD_LINEAR, modifiers, count);
 620         struct vc5_resource *rsc = vc5_resource_setup(pscreen, tmpl);
 621         struct pipe_resource *prsc = &rsc->base;
 622         /* Use a tiled layout if we can, for better 3D performance. */
 623         bool should_tile = true;
 624
 625         /* VBOs/PBOs are untiled (and 1 height). */
 626         if (tmpl->target == PIPE_BUFFER)
 627                 should_tile = false;
 628
 629         /* Cursors are always linear, and the user can request linear as well.
 630          */
 631         if (tmpl->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR))
 632                 should_tile = false;
 633
 634         /* 1D and 1D_ARRAY textures are always raster-order. */
 635         if (tmpl->target == PIPE_TEXTURE_1D ||
 636             tmpl->target == PIPE_TEXTURE_1D_ARRAY)
 637                 should_tile = false;
 638
 639         /* Scanout BOs for simulator need to be linear for interaction with
 640          * i965.
 641          */
 642         if (using_vc5_simulator &&
 643             tmpl->bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
 644                 should_tile = false;
 645
 646         /* No user-specified modifier; determine our own. */
 647         if (count == 1 && modifiers[0] == DRM_FORMAT_MOD_INVALID) {
 648                 linear_ok = true;
 649                 rsc->tiled = should_tile;
 650         } else if (should_tile &&
 651                    find_modifier(DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
 652                                  modifiers, count)) {
 653                 rsc->tiled = true;
 654         } else if (linear_ok) {
 655                 rsc->tiled = false;
 656         } else {
 657                 fprintf(stderr, "Unsupported modifier requested\n");
 658                 return NULL;
 659         }
 660
 661         rsc->internal_format = prsc->format;
 662
 663         vc5_setup_slices(rsc);
 664         if (!vc5_resource_bo_alloc(rsc))
 665                 goto fail;
 666
 667         return prsc;
 668 fail:
 669         vc5_resource_destroy(pscreen, prsc);
 670         return NULL;
 671 }
 672
 673 struct pipe_resource *
 674 vc5_resource_create(struct pipe_screen *pscreen,
 675                     const struct pipe_resource *tmpl)
 676 {
 677         const uint64_t mod = DRM_FORMAT_MOD_INVALID;
 678         return vc5_resource_create_with_modifiers(pscreen, tmpl, &mod, 1);
 679 }
 680
 681 static struct pipe_resource *
 682 vc5_resource_from_handle(struct pipe_screen *pscreen,
 683                          const struct pipe_resource *tmpl,
 684                          struct winsys_handle *whandle,
 685                          unsigned usage)
 686 {
 687         struct vc5_screen *screen = vc5_screen(pscreen);
 688         struct vc5_resource *rsc = vc5_resource_setup(pscreen, tmpl);
 689         struct pipe_resource *prsc = &rsc->base;
 690         struct vc5_resource_slice *slice = &rsc->slices[0];
 691
 692         if (!rsc)
 693                 return NULL;
 694
 695         switch (whandle->modifier) {
 696         case DRM_FORMAT_MOD_LINEAR:
 697         case DRM_FORMAT_MOD_INVALID:
 698                 rsc->tiled = false;
 699                 break;
 700         /* XXX: UIF */
 701         default:
 702                 fprintf(stderr,
 703                         "Attempt to import unsupported modifier 0x%llx\n",
 704                         (long long)whandle->modifier);
 705                 goto fail;
 706         }
 707
 708         if (whandle->offset != 0) {
 709                 fprintf(stderr,
 710                         "Attempt to import unsupported winsys offset %u\n",
 711                         whandle->offset);
 712                 goto fail;
 713         }
 714
 715         switch (whandle->type) {
 716         case DRM_API_HANDLE_TYPE_SHARED:
 717                 rsc->bo = vc5_bo_open_name(screen,
 718                                            whandle->handle, whandle->stride);
 719                 break;
 720         case DRM_API_HANDLE_TYPE_FD:
 721                 rsc->bo = vc5_bo_open_dmabuf(screen,
 722                                              whandle->handle, whandle->stride);
 723                 break;
 724         default:
 725                 fprintf(stderr,
 726                         "Attempt to import unsupported handle type %d\n",
 727                         whandle->type);
 728                 goto fail;
 729         }
 730
 731         if (!rsc->bo)
 732                 goto fail;
 733
 734         vc5_setup_slices(rsc);
 735         vc5_debug_resource_layout(rsc, "import");
 736
 737         if (whandle->stride != slice->stride) {
 738                 static bool warned = false;
 739                 if (!warned) {
 740                         warned = true;
 741                         fprintf(stderr,
 742                                 "Attempting to import %dx%d %s with "
 743                                 "unsupported stride %d instead of %d\n",
 744                                 prsc->width0, prsc->height0,
 745                                 util_format_short_name(prsc->format),
 746                                 whandle->stride,
 747                                 slice->stride);
 748                 }
 749                 goto fail;
 750         }
 751
 752         return prsc;
 753
 754 fail:
 755         vc5_resource_destroy(pscreen, prsc);
 756         return NULL;
 757 }
 758
 759 static struct pipe_surface *
 760 vc5_create_surface(struct pipe_context *pctx,
 761                    struct pipe_resource *ptex,
 762                    const struct pipe_surface *surf_tmpl)
 763 {
 764         struct vc5_context *vc5 = vc5_context(pctx);
 765         struct vc5_screen *screen = vc5->screen;
 766         struct vc5_surface *surface = CALLOC_STRUCT(vc5_surface);
 767         struct vc5_resource *rsc = vc5_resource(ptex);
 768
 769         if (!surface)
 770                 return NULL;
 771
 772         assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer);
 773
 774         struct pipe_surface *psurf = &surface->base;
 775         unsigned level = surf_tmpl->u.tex.level;
 776         struct vc5_resource_slice *slice = &rsc->slices[level];
 777
 778         pipe_reference_init(&psurf->reference, 1);
 779         pipe_resource_reference(&psurf->texture, ptex);
 780
 781         psurf->context = pctx;
 782         psurf->format = surf_tmpl->format;
 783         psurf->width = u_minify(ptex->width0, level);
 784         psurf->height = u_minify(ptex->height0, level);
 785         psurf->u.tex.level = level;
 786         psurf->u.tex.first_layer = surf_tmpl->u.tex.first_layer;
 787         psurf->u.tex.last_layer = surf_tmpl->u.tex.last_layer;
 788
 789         surface->offset = vc5_layer_offset(ptex, level,
 790                                            psurf->u.tex.first_layer);
 791         surface->tiling = slice->tiling;
 792
 793         surface->format = vc5_get_rt_format(&screen->devinfo, psurf->format);
 794
 795         if (util_format_is_depth_or_stencil(psurf->format)) {
 796                 switch (psurf->format) {
 797                 case PIPE_FORMAT_Z16_UNORM:
 798                         surface->internal_type = V3D_INTERNAL_TYPE_DEPTH_16;
 799                         break;
 800                 case PIPE_FORMAT_Z32_FLOAT:
 801                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 802                         surface->internal_type = V3D_INTERNAL_TYPE_DEPTH_32F;
 803                         break;
 804                 default:
 805                         surface->internal_type = V3D_INTERNAL_TYPE_DEPTH_24;
 806                 }
 807         } else {
 808                 uint32_t bpp, type;
 809                 vc5_get_internal_type_bpp_for_output_format(&screen->devinfo,
 810                                                             surface->format,
 811                                                             &type, &bpp);
 812                 surface->internal_type = type;
 813                 surface->internal_bpp = bpp;
 814         }
 815
 816         if (surface->tiling == VC5_TILING_UIF_NO_XOR ||
 817             surface->tiling == VC5_TILING_UIF_XOR) {
 818                 surface->padded_height_of_output_image_in_uif_blocks =
 819                         (slice->padded_height /
 820                          (2 * vc5_utile_height(rsc->cpp)));
 821         }
 822
 823         if (rsc->separate_stencil) {
 824                 surface->separate_stencil =
 825                         vc5_create_surface(pctx, &rsc->separate_stencil->base,
 826                                            surf_tmpl);
 827         }
 828
 829         return &surface->base;
 830 }
 831
 832 static void
 833 vc5_surface_destroy(struct pipe_context *pctx, struct pipe_surface *psurf)
 834 {
 835         struct vc5_surface *surf = vc5_surface(psurf);
 836
 837         if (surf->separate_stencil)
 838                 pipe_surface_reference(&surf->separate_stencil, NULL);
 839
 840         pipe_resource_reference(&psurf->texture, NULL);
 841         FREE(psurf);
 842 }
 843
 844 static void
 845 vc5_flush_resource(struct pipe_context *pctx, struct pipe_resource *resource)
 846 {
 847         /* All calls to flush_resource are followed by a flush of the context,
 848          * so there's nothing to do.
 849          */
 850 }
 851
 852 static enum pipe_format
 853 vc5_resource_get_internal_format(struct pipe_resource *prsc)
 854 {
 855         return vc5_resource(prsc)->internal_format;
 856 }
 857
 858 static void
 859 vc5_resource_set_stencil(struct pipe_resource *prsc,
 860                          struct pipe_resource *stencil)
 861 {
 862         vc5_resource(prsc)->separate_stencil = vc5_resource(stencil);
 863 }
 864
 865 static struct pipe_resource *
 866 vc5_resource_get_stencil(struct pipe_resource *prsc)
 867 {
 868         struct vc5_resource *rsc = vc5_resource(prsc);
 869
 870         return &rsc->separate_stencil->base;
 871 }
 872
 873 static const struct u_transfer_vtbl transfer_vtbl = {
 874         .resource_create          = vc5_resource_create,
 875         .resource_destroy         = vc5_resource_destroy,
 876         .transfer_map             = vc5_resource_transfer_map,
 877         .transfer_unmap           = vc5_resource_transfer_unmap,
 878         .transfer_flush_region    = u_default_transfer_flush_region,
 879         .get_internal_format      = vc5_resource_get_internal_format,
 880         .set_stencil              = vc5_resource_set_stencil,
 881         .get_stencil              = vc5_resource_get_stencil,
 882 };
 883
 884 void
 885 vc5_resource_screen_init(struct pipe_screen *pscreen)
 886 {
 887         pscreen->resource_create_with_modifiers =
 888                 vc5_resource_create_with_modifiers;
 889         pscreen->resource_create = u_transfer_helper_resource_create;
 890         pscreen->resource_from_handle = vc5_resource_from_handle;
 891         pscreen->resource_get_handle = vc5_resource_get_handle;
 892         pscreen->resource_destroy = u_transfer_helper_resource_destroy;
 893         pscreen->transfer_helper = u_transfer_helper_create(&transfer_vtbl,
 894                                                             true, true, true);
 895 }
 896
 897 void
 898 vc5_resource_context_init(struct pipe_context *pctx)
 899 {
 900         pctx->transfer_map = u_transfer_helper_transfer_map;
 901         pctx->transfer_flush_region = u_transfer_helper_transfer_flush_region;
 902         pctx->transfer_unmap = u_transfer_helper_transfer_unmap;
 903         pctx->buffer_subdata = u_default_buffer_subdata;
 904         pctx->texture_subdata = u_default_texture_subdata;
 905         pctx->create_surface = vc5_create_surface;
 906         pctx->surface_destroy = vc5_surface_destroy;
 907         pctx->resource_copy_region = util_resource_copy_region;
 908         pctx->blit = vc5_blit;
 909         pctx->flush_resource = vc5_flush_resource;
 910 }