src/gallium/drivers/vc5/vc5_resource.h

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  */
  24
  25 #ifndef VC5_RESOURCE_H
  26 #define VC5_RESOURCE_H
  27
  28 #include "vc5_screen.h"
  29 #include "util/u_transfer.h"
  30
  31 /* A UIFblock is a 256-byte region of memory that's 256-byte aligned.  These
  32  * will be grouped in 4x4 blocks (left-to-right, then top-to-bottom) in a 4KB
  33  * page.  Those pages are then arranged left-to-right, top-to-bottom, to cover
  34  * an image.
  35  *
  36  * The inside of a UIFblock, for packed pixels, will be split into 4 64-byte
  37  * utiles.  Utiles may be 8x8 (8bpp), 8x4(16bpp) or 4x4 (32bpp).
  38  */
  39
  40 /**
  41  * Tiling mode enum used for vc5_resource.c, which maps directly to the Memory
  42  * Format field of render target and Z/Stencil config.
  43  */
  44 enum vc5_tiling_mode {
  45         /* Untiled resources.  Not valid as texture inputs. */
  46         VC5_TILING_RASTER,
  47
  48         /* Single line of u-tiles. */
  49         VC5_TILING_LINEARTILE,
  50
  51         /* Departure from standard 4-UIF block column format. */
  52         VC5_TILING_UBLINEAR_1_COLUMN,
  53
  54         /* Departure from standard 4-UIF block column format. */
  55         VC5_TILING_UBLINEAR_2_COLUMN,
  56
  57         /* Normal tiling format: grouped in 4x4 UIFblocks, each of which is
  58          * split 2x2 into utiles.
  59          */
  60         VC5_TILING_UIF_NO_XOR,
  61
  62         /* Normal tiling format: grouped in 4x4 UIFblocks, each of which is
  63          * split 2x2 into utiles.
  64          */
  65         VC5_TILING_UIF_XOR,
  66 };
  67
  68 struct vc5_transfer {
  69         struct pipe_transfer base;
  70         void *map;
  71
  72         struct pipe_resource *ss_resource;
  73         struct pipe_box ss_box;
  74 };
  75
  76 struct vc5_resource_slice {
  77         uint32_t offset;
  78         uint32_t stride;
  79         uint32_t size;
  80         enum vc5_tiling_mode tiling;
  81 };
  82
  83 struct vc5_surface {
  84         struct pipe_surface base;
  85         uint32_t offset;
  86         enum vc5_tiling_mode tiling;
  87         /**
  88          * Output image format for TILE_RENDERING_MODE_CONFIGURATION
  89          */
  90         uint8_t format;
  91
  92         /**
  93          * Internal format of the tile buffer for
  94          * TILE_RENDERING_MODE_CONFIGURATION.
  95          */
  96         uint8_t internal_type;
  97
  98         /**
  99          * internal bpp value (0=32bpp, 2=128bpp) for color buffers in
 100          * TILE_RENDERING_MODE_CONFIGURATION.
 101          */
 102         uint8_t internal_bpp;
 103
 104         uint32_t padded_height_of_output_image_in_uif_blocks;
 105 };
 106
 107 struct vc5_resource {
 108         struct pipe_resource base;
 109         struct vc5_bo *bo;
 110         struct vc5_resource_slice slices[VC5_MAX_MIP_LEVELS];
 111         uint32_t cube_map_stride;
 112         int cpp;
 113         bool tiled;
 114
 115         /**
 116          * Number of times the resource has been written to.
 117          *
 118          * This is used to track whether we need to load the surface on first
 119          * rendering.
 120          */
 121         uint64_t writes;
 122
 123         /**
 124          * Bitmask of PIPE_CLEAR_COLOR0, PIPE_CLEAR_DEPTH, PIPE_CLEAR_STENCIL
 125          * for which parts of the resource are defined.
 126          *
 127          * Used for avoiding fallback to quad clears for clearing just depth,
 128          * when the stencil contents have never been initialized.  Note that
 129          * we're lazy and fields not present in the buffer (DEPTH in a color
 130          * buffer) may get marked.
 131          */
 132         uint32_t initialized_buffers;
 133 };
 134
 135 static inline struct vc5_resource *
 136 vc5_resource(struct pipe_resource *prsc)
 137 {
 138         return (struct vc5_resource *)prsc;
 139 }
 140
 141 static inline struct vc5_surface *
 142 vc5_surface(struct pipe_surface *psurf)
 143 {
 144         return (struct vc5_surface *)psurf;
 145 }
 146
 147 static inline struct vc5_transfer *
 148 vc5_transfer(struct pipe_transfer *ptrans)
 149 {
 150         return (struct vc5_transfer *)ptrans;
 151 }
 152
 153 void vc5_resource_screen_init(struct pipe_screen *pscreen);
 154 void vc5_resource_context_init(struct pipe_context *pctx);
 155 struct pipe_resource *vc5_resource_create(struct pipe_screen *pscreen,
 156                                           const struct pipe_resource *tmpl);
 157
 158 #endif /* VC5_RESOURCE_H */