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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * @file vc5_simulator.c
27 * Implements VC5 simulation on top of a non-VC5 GEM fd.
29 * This file's goal is to emulate the VC5 ioctls' behavior in the kernel on
30 * top of the simpenrose software simulator. Generally, VC5 driver BOs have a
31 * GEM-side copy of their contents and a simulator-side memory area that the
32 * GEM contents get copied into during simulation. Once simulation is done,
33 * the simulator's data is copied back out to the GEM BOs, so that rendering
34 * appears on the screen as if actual hardware rendering had been done.
36 * One of the limitations of this code is that we shouldn't really need a
37 * GEM-side BO for non-window-system BOs. However, do we need unique BO
38 * handles for each of our GEM bos so that this file can look up its state
39 * from the handle passed in at submit ioctl time (also, a couple of places
40 * outside of this file still call ioctls directly on the fd).
42 * Another limitation is that BO import doesn't work unless the underlying
43 * window system's BO size matches what VC5 is going to use, which of course
44 * doesn't work out in practice. This means that for now, only DRI3 (VC5
45 * makes the winsys BOs) is supported, not DRI2 (window system makes the winys
49 #ifdef USE_VC5_SIMULATOR
52 #include "util/hash_table.h"
53 #include "util/ralloc.h"
55 #include "util/u_memory.h"
56 #include "util/u_mm.h"
58 #define HW_REGISTER_RO(x) (x)
59 #define HW_REGISTER_RW(x) (x)
60 #include "libs/core/v3d/registers/3.3.0.0/v3d.h"
62 #include "vc5_screen.h"
63 #include "vc5_context.h"
64 #define V3D_TECH_VERSION 3
65 #define V3D_REVISION 3
67 #define V3D_HIDDEN_REV 0
69 #include "v3d_hw_auto.h"
71 /** Global (across GEM fds) state for the simulator */
72 static struct vc5_simulator_state
{
77 /* Base virtual address of the heap. */
79 /* Base hardware address of the heap. */
81 /* Size of the heap. */
84 struct mem_block
*heap
;
85 struct mem_block
*overflow
;
87 /** Mapping from GEM handle to struct vc5_simulator_bo * */
88 struct hash_table
*fd_map
;
92 .mutex
= _MTX_INITIALIZER_NP
,
95 /** Per-GEM-fd state for the simulator. */
96 struct vc5_simulator_file
{
99 /** Mapping from GEM handle to struct vc5_simulator_bo * */
100 struct hash_table
*bo_map
;
102 struct mem_block
*gmp
;
106 /** Wrapper for drm_vc5_bo tracking the simulator-specific state. */
107 struct vc5_simulator_bo
{
108 struct vc5_simulator_file
*file
;
110 /** Area for this BO within sim_state->mem */
111 struct mem_block
*block
;
116 uint32_t winsys_stride
;
124 return (void *)(uintptr_t)key
;
127 static struct vc5_simulator_file
*
128 vc5_get_simulator_file_for_fd(int fd
)
130 struct hash_entry
*entry
= _mesa_hash_table_search(sim_state
.fd_map
,
132 return entry
? entry
->data
: NULL
;
135 /* A marker placed just after each BO, then checked after rendering to make
136 * sure it's still there.
138 #define BO_SENTINEL 0xfedcba98
141 #define GMP_ALIGN2 17
144 * Sets the range of GPU virtual address space to have the given GMP
145 * permissions (bit 0 = read, bit 1 = write, write-only forbidden).
148 set_gmp_flags(struct vc5_simulator_file
*file
,
149 uint32_t offset
, uint32_t size
, uint32_t flag
)
151 assert((offset
& ((1 << GMP_ALIGN2
) - 1)) == 0);
152 int gmp_offset
= offset
>> GMP_ALIGN2
;
153 int gmp_count
= align(size
, 1 << GMP_ALIGN2
) >> GMP_ALIGN2
;
154 uint32_t *gmp
= file
->gmp_vaddr
;
158 for (int i
= gmp_offset
; i
< gmp_offset
+ gmp_count
; i
++) {
159 int32_t bitshift
= (i
% 16) * 2;
160 gmp
[i
/ 16] &= ~(0x3 << bitshift
);
161 gmp
[i
/ 16] |= flag
<< bitshift
;
166 * Allocates space in simulator memory and returns a tracking struct for it
167 * that also contains the drm_gem_cma_object struct.
169 static struct vc5_simulator_bo
*
170 vc5_create_simulator_bo(int fd
, int handle
, unsigned size
)
172 struct vc5_simulator_file
*file
= vc5_get_simulator_file_for_fd(fd
);
173 struct vc5_simulator_bo
*sim_bo
= rzalloc(file
,
174 struct vc5_simulator_bo
);
175 size
= align(size
, 4096);
178 sim_bo
->handle
= handle
;
180 mtx_lock(&sim_state
.mutex
);
181 sim_bo
->block
= u_mmAllocMem(sim_state
.heap
, size
+ 4, GMP_ALIGN2
, 0);
182 mtx_unlock(&sim_state
.mutex
);
183 assert(sim_bo
->block
);
185 set_gmp_flags(file
, sim_bo
->block
->ofs
, size
, 0x3);
188 sim_bo
->vaddr
= sim_state
.mem
+ sim_bo
->block
->ofs
- sim_state
.mem_base
;
189 memset(sim_bo
->vaddr
, 0xd0, size
);
191 *(uint32_t *)(sim_bo
->vaddr
+ sim_bo
->size
) = BO_SENTINEL
;
193 /* A handle of 0 is used for vc5_gem.c internal allocations that
194 * don't need to go in the lookup table.
197 mtx_lock(&sim_state
.mutex
);
198 _mesa_hash_table_insert(file
->bo_map
, int_to_key(handle
),
200 mtx_unlock(&sim_state
.mutex
);
207 vc5_free_simulator_bo(struct vc5_simulator_bo
*sim_bo
)
209 struct vc5_simulator_file
*sim_file
= sim_bo
->file
;
211 if (sim_bo
->winsys_map
)
212 munmap(sim_bo
->winsys_map
, sim_bo
->size
);
214 set_gmp_flags(sim_file
, sim_bo
->block
->ofs
, sim_bo
->size
, 0x0);
216 mtx_lock(&sim_state
.mutex
);
217 u_mmFreeMem(sim_bo
->block
);
218 if (sim_bo
->handle
) {
219 struct hash_entry
*entry
=
220 _mesa_hash_table_search(sim_file
->bo_map
,
221 int_to_key(sim_bo
->handle
));
222 _mesa_hash_table_remove(sim_file
->bo_map
, entry
);
224 mtx_unlock(&sim_state
.mutex
);
228 static struct vc5_simulator_bo
*
229 vc5_get_simulator_bo(struct vc5_simulator_file
*file
, int gem_handle
)
231 mtx_lock(&sim_state
.mutex
);
232 struct hash_entry
*entry
=
233 _mesa_hash_table_search(file
->bo_map
, int_to_key(gem_handle
));
234 mtx_unlock(&sim_state
.mutex
);
236 return entry
? entry
->data
: NULL
;
240 vc5_simulator_pin_bos(int fd
, struct vc5_job
*job
)
242 struct vc5_simulator_file
*file
= vc5_get_simulator_file_for_fd(fd
);
243 struct set_entry
*entry
;
245 set_foreach(job
->bos
, entry
) {
246 struct vc5_bo
*bo
= (struct vc5_bo
*)entry
->key
;
247 struct vc5_simulator_bo
*sim_bo
=
248 vc5_get_simulator_bo(file
, bo
->handle
);
251 memcpy(sim_bo
->vaddr
, bo
->map
, bo
->size
);
258 vc5_simulator_unpin_bos(int fd
, struct vc5_job
*job
)
260 struct vc5_simulator_file
*file
= vc5_get_simulator_file_for_fd(fd
);
261 struct set_entry
*entry
;
263 set_foreach(job
->bos
, entry
) {
264 struct vc5_bo
*bo
= (struct vc5_bo
*)entry
->key
;
265 struct vc5_simulator_bo
*sim_bo
=
266 vc5_get_simulator_bo(file
, bo
->handle
);
268 assert(*(uint32_t *)(sim_bo
->vaddr
+
269 sim_bo
->size
) == BO_SENTINEL
);
272 memcpy(bo
->map
, sim_bo
->vaddr
, bo
->size
);
280 vc5_dump_to_file(struct vc5_exec_info
*exec
)
282 static int dumpno
= 0;
283 struct drm_vc5_get_hang_state
*state
;
284 struct drm_vc5_get_hang_state_bo
*bo_state
;
285 unsigned int dump_version
= 0;
287 if (!(vc5_debug
& VC5_DEBUG_DUMP
))
290 state
= calloc(1, sizeof(*state
));
293 list_for_each_entry_safe(struct drm_vc5_bo
, bo
, &exec
->unref_list
,
298 /* Add one more for the overflow area that isn't wrapped in a BO. */
299 state
->bo_count
= exec
->bo_count
+ unref_count
+ 1;
300 bo_state
= calloc(state
->bo_count
, sizeof(*bo_state
));
302 char *filename
= NULL
;
303 asprintf(&filename
, "vc5-dri-%d.dump", dumpno
++);
304 FILE *f
= fopen(filename
, "w+");
306 fprintf(stderr
, "Couldn't open %s: %s", filename
,
311 fwrite(&dump_version
, sizeof(dump_version
), 1, f
);
313 state
->ct0ca
= exec
->ct0ca
;
314 state
->ct0ea
= exec
->ct0ea
;
315 state
->ct1ca
= exec
->ct1ca
;
316 state
->ct1ea
= exec
->ct1ea
;
317 state
->start_bin
= exec
->ct0ca
;
318 state
->start_render
= exec
->ct1ca
;
319 fwrite(state
, sizeof(*state
), 1, f
);
322 for (i
= 0; i
< exec
->bo_count
; i
++) {
323 struct drm_gem_cma_object
*cma_bo
= exec
->bo
[i
];
324 bo_state
[i
].handle
= i
; /* Not used by the parser. */
325 bo_state
[i
].paddr
= cma_bo
->paddr
;
326 bo_state
[i
].size
= cma_bo
->base
.size
;
329 list_for_each_entry_safe(struct drm_vc5_bo
, bo
, &exec
->unref_list
,
331 struct drm_gem_cma_object
*cma_bo
= &bo
->base
;
332 bo_state
[i
].handle
= 0;
333 bo_state
[i
].paddr
= cma_bo
->paddr
;
334 bo_state
[i
].size
= cma_bo
->base
.size
;
338 /* Add the static overflow memory area. */
339 bo_state
[i
].handle
= exec
->bo_count
;
340 bo_state
[i
].paddr
= sim_state
.overflow
->ofs
;
341 bo_state
[i
].size
= sim_state
.overflow
->size
;
344 fwrite(bo_state
, sizeof(*bo_state
), state
->bo_count
, f
);
346 for (int i
= 0; i
< exec
->bo_count
; i
++) {
347 struct drm_gem_cma_object
*cma_bo
= exec
->bo
[i
];
348 fwrite(cma_bo
->vaddr
, cma_bo
->base
.size
, 1, f
);
351 list_for_each_entry_safe(struct drm_vc5_bo
, bo
, &exec
->unref_list
,
353 struct drm_gem_cma_object
*cma_bo
= &bo
->base
;
354 fwrite(cma_bo
->vaddr
, cma_bo
->base
.size
, 1, f
);
357 void *overflow
= calloc(1, sim_state
.overflow
->size
);
358 fwrite(overflow
, 1, sim_state
.overflow
->size
, f
);
367 #define V3D_WRITE(reg, val) v3d_hw_write_reg(sim_state.v3d, reg, val)
368 #define V3D_READ(reg) v3d_hw_read_reg(sim_state.v3d, reg)
373 if (!v3d_hw_has_gca(sim_state
.v3d
))
376 uint32_t gca_ctrl
= V3D_READ(V3D_GCA_CACHE_CTRL
);
378 V3D_WRITE(V3D_GCA_CACHE_CTRL
, gca_ctrl
| V3D_GCA_CACHE_CTRL_FLUSH_SET
);
379 V3D_WRITE(V3D_GCA_CACHE_CTRL
, gca_ctrl
& ~V3D_GCA_CACHE_CTRL_FLUSH_SET
);
382 /* Invalidates the L2 cache. This is a read-only cache. */
386 V3D_WRITE(V3D_CTL_0_L2CACTL
,
387 V3D_CTL_0_L2CACTL_L2CCLR_SET
|
388 V3D_CTL_0_L2CACTL_L2CENA_SET
);
391 /* Invalidates texture L2 cachelines */
395 V3D_WRITE(V3D_CTL_0_L2TFLSTA
, 0);
396 V3D_WRITE(V3D_CTL_0_L2TFLEND
, ~0);
397 V3D_WRITE(V3D_CTL_0_L2TCACTL
,
398 V3D_CTL_0_L2TCACTL_L2TFLS_SET
|
399 (0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB
));
402 /* Invalidates the slice caches. These are read-only caches. */
404 vc5_flush_slices(void)
406 V3D_WRITE(V3D_CTL_0_SLCACTL
, ~0);
410 vc5_flush_caches(void)
419 vc5_simulator_flush(struct vc5_context
*vc5
,
420 struct drm_vc5_submit_cl
*submit
, struct vc5_job
*job
)
422 struct vc5_screen
*screen
= vc5
->screen
;
424 struct vc5_simulator_file
*file
= vc5_get_simulator_file_for_fd(fd
);
425 struct vc5_surface
*csurf
= vc5_surface(vc5
->framebuffer
.cbufs
[0]);
426 struct vc5_resource
*ctex
= csurf
? vc5_resource(csurf
->base
.texture
) : NULL
;
427 struct vc5_simulator_bo
*csim_bo
= ctex
? vc5_get_simulator_bo(file
, ctex
->bo
->handle
) : NULL
;
428 uint32_t winsys_stride
= ctex
? csim_bo
->winsys_stride
: 0;
429 uint32_t sim_stride
= ctex
? ctex
->slices
[0].stride
: 0;
430 uint32_t row_len
= MIN2(sim_stride
, winsys_stride
);
433 if (ctex
&& csim_bo
->winsys_map
) {
435 fprintf(stderr
, "%dx%d %d %d %d\n",
436 ctex
->base
.b
.width0
, ctex
->base
.b
.height0
,
442 for (int y
= 0; y
< ctex
->base
.b
.height0
; y
++) {
443 memcpy(ctex
->bo
->map
+ y
* sim_stride
,
444 csim_bo
->winsys_map
+ y
* winsys_stride
,
449 ret
= vc5_simulator_pin_bos(fd
, job
);
453 //vc5_dump_to_file(&exec);
455 /* Completely reset the GMP. */
456 v3d_hw_write_reg(sim_state
.v3d
, V3D_GMP_0_CFG
,
457 V3D_GMP_0_CFG_PROTENABLE_SET
);
458 v3d_hw_write_reg(sim_state
.v3d
, V3D_GMP_0_TABLE_ADDR
, file
->gmp
->ofs
);
459 v3d_hw_write_reg(sim_state
.v3d
, V3D_GMP_0_CLEAR_LOAD
, ~0);
460 while (v3d_hw_read_reg(sim_state
.v3d
, V3D_GMP_0_STATUS
) &
461 V3D_GMP_0_STATUS_CFG_BUSY_SET
) {
467 v3d_hw_write_reg(sim_state
.v3d
, V3D_CLE_0_CT0QBA
, submit
->bcl_start
);
468 v3d_hw_write_reg(sim_state
.v3d
, V3D_CLE_0_CT0QEA
, submit
->bcl_end
);
470 /* Wait for bin to complete before firing render, as it seems the
471 * simulator doesn't implement the semaphores.
473 while (v3d_hw_read_reg(sim_state
.v3d
, V3D_CLE_0_CT0CA
) !=
474 v3d_hw_read_reg(sim_state
.v3d
, V3D_CLE_0_CT0EA
)) {
475 v3d_hw_tick(sim_state
.v3d
);
478 v3d_hw_write_reg(sim_state
.v3d
, V3D_CLE_0_CT1QBA
, submit
->rcl_start
);
479 v3d_hw_write_reg(sim_state
.v3d
, V3D_CLE_0_CT1QEA
, submit
->rcl_end
);
481 while (v3d_hw_read_reg(sim_state
.v3d
, V3D_CLE_0_CT1CA
) !=
482 v3d_hw_read_reg(sim_state
.v3d
, V3D_CLE_0_CT1EA
) ||
483 v3d_hw_read_reg(sim_state
.v3d
, V3D_CLE_1_CT1CA
) !=
484 v3d_hw_read_reg(sim_state
.v3d
, V3D_CLE_1_CT1EA
)) {
485 v3d_hw_tick(sim_state
.v3d
);
488 ret
= vc5_simulator_unpin_bos(fd
, job
);
492 if (ctex
&& csim_bo
->winsys_map
) {
493 for (int y
= 0; y
< ctex
->base
.b
.height0
; y
++) {
494 memcpy(csim_bo
->winsys_map
+ y
* winsys_stride
,
495 ctex
->bo
->map
+ y
* sim_stride
,
504 * Map the underlying GEM object from the real hardware GEM handle.
507 vc5_simulator_map_winsys_bo(int fd
, struct vc5_simulator_bo
*sim_bo
)
512 struct drm_mode_map_dumb map_dumb
= {
513 .handle
= sim_bo
->handle
,
515 ret
= drmIoctl(fd
, DRM_IOCTL_MODE_MAP_DUMB
, &map_dumb
);
517 fprintf(stderr
, "map ioctl failure\n");
521 map
= mmap(NULL
, sim_bo
->size
, PROT_READ
| PROT_WRITE
, MAP_SHARED
,
522 fd
, map_dumb
.offset
);
523 if (map
== MAP_FAILED
) {
525 "mmap of bo %d (offset 0x%016llx, size %d) failed\n",
526 sim_bo
->handle
, (long long)map_dumb
.offset
,
535 * Do fixups after a BO has been opened from a handle.
537 * This could be done at DRM_IOCTL_GEM_OPEN/DRM_IOCTL_GEM_PRIME_FD_TO_HANDLE
538 * time, but we're still using drmPrimeFDToHandle() so we have this helper to
539 * be called afterward instead.
541 void vc5_simulator_open_from_handle(int fd
, uint32_t winsys_stride
,
542 int handle
, uint32_t size
)
544 struct vc5_simulator_bo
*sim_bo
=
545 vc5_create_simulator_bo(fd
, handle
, size
);
547 sim_bo
->winsys_stride
= winsys_stride
;
548 sim_bo
->winsys_map
= vc5_simulator_map_winsys_bo(fd
, sim_bo
);
552 * Simulated ioctl(fd, DRM_VC5_CREATE_BO) implementation.
554 * Making a VC5 BO is just a matter of making a corresponding BO on the host.
557 vc5_simulator_create_bo_ioctl(int fd
, struct drm_vc5_create_bo
*args
)
560 struct drm_mode_create_dumb create
= {
563 .height
= (args
->size
+ 127) / 128,
566 ret
= drmIoctl(fd
, DRM_IOCTL_MODE_CREATE_DUMB
, &create
);
567 assert(create
.size
>= args
->size
);
569 args
->handle
= create
.handle
;
571 struct vc5_simulator_bo
*sim_bo
=
572 vc5_create_simulator_bo(fd
, create
.handle
, args
->size
);
574 args
->offset
= sim_bo
->block
->ofs
;
580 * Simulated ioctl(fd, DRM_VC5_MMAP_BO) implementation.
582 * We just pass this straight through to dumb mmap.
585 vc5_simulator_mmap_bo_ioctl(int fd
, struct drm_vc5_mmap_bo
*args
)
588 struct drm_mode_map_dumb map
= {
589 .handle
= args
->handle
,
592 ret
= drmIoctl(fd
, DRM_IOCTL_MODE_MAP_DUMB
, &map
);
593 args
->offset
= map
.offset
;
599 vc5_simulator_gem_close_ioctl(int fd
, struct drm_gem_close
*args
)
601 /* Free the simulator's internal tracking. */
602 struct vc5_simulator_file
*file
= vc5_get_simulator_file_for_fd(fd
);
603 struct vc5_simulator_bo
*sim_bo
= vc5_get_simulator_bo(file
,
606 vc5_free_simulator_bo(sim_bo
);
608 /* Pass the call on down. */
609 return drmIoctl(fd
, DRM_IOCTL_GEM_CLOSE
, args
);
613 vc5_simulator_get_param_ioctl(int fd
, struct drm_vc5_get_param
*args
)
615 static const uint32_t reg_map
[] = {
616 [DRM_VC5_PARAM_V3D_UIFCFG
] = V3D_HUB_CTL_UIFCFG
,
617 [DRM_VC5_PARAM_V3D_HUB_IDENT1
] = V3D_HUB_CTL_IDENT1
,
618 [DRM_VC5_PARAM_V3D_HUB_IDENT2
] = V3D_HUB_CTL_IDENT2
,
619 [DRM_VC5_PARAM_V3D_HUB_IDENT3
] = V3D_HUB_CTL_IDENT3
,
620 [DRM_VC5_PARAM_V3D_CORE0_IDENT0
] = V3D_CTL_0_IDENT0
,
621 [DRM_VC5_PARAM_V3D_CORE0_IDENT1
] = V3D_CTL_0_IDENT1
,
622 [DRM_VC5_PARAM_V3D_CORE0_IDENT2
] = V3D_CTL_0_IDENT2
,
625 if (args
->param
< ARRAY_SIZE(reg_map
) && reg_map
[args
->param
]) {
626 args
->value
= v3d_hw_read_reg(sim_state
.v3d
,
627 reg_map
[args
->param
]);
631 fprintf(stderr
, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
632 (long long)args
->value
);
637 vc5_simulator_ioctl(int fd
, unsigned long request
, void *args
)
640 case DRM_IOCTL_VC5_CREATE_BO
:
641 return vc5_simulator_create_bo_ioctl(fd
, args
);
642 case DRM_IOCTL_VC5_MMAP_BO
:
643 return vc5_simulator_mmap_bo_ioctl(fd
, args
);
645 case DRM_IOCTL_VC5_WAIT_BO
:
646 case DRM_IOCTL_VC5_WAIT_SEQNO
:
647 /* We do all of the vc5 rendering synchronously, so we just
648 * return immediately on the wait ioctls. This ignores any
649 * native rendering to the host BO, so it does mean we race on
650 * front buffer rendering.
654 case DRM_IOCTL_VC5_GET_PARAM
:
655 return vc5_simulator_get_param_ioctl(fd
, args
);
657 case DRM_IOCTL_GEM_CLOSE
:
658 return vc5_simulator_gem_close_ioctl(fd
, args
);
660 case DRM_IOCTL_GEM_OPEN
:
661 case DRM_IOCTL_GEM_FLINK
:
662 return drmIoctl(fd
, request
, args
);
664 fprintf(stderr
, "Unknown ioctl 0x%08x\n", (int)request
);
670 vc5_simulator_init_global(void)
672 mtx_lock(&sim_state
.mutex
);
673 if (sim_state
.refcount
++) {
674 mtx_unlock(&sim_state
.mutex
);
678 sim_state
.v3d
= v3d_hw_auto_new(NULL
);
679 v3d_hw_alloc_mem(sim_state
.v3d
, 256 * 1024 * 1024);
681 v3d_hw_get_mem(sim_state
.v3d
, &sim_state
.mem_size
,
684 sim_state
.heap
= u_mmInit(0, sim_state
.mem_size
);
686 /* Make a block of 0xd0 at address 0 to make sure we don't screw up
689 struct mem_block
*b
= u_mmAllocMem(sim_state
.heap
, 4096, GMP_ALIGN2
, 0);
690 memset(sim_state
.mem
+ b
->ofs
- sim_state
.mem_base
, 0xd0, 4096);
692 mtx_unlock(&sim_state
.mutex
);
695 _mesa_hash_table_create(NULL
,
697 _mesa_key_pointer_equal
);
701 vc5_simulator_init(struct vc5_screen
*screen
)
703 vc5_simulator_init_global();
705 screen
->sim_file
= rzalloc(screen
, struct vc5_simulator_file
);
706 struct vc5_simulator_file
*sim_file
= screen
->sim_file
;
708 screen
->sim_file
->bo_map
=
709 _mesa_hash_table_create(screen
->sim_file
,
711 _mesa_key_pointer_equal
);
713 mtx_lock(&sim_state
.mutex
);
714 _mesa_hash_table_insert(sim_state
.fd_map
, int_to_key(screen
->fd
+ 1),
716 mtx_unlock(&sim_state
.mutex
);
718 sim_file
->gmp
= u_mmAllocMem(sim_state
.heap
, 8096, GMP_ALIGN2
, 0);
719 sim_file
->gmp_vaddr
= (sim_state
.mem
+ sim_file
->gmp
->ofs
-
724 vc5_simulator_destroy(struct vc5_screen
*screen
)
726 mtx_lock(&sim_state
.mutex
);
727 if (!--sim_state
.refcount
) {
728 _mesa_hash_table_destroy(sim_state
.fd_map
, NULL
);
729 u_mmDestroy(sim_state
.heap
);
730 /* No memsetting the struct, because it contains the mutex. */
731 sim_state
.mem
= NULL
;
733 mtx_unlock(&sim_state
.mutex
);
736 #endif /* USE_VC5_SIMULATOR */