broadcom/vc5: Move default attribute value setup to the CSO and fix them.
[mesa.git] / src / gallium / drivers / vc5 / vc5_state.c
1 /*
2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "pipe/p_state.h"
26 #include "util/u_format.h"
27 #include "util/u_inlines.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/u_half.h"
31 #include "util/u_helpers.h"
32
33 #include "vc5_context.h"
34 #include "broadcom/cle/v3d_packet_v33_pack.h"
35
36 static void *
37 vc5_generic_cso_state_create(const void *src, uint32_t size)
38 {
39 void *dst = calloc(1, size);
40 if (!dst)
41 return NULL;
42 memcpy(dst, src, size);
43 return dst;
44 }
45
46 static void
47 vc5_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
48 {
49 free(hwcso);
50 }
51
52 static void
53 vc5_set_blend_color(struct pipe_context *pctx,
54 const struct pipe_blend_color *blend_color)
55 {
56 struct vc5_context *vc5 = vc5_context(pctx);
57 vc5->blend_color.f = *blend_color;
58 for (int i = 0; i < 4; i++) {
59 vc5->blend_color.hf[i] =
60 util_float_to_half(blend_color->color[i]);
61 }
62 vc5->dirty |= VC5_DIRTY_BLEND_COLOR;
63 }
64
65 static void
66 vc5_set_stencil_ref(struct pipe_context *pctx,
67 const struct pipe_stencil_ref *stencil_ref)
68 {
69 struct vc5_context *vc5 = vc5_context(pctx);
70 vc5->stencil_ref = *stencil_ref;
71 vc5->dirty |= VC5_DIRTY_STENCIL_REF;
72 }
73
74 static void
75 vc5_set_clip_state(struct pipe_context *pctx,
76 const struct pipe_clip_state *clip)
77 {
78 struct vc5_context *vc5 = vc5_context(pctx);
79 vc5->clip = *clip;
80 vc5->dirty |= VC5_DIRTY_CLIP;
81 }
82
83 static void
84 vc5_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
85 {
86 struct vc5_context *vc5 = vc5_context(pctx);
87 vc5->sample_mask = sample_mask & ((1 << VC5_MAX_SAMPLES) - 1);
88 vc5->dirty |= VC5_DIRTY_SAMPLE_MASK;
89 }
90
91 static uint16_t
92 float_to_187_half(float f)
93 {
94 return fui(f) >> 16;
95 }
96
97 static void *
98 vc5_create_rasterizer_state(struct pipe_context *pctx,
99 const struct pipe_rasterizer_state *cso)
100 {
101 struct vc5_rasterizer_state *so;
102
103 so = CALLOC_STRUCT(vc5_rasterizer_state);
104 if (!so)
105 return NULL;
106
107 so->base = *cso;
108
109 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
110 * BCM21553).
111 */
112 so->point_size = MAX2(cso->point_size, .125f);
113
114 if (cso->offset_tri) {
115 so->offset_units = float_to_187_half(cso->offset_units);
116 so->offset_factor = float_to_187_half(cso->offset_scale);
117 }
118
119 return so;
120 }
121
122 /* Blend state is baked into shaders. */
123 static void *
124 vc5_create_blend_state(struct pipe_context *pctx,
125 const struct pipe_blend_state *cso)
126 {
127 return vc5_generic_cso_state_create(cso, sizeof(*cso));
128 }
129
130 static void *
131 vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
132 const struct pipe_depth_stencil_alpha_state *cso)
133 {
134 struct vc5_depth_stencil_alpha_state *so;
135
136 so = CALLOC_STRUCT(vc5_depth_stencil_alpha_state);
137 if (!so)
138 return NULL;
139
140 so->base = *cso;
141
142 if (cso->depth.enabled) {
143 /* We only handle early Z in the < direction because otherwise
144 * we'd have to runtime guess which direction to set in the
145 * render config.
146 */
147 so->early_z_enable =
148 ((cso->depth.func == PIPE_FUNC_LESS ||
149 cso->depth.func == PIPE_FUNC_LEQUAL) &&
150 (!cso->stencil[0].enabled ||
151 (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
152 (!cso->stencil[1].enabled ||
153 cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP))));
154 }
155
156 return so;
157 }
158
159 static void
160 vc5_set_polygon_stipple(struct pipe_context *pctx,
161 const struct pipe_poly_stipple *stipple)
162 {
163 struct vc5_context *vc5 = vc5_context(pctx);
164 vc5->stipple = *stipple;
165 vc5->dirty |= VC5_DIRTY_STIPPLE;
166 }
167
168 static void
169 vc5_set_scissor_states(struct pipe_context *pctx,
170 unsigned start_slot,
171 unsigned num_scissors,
172 const struct pipe_scissor_state *scissor)
173 {
174 struct vc5_context *vc5 = vc5_context(pctx);
175
176 vc5->scissor = *scissor;
177 vc5->dirty |= VC5_DIRTY_SCISSOR;
178 }
179
180 static void
181 vc5_set_viewport_states(struct pipe_context *pctx,
182 unsigned start_slot,
183 unsigned num_viewports,
184 const struct pipe_viewport_state *viewport)
185 {
186 struct vc5_context *vc5 = vc5_context(pctx);
187 vc5->viewport = *viewport;
188 vc5->dirty |= VC5_DIRTY_VIEWPORT;
189 }
190
191 static void
192 vc5_set_vertex_buffers(struct pipe_context *pctx,
193 unsigned start_slot, unsigned count,
194 const struct pipe_vertex_buffer *vb)
195 {
196 struct vc5_context *vc5 = vc5_context(pctx);
197 struct vc5_vertexbuf_stateobj *so = &vc5->vertexbuf;
198
199 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
200 start_slot, count);
201 so->count = util_last_bit(so->enabled_mask);
202
203 vc5->dirty |= VC5_DIRTY_VTXBUF;
204 }
205
206 static void
207 vc5_blend_state_bind(struct pipe_context *pctx, void *hwcso)
208 {
209 struct vc5_context *vc5 = vc5_context(pctx);
210 vc5->blend = hwcso;
211 vc5->dirty |= VC5_DIRTY_BLEND;
212 }
213
214 static void
215 vc5_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
216 {
217 struct vc5_context *vc5 = vc5_context(pctx);
218 struct vc5_rasterizer_state *rast = hwcso;
219
220 if (vc5->rasterizer && rast &&
221 vc5->rasterizer->base.flatshade != rast->base.flatshade) {
222 vc5->dirty |= VC5_DIRTY_FLAT_SHADE_FLAGS;
223 }
224
225 vc5->rasterizer = hwcso;
226 vc5->dirty |= VC5_DIRTY_RASTERIZER;
227 }
228
229 static void
230 vc5_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
231 {
232 struct vc5_context *vc5 = vc5_context(pctx);
233 vc5->zsa = hwcso;
234 vc5->dirty |= VC5_DIRTY_ZSA;
235 }
236
237 static void *
238 vc5_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
239 const struct pipe_vertex_element *elements)
240 {
241 struct vc5_context *vc5 = vc5_context(pctx);
242 struct vc5_vertex_stateobj *so = CALLOC_STRUCT(vc5_vertex_stateobj);
243
244 if (!so)
245 return NULL;
246
247 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
248 so->num_elements = num_elements;
249
250 for (int i = 0; i < so->num_elements; i++) {
251 const struct pipe_vertex_element *elem = &elements[i];
252 const struct util_format_description *desc =
253 util_format_description(elem->src_format);
254 uint32_t r_size = desc->channel[0].size;
255
256 struct V3D33_GL_SHADER_STATE_ATTRIBUTE_RECORD attr_unpacked = {
257 /* vec_size == 0 means 4 */
258 .vec_size = desc->nr_channels & 3,
259 .signed_int_type = (desc->channel[0].type ==
260 UTIL_FORMAT_TYPE_SIGNED),
261
262 .normalized_int_type = desc->channel[0].normalized,
263 .read_as_int_uint = desc->channel[0].pure_integer,
264 .instance_divisor = elem->instance_divisor,
265 };
266
267 switch (desc->channel[0].type) {
268 case UTIL_FORMAT_TYPE_FLOAT:
269 if (r_size == 32) {
270 attr_unpacked.type = ATTRIBUTE_FLOAT;
271 } else {
272 assert(r_size == 16);
273 attr_unpacked.type = ATTRIBUTE_HALF_FLOAT;
274 }
275 break;
276
277 case UTIL_FORMAT_TYPE_SIGNED:
278 case UTIL_FORMAT_TYPE_UNSIGNED:
279 switch (r_size) {
280 case 32:
281 attr_unpacked.type = ATTRIBUTE_INT;
282 break;
283 case 16:
284 attr_unpacked.type = ATTRIBUTE_SHORT;
285 break;
286 case 10:
287 attr_unpacked.type = ATTRIBUTE_INT2_10_10_10;
288 break;
289 case 8:
290 attr_unpacked.type = ATTRIBUTE_BYTE;
291 break;
292 default:
293 fprintf(stderr,
294 "format %s unsupported\n",
295 desc->name);
296 attr_unpacked.type = ATTRIBUTE_BYTE;
297 abort();
298 }
299 break;
300
301 default:
302 fprintf(stderr,
303 "format %s unsupported\n",
304 desc->name);
305 abort();
306 }
307
308 const uint32_t size =
309 cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD);
310 V3D33_GL_SHADER_STATE_ATTRIBUTE_RECORD_pack(NULL,
311 (uint8_t *)&so->attrs[i * size],
312 &attr_unpacked);
313 }
314
315 /* Set up the default attribute values in case any of the vertex
316 * elements use them.
317 */
318 so->default_attribute_values = vc5_bo_alloc(vc5->screen,
319 VC5_MAX_ATTRIBUTES *
320 4 * sizeof(float),
321 "default attributes");
322 uint32_t *attrs = vc5_bo_map(so->default_attribute_values);
323 for (int i = 0; i < VC5_MAX_ATTRIBUTES; i++) {
324 attrs[i * 4 + 0] = 0;
325 attrs[i * 4 + 1] = 0;
326 attrs[i * 4 + 2] = 0;
327 if (i < so->num_elements &&
328 util_format_is_pure_integer(so->pipe[i].src_format)) {
329 attrs[i * 4 + 3] = 1;
330 } else {
331 attrs[i * 4 + 3] = fui(1.0);
332 }
333 }
334
335 return so;
336 }
337
338 static void
339 vc5_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
340 {
341 struct vc5_context *vc5 = vc5_context(pctx);
342 vc5->vtx = hwcso;
343 vc5->dirty |= VC5_DIRTY_VTXSTATE;
344 }
345
346 static void
347 vc5_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
348 const struct pipe_constant_buffer *cb)
349 {
350 struct vc5_context *vc5 = vc5_context(pctx);
351 struct vc5_constbuf_stateobj *so = &vc5->constbuf[shader];
352
353 util_copy_constant_buffer(&so->cb[index], cb);
354
355 /* Note that the state tracker can unbind constant buffers by
356 * passing NULL here.
357 */
358 if (unlikely(!cb)) {
359 so->enabled_mask &= ~(1 << index);
360 so->dirty_mask &= ~(1 << index);
361 return;
362 }
363
364 so->enabled_mask |= 1 << index;
365 so->dirty_mask |= 1 << index;
366 vc5->dirty |= VC5_DIRTY_CONSTBUF;
367 }
368
369 static void
370 vc5_set_framebuffer_state(struct pipe_context *pctx,
371 const struct pipe_framebuffer_state *framebuffer)
372 {
373 struct vc5_context *vc5 = vc5_context(pctx);
374 struct pipe_framebuffer_state *cso = &vc5->framebuffer;
375 unsigned i;
376
377 vc5->job = NULL;
378
379 for (i = 0; i < framebuffer->nr_cbufs; i++)
380 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
381 for (; i < vc5->framebuffer.nr_cbufs; i++)
382 pipe_surface_reference(&cso->cbufs[i], NULL);
383
384 cso->nr_cbufs = framebuffer->nr_cbufs;
385
386 pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
387
388 cso->width = framebuffer->width;
389 cso->height = framebuffer->height;
390
391 vc5->dirty |= VC5_DIRTY_FRAMEBUFFER;
392 }
393
394 static struct vc5_texture_stateobj *
395 vc5_get_stage_tex(struct vc5_context *vc5, enum pipe_shader_type shader)
396 {
397 switch (shader) {
398 case PIPE_SHADER_FRAGMENT:
399 vc5->dirty |= VC5_DIRTY_FRAGTEX;
400 return &vc5->fragtex;
401 break;
402 case PIPE_SHADER_VERTEX:
403 vc5->dirty |= VC5_DIRTY_VERTTEX;
404 return &vc5->verttex;
405 break;
406 default:
407 fprintf(stderr, "Unknown shader target %d\n", shader);
408 abort();
409 }
410 }
411
412 static uint32_t translate_wrap(uint32_t pipe_wrap, bool using_nearest)
413 {
414 switch (pipe_wrap) {
415 case PIPE_TEX_WRAP_REPEAT:
416 return 0;
417 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
418 return 1;
419 case PIPE_TEX_WRAP_MIRROR_REPEAT:
420 return 2;
421 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
422 return 3;
423 case PIPE_TEX_WRAP_CLAMP:
424 return (using_nearest ? 1 : 3);
425 default:
426 unreachable("Unknown wrap mode");
427 }
428 }
429
430
431 static void *
432 vc5_create_sampler_state(struct pipe_context *pctx,
433 const struct pipe_sampler_state *cso)
434 {
435 struct vc5_sampler_state *so = CALLOC_STRUCT(vc5_sampler_state);
436
437 if (!so)
438 return NULL;
439
440 memcpy(so, cso, sizeof(*cso));
441
442 bool either_nearest =
443 (cso->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
444 cso->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
445
446 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
447 .s_wrap_mode = translate_wrap(cso->wrap_s, either_nearest),
448 .t_wrap_mode = translate_wrap(cso->wrap_t, either_nearest),
449 .r_wrap_mode = translate_wrap(cso->wrap_r, either_nearest),
450 };
451 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
452 (uint8_t *)&so->p0,
453 &p0_unpacked);
454
455 struct V3D33_TEXTURE_SHADER_STATE state_unpacked = {
456 cl_packet_header(TEXTURE_SHADER_STATE),
457
458 .min_level_of_detail = MAX2(cso->min_lod, 0.0),
459 .depth_compare_function = cso->compare_func,
460 .fixed_bias = cso->lod_bias,
461 };
462 STATIC_ASSERT(ARRAY_SIZE(so->texture_shader_state) ==
463 cl_packet_length(TEXTURE_SHADER_STATE));
464 cl_packet_pack(TEXTURE_SHADER_STATE)(NULL, so->texture_shader_state,
465 &state_unpacked);
466
467 return so;
468 }
469
470 static void
471 vc5_sampler_states_bind(struct pipe_context *pctx,
472 enum pipe_shader_type shader, unsigned start,
473 unsigned nr, void **hwcso)
474 {
475 struct vc5_context *vc5 = vc5_context(pctx);
476 struct vc5_texture_stateobj *stage_tex = vc5_get_stage_tex(vc5, shader);
477
478 assert(start == 0);
479 unsigned i;
480 unsigned new_nr = 0;
481
482 for (i = 0; i < nr; i++) {
483 if (hwcso[i])
484 new_nr = i + 1;
485 stage_tex->samplers[i] = hwcso[i];
486 }
487
488 for (; i < stage_tex->num_samplers; i++) {
489 stage_tex->samplers[i] = NULL;
490 }
491
492 stage_tex->num_samplers = new_nr;
493 }
494
495 static uint32_t
496 translate_swizzle(unsigned char pipe_swizzle)
497 {
498 switch (pipe_swizzle) {
499 case PIPE_SWIZZLE_0:
500 return 0;
501 case PIPE_SWIZZLE_1:
502 return 1;
503 case PIPE_SWIZZLE_X:
504 case PIPE_SWIZZLE_Y:
505 case PIPE_SWIZZLE_Z:
506 case PIPE_SWIZZLE_W:
507 return 2 + pipe_swizzle;
508 default:
509 unreachable("unknown swizzle");
510 }
511 }
512
513 static struct pipe_sampler_view *
514 vc5_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
515 const struct pipe_sampler_view *cso)
516 {
517 struct vc5_sampler_view *so = CALLOC_STRUCT(vc5_sampler_view);
518 struct vc5_resource *rsc = vc5_resource(prsc);
519
520 if (!so)
521 return NULL;
522
523 so->base = *cso;
524
525 pipe_reference(NULL, &prsc->reference);
526
527 struct V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1 unpacked = {
528 };
529
530 unpacked.return_word_0_of_texture_data = true;
531 if (vc5_get_tex_return_size(cso->format) == 16) {
532 unpacked.return_word_1_of_texture_data = true;
533 } else {
534 int chans = vc5_get_tex_return_channels(cso->format);
535
536 if (chans > 1)
537 unpacked.return_word_1_of_texture_data = true;
538 if (chans > 2)
539 unpacked.return_word_2_of_texture_data = true;
540 if (chans > 3)
541 unpacked.return_word_3_of_texture_data = true;
542 }
543
544 V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1_pack(NULL,
545 (uint8_t *)&so->p1,
546 &unpacked);
547
548 /* Compute the sampler view's swizzle up front. This will be plugged
549 * into either the sampler (for 16-bit returns) or the shader's
550 * texture key (for 32)
551 */
552 uint8_t view_swizzle[4] = {
553 cso->swizzle_r,
554 cso->swizzle_g,
555 cso->swizzle_b,
556 cso->swizzle_a
557 };
558 const uint8_t *fmt_swizzle = vc5_get_format_swizzle(so->base.format);
559 util_format_compose_swizzles(fmt_swizzle, view_swizzle, so->swizzle);
560
561 so->base.texture = prsc;
562 so->base.reference.count = 1;
563 so->base.context = pctx;
564
565 struct V3D33_TEXTURE_SHADER_STATE state_unpacked = {
566 cl_packet_header(TEXTURE_SHADER_STATE),
567
568 .image_width = prsc->width0,
569 .image_height = prsc->height0,
570 .image_depth = prsc->depth0,
571
572 .texture_type = rsc->tex_format,
573 .srgb = util_format_is_srgb(cso->format),
574
575 .base_level = cso->u.tex.first_level,
576 .array_stride_64_byte_aligned = rsc->cube_map_stride / 64,
577 };
578
579 /* Note: Contrary to the docs, the swizzle still applies even
580 * if the return size is 32. It's just that you probably want
581 * to swizzle in the shader, because you need the Y/Z/W
582 * channels to be defined.
583 */
584 if (vc5_get_tex_return_size(cso->format) != 32) {
585 state_unpacked.swizzle_r = translate_swizzle(so->swizzle[0]);
586 state_unpacked.swizzle_g = translate_swizzle(so->swizzle[1]);
587 state_unpacked.swizzle_b = translate_swizzle(so->swizzle[2]);
588 state_unpacked.swizzle_a = translate_swizzle(so->swizzle[3]);
589 } else {
590 state_unpacked.swizzle_r = translate_swizzle(PIPE_SWIZZLE_X);
591 state_unpacked.swizzle_g = translate_swizzle(PIPE_SWIZZLE_Y);
592 state_unpacked.swizzle_b = translate_swizzle(PIPE_SWIZZLE_Z);
593 state_unpacked.swizzle_a = translate_swizzle(PIPE_SWIZZLE_W);
594 }
595
596 /* XXX: While we need to use this flag to enable tiled
597 * resource sharing (even a small shared buffer should be UIF,
598 * not UBLINEAR or raster), this is also at the moment
599 * patching up the fact that our resource layout's decisions
600 * about XOR don't quite match the HW's.
601 */
602 switch (rsc->slices[0].tiling) {
603 case VC5_TILING_UIF_NO_XOR:
604 case VC5_TILING_UIF_XOR:
605 state_unpacked.level_0_is_strictly_uif = true;
606 state_unpacked.level_0_xor_enable = false;
607 break;
608 default:
609 break;
610 }
611
612 STATIC_ASSERT(ARRAY_SIZE(so->texture_shader_state) ==
613 cl_packet_length(TEXTURE_SHADER_STATE));
614 cl_packet_pack(TEXTURE_SHADER_STATE)(NULL, so->texture_shader_state,
615 &state_unpacked);
616
617 return &so->base;
618 }
619
620 static void
621 vc5_sampler_view_destroy(struct pipe_context *pctx,
622 struct pipe_sampler_view *view)
623 {
624 pipe_resource_reference(&view->texture, NULL);
625 free(view);
626 }
627
628 static void
629 vc5_set_sampler_views(struct pipe_context *pctx,
630 enum pipe_shader_type shader,
631 unsigned start, unsigned nr,
632 struct pipe_sampler_view **views)
633 {
634 struct vc5_context *vc5 = vc5_context(pctx);
635 struct vc5_texture_stateobj *stage_tex = vc5_get_stage_tex(vc5, shader);
636 unsigned i;
637 unsigned new_nr = 0;
638
639 assert(start == 0);
640
641 for (i = 0; i < nr; i++) {
642 if (views[i])
643 new_nr = i + 1;
644 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
645 }
646
647 for (; i < stage_tex->num_textures; i++) {
648 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
649 }
650
651 stage_tex->num_textures = new_nr;
652 }
653
654 static struct pipe_stream_output_target *
655 vc5_create_stream_output_target(struct pipe_context *pctx,
656 struct pipe_resource *prsc,
657 unsigned buffer_offset,
658 unsigned buffer_size)
659 {
660 struct pipe_stream_output_target *target;
661
662 target = CALLOC_STRUCT(pipe_stream_output_target);
663 if (!target)
664 return NULL;
665
666 pipe_reference_init(&target->reference, 1);
667 pipe_resource_reference(&target->buffer, prsc);
668
669 target->context = pctx;
670 target->buffer_offset = buffer_offset;
671 target->buffer_size = buffer_size;
672
673 return target;
674 }
675
676 static void
677 vc5_stream_output_target_destroy(struct pipe_context *pctx,
678 struct pipe_stream_output_target *target)
679 {
680 pipe_resource_reference(&target->buffer, NULL);
681 free(target);
682 }
683
684 static void
685 vc5_set_stream_output_targets(struct pipe_context *pctx,
686 unsigned num_targets,
687 struct pipe_stream_output_target **targets,
688 const unsigned *offsets)
689 {
690 struct vc5_context *ctx = vc5_context(pctx);
691 struct vc5_streamout_stateobj *so = &ctx->streamout;
692 unsigned i;
693
694 assert(num_targets <= ARRAY_SIZE(so->targets));
695
696 for (i = 0; i < num_targets; i++)
697 pipe_so_target_reference(&so->targets[i], targets[i]);
698
699 for (; i < so->num_targets; i++)
700 pipe_so_target_reference(&so->targets[i], NULL);
701
702 so->num_targets = num_targets;
703
704 ctx->dirty |= VC5_DIRTY_STREAMOUT;
705 }
706
707 void
708 vc5_state_init(struct pipe_context *pctx)
709 {
710 pctx->set_blend_color = vc5_set_blend_color;
711 pctx->set_stencil_ref = vc5_set_stencil_ref;
712 pctx->set_clip_state = vc5_set_clip_state;
713 pctx->set_sample_mask = vc5_set_sample_mask;
714 pctx->set_constant_buffer = vc5_set_constant_buffer;
715 pctx->set_framebuffer_state = vc5_set_framebuffer_state;
716 pctx->set_polygon_stipple = vc5_set_polygon_stipple;
717 pctx->set_scissor_states = vc5_set_scissor_states;
718 pctx->set_viewport_states = vc5_set_viewport_states;
719
720 pctx->set_vertex_buffers = vc5_set_vertex_buffers;
721
722 pctx->create_blend_state = vc5_create_blend_state;
723 pctx->bind_blend_state = vc5_blend_state_bind;
724 pctx->delete_blend_state = vc5_generic_cso_state_delete;
725
726 pctx->create_rasterizer_state = vc5_create_rasterizer_state;
727 pctx->bind_rasterizer_state = vc5_rasterizer_state_bind;
728 pctx->delete_rasterizer_state = vc5_generic_cso_state_delete;
729
730 pctx->create_depth_stencil_alpha_state = vc5_create_depth_stencil_alpha_state;
731 pctx->bind_depth_stencil_alpha_state = vc5_zsa_state_bind;
732 pctx->delete_depth_stencil_alpha_state = vc5_generic_cso_state_delete;
733
734 pctx->create_vertex_elements_state = vc5_vertex_state_create;
735 pctx->delete_vertex_elements_state = vc5_generic_cso_state_delete;
736 pctx->bind_vertex_elements_state = vc5_vertex_state_bind;
737
738 pctx->create_sampler_state = vc5_create_sampler_state;
739 pctx->delete_sampler_state = vc5_generic_cso_state_delete;
740 pctx->bind_sampler_states = vc5_sampler_states_bind;
741
742 pctx->create_sampler_view = vc5_create_sampler_view;
743 pctx->sampler_view_destroy = vc5_sampler_view_destroy;
744 pctx->set_sampler_views = vc5_set_sampler_views;
745
746 pctx->create_stream_output_target = vc5_create_stream_output_target;
747 pctx->stream_output_target_destroy = vc5_stream_output_target_destroy;
748 pctx->set_stream_output_targets = vc5_set_stream_output_targets;
749 }