broadcom/vc5: Move most of the shader state attribute record to the CSO.
[mesa.git] / src / gallium / drivers / vc5 / vc5_state.c
1 /*
2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include "pipe/p_state.h"
26 #include "util/u_format.h"
27 #include "util/u_inlines.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/u_half.h"
31 #include "util/u_helpers.h"
32
33 #include "vc5_context.h"
34 #include "broadcom/cle/v3d_packet_v33_pack.h"
35
36 static void *
37 vc5_generic_cso_state_create(const void *src, uint32_t size)
38 {
39 void *dst = calloc(1, size);
40 if (!dst)
41 return NULL;
42 memcpy(dst, src, size);
43 return dst;
44 }
45
46 static void
47 vc5_generic_cso_state_delete(struct pipe_context *pctx, void *hwcso)
48 {
49 free(hwcso);
50 }
51
52 static void
53 vc5_set_blend_color(struct pipe_context *pctx,
54 const struct pipe_blend_color *blend_color)
55 {
56 struct vc5_context *vc5 = vc5_context(pctx);
57 vc5->blend_color.f = *blend_color;
58 for (int i = 0; i < 4; i++) {
59 vc5->blend_color.hf[i] =
60 util_float_to_half(blend_color->color[i]);
61 }
62 vc5->dirty |= VC5_DIRTY_BLEND_COLOR;
63 }
64
65 static void
66 vc5_set_stencil_ref(struct pipe_context *pctx,
67 const struct pipe_stencil_ref *stencil_ref)
68 {
69 struct vc5_context *vc5 = vc5_context(pctx);
70 vc5->stencil_ref = *stencil_ref;
71 vc5->dirty |= VC5_DIRTY_STENCIL_REF;
72 }
73
74 static void
75 vc5_set_clip_state(struct pipe_context *pctx,
76 const struct pipe_clip_state *clip)
77 {
78 struct vc5_context *vc5 = vc5_context(pctx);
79 vc5->clip = *clip;
80 vc5->dirty |= VC5_DIRTY_CLIP;
81 }
82
83 static void
84 vc5_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
85 {
86 struct vc5_context *vc5 = vc5_context(pctx);
87 vc5->sample_mask = sample_mask & ((1 << VC5_MAX_SAMPLES) - 1);
88 vc5->dirty |= VC5_DIRTY_SAMPLE_MASK;
89 }
90
91 static uint16_t
92 float_to_187_half(float f)
93 {
94 return fui(f) >> 16;
95 }
96
97 static void *
98 vc5_create_rasterizer_state(struct pipe_context *pctx,
99 const struct pipe_rasterizer_state *cso)
100 {
101 struct vc5_rasterizer_state *so;
102
103 so = CALLOC_STRUCT(vc5_rasterizer_state);
104 if (!so)
105 return NULL;
106
107 so->base = *cso;
108
109 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
110 * BCM21553).
111 */
112 so->point_size = MAX2(cso->point_size, .125f);
113
114 if (cso->offset_tri) {
115 so->offset_units = float_to_187_half(cso->offset_units);
116 so->offset_factor = float_to_187_half(cso->offset_scale);
117 }
118
119 return so;
120 }
121
122 /* Blend state is baked into shaders. */
123 static void *
124 vc5_create_blend_state(struct pipe_context *pctx,
125 const struct pipe_blend_state *cso)
126 {
127 return vc5_generic_cso_state_create(cso, sizeof(*cso));
128 }
129
130 static void *
131 vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
132 const struct pipe_depth_stencil_alpha_state *cso)
133 {
134 struct vc5_depth_stencil_alpha_state *so;
135
136 so = CALLOC_STRUCT(vc5_depth_stencil_alpha_state);
137 if (!so)
138 return NULL;
139
140 so->base = *cso;
141
142 if (cso->depth.enabled) {
143 /* We only handle early Z in the < direction because otherwise
144 * we'd have to runtime guess which direction to set in the
145 * render config.
146 */
147 so->early_z_enable =
148 ((cso->depth.func == PIPE_FUNC_LESS ||
149 cso->depth.func == PIPE_FUNC_LEQUAL) &&
150 (!cso->stencil[0].enabled ||
151 (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
152 (!cso->stencil[1].enabled ||
153 cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP))));
154 }
155
156 return so;
157 }
158
159 static void
160 vc5_set_polygon_stipple(struct pipe_context *pctx,
161 const struct pipe_poly_stipple *stipple)
162 {
163 struct vc5_context *vc5 = vc5_context(pctx);
164 vc5->stipple = *stipple;
165 vc5->dirty |= VC5_DIRTY_STIPPLE;
166 }
167
168 static void
169 vc5_set_scissor_states(struct pipe_context *pctx,
170 unsigned start_slot,
171 unsigned num_scissors,
172 const struct pipe_scissor_state *scissor)
173 {
174 struct vc5_context *vc5 = vc5_context(pctx);
175
176 vc5->scissor = *scissor;
177 vc5->dirty |= VC5_DIRTY_SCISSOR;
178 }
179
180 static void
181 vc5_set_viewport_states(struct pipe_context *pctx,
182 unsigned start_slot,
183 unsigned num_viewports,
184 const struct pipe_viewport_state *viewport)
185 {
186 struct vc5_context *vc5 = vc5_context(pctx);
187 vc5->viewport = *viewport;
188 vc5->dirty |= VC5_DIRTY_VIEWPORT;
189 }
190
191 static void
192 vc5_set_vertex_buffers(struct pipe_context *pctx,
193 unsigned start_slot, unsigned count,
194 const struct pipe_vertex_buffer *vb)
195 {
196 struct vc5_context *vc5 = vc5_context(pctx);
197 struct vc5_vertexbuf_stateobj *so = &vc5->vertexbuf;
198
199 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
200 start_slot, count);
201 so->count = util_last_bit(so->enabled_mask);
202
203 vc5->dirty |= VC5_DIRTY_VTXBUF;
204 }
205
206 static void
207 vc5_blend_state_bind(struct pipe_context *pctx, void *hwcso)
208 {
209 struct vc5_context *vc5 = vc5_context(pctx);
210 vc5->blend = hwcso;
211 vc5->dirty |= VC5_DIRTY_BLEND;
212 }
213
214 static void
215 vc5_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
216 {
217 struct vc5_context *vc5 = vc5_context(pctx);
218 struct vc5_rasterizer_state *rast = hwcso;
219
220 if (vc5->rasterizer && rast &&
221 vc5->rasterizer->base.flatshade != rast->base.flatshade) {
222 vc5->dirty |= VC5_DIRTY_FLAT_SHADE_FLAGS;
223 }
224
225 vc5->rasterizer = hwcso;
226 vc5->dirty |= VC5_DIRTY_RASTERIZER;
227 }
228
229 static void
230 vc5_zsa_state_bind(struct pipe_context *pctx, void *hwcso)
231 {
232 struct vc5_context *vc5 = vc5_context(pctx);
233 vc5->zsa = hwcso;
234 vc5->dirty |= VC5_DIRTY_ZSA;
235 }
236
237 static void *
238 vc5_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
239 const struct pipe_vertex_element *elements)
240 {
241 struct vc5_vertex_stateobj *so = CALLOC_STRUCT(vc5_vertex_stateobj);
242
243 if (!so)
244 return NULL;
245
246 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
247 so->num_elements = num_elements;
248
249 for (int i = 0; i < so->num_elements; i++) {
250 const struct pipe_vertex_element *elem = &elements[i];
251 const struct util_format_description *desc =
252 util_format_description(elem->src_format);
253 uint32_t r_size = desc->channel[0].size;
254
255 struct V3D33_GL_SHADER_STATE_ATTRIBUTE_RECORD attr_unpacked = {
256 /* vec_size == 0 means 4 */
257 .vec_size = desc->nr_channels & 3,
258 .signed_int_type = (desc->channel[0].type ==
259 UTIL_FORMAT_TYPE_SIGNED),
260
261 .normalized_int_type = desc->channel[0].normalized,
262 .read_as_int_uint = desc->channel[0].pure_integer,
263 .instance_divisor = elem->instance_divisor,
264 };
265
266 switch (desc->channel[0].type) {
267 case UTIL_FORMAT_TYPE_FLOAT:
268 if (r_size == 32) {
269 attr_unpacked.type = ATTRIBUTE_FLOAT;
270 } else {
271 assert(r_size == 16);
272 attr_unpacked.type = ATTRIBUTE_HALF_FLOAT;
273 }
274 break;
275
276 case UTIL_FORMAT_TYPE_SIGNED:
277 case UTIL_FORMAT_TYPE_UNSIGNED:
278 switch (r_size) {
279 case 32:
280 attr_unpacked.type = ATTRIBUTE_INT;
281 break;
282 case 16:
283 attr_unpacked.type = ATTRIBUTE_SHORT;
284 break;
285 case 10:
286 attr_unpacked.type = ATTRIBUTE_INT2_10_10_10;
287 break;
288 case 8:
289 attr_unpacked.type = ATTRIBUTE_BYTE;
290 break;
291 default:
292 fprintf(stderr,
293 "format %s unsupported\n",
294 desc->name);
295 attr_unpacked.type = ATTRIBUTE_BYTE;
296 abort();
297 }
298 break;
299
300 default:
301 fprintf(stderr,
302 "format %s unsupported\n",
303 desc->name);
304 abort();
305 }
306
307 const uint32_t size =
308 cl_packet_length(GL_SHADER_STATE_ATTRIBUTE_RECORD);
309 V3D33_GL_SHADER_STATE_ATTRIBUTE_RECORD_pack(NULL,
310 (uint8_t *)&so->attrs[i * size],
311 &attr_unpacked);
312 }
313
314
315 return so;
316 }
317
318 static void
319 vc5_vertex_state_bind(struct pipe_context *pctx, void *hwcso)
320 {
321 struct vc5_context *vc5 = vc5_context(pctx);
322 vc5->vtx = hwcso;
323 vc5->dirty |= VC5_DIRTY_VTXSTATE;
324 }
325
326 static void
327 vc5_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
328 const struct pipe_constant_buffer *cb)
329 {
330 struct vc5_context *vc5 = vc5_context(pctx);
331 struct vc5_constbuf_stateobj *so = &vc5->constbuf[shader];
332
333 util_copy_constant_buffer(&so->cb[index], cb);
334
335 /* Note that the state tracker can unbind constant buffers by
336 * passing NULL here.
337 */
338 if (unlikely(!cb)) {
339 so->enabled_mask &= ~(1 << index);
340 so->dirty_mask &= ~(1 << index);
341 return;
342 }
343
344 so->enabled_mask |= 1 << index;
345 so->dirty_mask |= 1 << index;
346 vc5->dirty |= VC5_DIRTY_CONSTBUF;
347 }
348
349 static void
350 vc5_set_framebuffer_state(struct pipe_context *pctx,
351 const struct pipe_framebuffer_state *framebuffer)
352 {
353 struct vc5_context *vc5 = vc5_context(pctx);
354 struct pipe_framebuffer_state *cso = &vc5->framebuffer;
355 unsigned i;
356
357 vc5->job = NULL;
358
359 for (i = 0; i < framebuffer->nr_cbufs; i++)
360 pipe_surface_reference(&cso->cbufs[i], framebuffer->cbufs[i]);
361 for (; i < vc5->framebuffer.nr_cbufs; i++)
362 pipe_surface_reference(&cso->cbufs[i], NULL);
363
364 cso->nr_cbufs = framebuffer->nr_cbufs;
365
366 pipe_surface_reference(&cso->zsbuf, framebuffer->zsbuf);
367
368 cso->width = framebuffer->width;
369 cso->height = framebuffer->height;
370
371 vc5->dirty |= VC5_DIRTY_FRAMEBUFFER;
372 }
373
374 static struct vc5_texture_stateobj *
375 vc5_get_stage_tex(struct vc5_context *vc5, enum pipe_shader_type shader)
376 {
377 switch (shader) {
378 case PIPE_SHADER_FRAGMENT:
379 vc5->dirty |= VC5_DIRTY_FRAGTEX;
380 return &vc5->fragtex;
381 break;
382 case PIPE_SHADER_VERTEX:
383 vc5->dirty |= VC5_DIRTY_VERTTEX;
384 return &vc5->verttex;
385 break;
386 default:
387 fprintf(stderr, "Unknown shader target %d\n", shader);
388 abort();
389 }
390 }
391
392 static uint32_t translate_wrap(uint32_t pipe_wrap, bool using_nearest)
393 {
394 switch (pipe_wrap) {
395 case PIPE_TEX_WRAP_REPEAT:
396 return 0;
397 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
398 return 1;
399 case PIPE_TEX_WRAP_MIRROR_REPEAT:
400 return 2;
401 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
402 return 3;
403 case PIPE_TEX_WRAP_CLAMP:
404 return (using_nearest ? 1 : 3);
405 default:
406 unreachable("Unknown wrap mode");
407 }
408 }
409
410
411 static void *
412 vc5_create_sampler_state(struct pipe_context *pctx,
413 const struct pipe_sampler_state *cso)
414 {
415 struct vc5_sampler_state *so = CALLOC_STRUCT(vc5_sampler_state);
416
417 if (!so)
418 return NULL;
419
420 memcpy(so, cso, sizeof(*cso));
421
422 bool either_nearest =
423 (cso->mag_img_filter == PIPE_TEX_MIPFILTER_NEAREST ||
424 cso->min_img_filter == PIPE_TEX_MIPFILTER_NEAREST);
425
426 struct V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1 p0_unpacked = {
427 .s_wrap_mode = translate_wrap(cso->wrap_s, either_nearest),
428 .t_wrap_mode = translate_wrap(cso->wrap_t, either_nearest),
429 .r_wrap_mode = translate_wrap(cso->wrap_r, either_nearest),
430 };
431 V3D33_TEXTURE_UNIFORM_PARAMETER_0_CFG_MODE1_pack(NULL,
432 (uint8_t *)&so->p0,
433 &p0_unpacked);
434
435 struct V3D33_TEXTURE_SHADER_STATE state_unpacked = {
436 cl_packet_header(TEXTURE_SHADER_STATE),
437
438 .min_level_of_detail = MAX2(cso->min_lod, 0.0),
439 .depth_compare_function = cso->compare_func,
440 .fixed_bias = cso->lod_bias,
441 };
442 STATIC_ASSERT(ARRAY_SIZE(so->texture_shader_state) ==
443 cl_packet_length(TEXTURE_SHADER_STATE));
444 cl_packet_pack(TEXTURE_SHADER_STATE)(NULL, so->texture_shader_state,
445 &state_unpacked);
446
447 return so;
448 }
449
450 static void
451 vc5_sampler_states_bind(struct pipe_context *pctx,
452 enum pipe_shader_type shader, unsigned start,
453 unsigned nr, void **hwcso)
454 {
455 struct vc5_context *vc5 = vc5_context(pctx);
456 struct vc5_texture_stateobj *stage_tex = vc5_get_stage_tex(vc5, shader);
457
458 assert(start == 0);
459 unsigned i;
460 unsigned new_nr = 0;
461
462 for (i = 0; i < nr; i++) {
463 if (hwcso[i])
464 new_nr = i + 1;
465 stage_tex->samplers[i] = hwcso[i];
466 }
467
468 for (; i < stage_tex->num_samplers; i++) {
469 stage_tex->samplers[i] = NULL;
470 }
471
472 stage_tex->num_samplers = new_nr;
473 }
474
475 static uint32_t
476 translate_swizzle(unsigned char pipe_swizzle)
477 {
478 switch (pipe_swizzle) {
479 case PIPE_SWIZZLE_0:
480 return 0;
481 case PIPE_SWIZZLE_1:
482 return 1;
483 case PIPE_SWIZZLE_X:
484 case PIPE_SWIZZLE_Y:
485 case PIPE_SWIZZLE_Z:
486 case PIPE_SWIZZLE_W:
487 return 2 + pipe_swizzle;
488 default:
489 unreachable("unknown swizzle");
490 }
491 }
492
493 static struct pipe_sampler_view *
494 vc5_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
495 const struct pipe_sampler_view *cso)
496 {
497 struct vc5_sampler_view *so = CALLOC_STRUCT(vc5_sampler_view);
498 struct vc5_resource *rsc = vc5_resource(prsc);
499
500 if (!so)
501 return NULL;
502
503 so->base = *cso;
504
505 pipe_reference(NULL, &prsc->reference);
506
507 struct V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1 unpacked = {
508 };
509
510 unpacked.return_word_0_of_texture_data = true;
511 if (vc5_get_tex_return_size(cso->format) == 16) {
512 unpacked.return_word_1_of_texture_data = true;
513 } else {
514 int chans = vc5_get_tex_return_channels(cso->format);
515
516 if (chans > 1)
517 unpacked.return_word_1_of_texture_data = true;
518 if (chans > 2)
519 unpacked.return_word_2_of_texture_data = true;
520 if (chans > 3)
521 unpacked.return_word_3_of_texture_data = true;
522 }
523
524 V3D33_TEXTURE_UNIFORM_PARAMETER_1_CFG_MODE1_pack(NULL,
525 (uint8_t *)&so->p1,
526 &unpacked);
527
528 /* Compute the sampler view's swizzle up front. This will be plugged
529 * into either the sampler (for 16-bit returns) or the shader's
530 * texture key (for 32)
531 */
532 uint8_t view_swizzle[4] = {
533 cso->swizzle_r,
534 cso->swizzle_g,
535 cso->swizzle_b,
536 cso->swizzle_a
537 };
538 const uint8_t *fmt_swizzle = vc5_get_format_swizzle(so->base.format);
539 util_format_compose_swizzles(fmt_swizzle, view_swizzle, so->swizzle);
540
541 so->base.texture = prsc;
542 so->base.reference.count = 1;
543 so->base.context = pctx;
544
545 struct V3D33_TEXTURE_SHADER_STATE state_unpacked = {
546 cl_packet_header(TEXTURE_SHADER_STATE),
547
548 .image_width = prsc->width0,
549 .image_height = prsc->height0,
550 .image_depth = prsc->depth0,
551
552 .texture_type = rsc->tex_format,
553 .srgb = util_format_is_srgb(cso->format),
554
555 .base_level = cso->u.tex.first_level,
556 .array_stride_64_byte_aligned = rsc->cube_map_stride / 64,
557 };
558
559 /* Note: Contrary to the docs, the swizzle still applies even
560 * if the return size is 32. It's just that you probably want
561 * to swizzle in the shader, because you need the Y/Z/W
562 * channels to be defined.
563 */
564 if (vc5_get_tex_return_size(cso->format) != 32) {
565 state_unpacked.swizzle_r = translate_swizzle(so->swizzle[0]);
566 state_unpacked.swizzle_g = translate_swizzle(so->swizzle[1]);
567 state_unpacked.swizzle_b = translate_swizzle(so->swizzle[2]);
568 state_unpacked.swizzle_a = translate_swizzle(so->swizzle[3]);
569 } else {
570 state_unpacked.swizzle_r = translate_swizzle(PIPE_SWIZZLE_X);
571 state_unpacked.swizzle_g = translate_swizzle(PIPE_SWIZZLE_Y);
572 state_unpacked.swizzle_b = translate_swizzle(PIPE_SWIZZLE_Z);
573 state_unpacked.swizzle_a = translate_swizzle(PIPE_SWIZZLE_W);
574 }
575
576 /* XXX: While we need to use this flag to enable tiled
577 * resource sharing (even a small shared buffer should be UIF,
578 * not UBLINEAR or raster), this is also at the moment
579 * patching up the fact that our resource layout's decisions
580 * about XOR don't quite match the HW's.
581 */
582 switch (rsc->slices[0].tiling) {
583 case VC5_TILING_UIF_NO_XOR:
584 case VC5_TILING_UIF_XOR:
585 state_unpacked.level_0_is_strictly_uif = true;
586 state_unpacked.level_0_xor_enable = false;
587 break;
588 default:
589 break;
590 }
591
592 STATIC_ASSERT(ARRAY_SIZE(so->texture_shader_state) ==
593 cl_packet_length(TEXTURE_SHADER_STATE));
594 cl_packet_pack(TEXTURE_SHADER_STATE)(NULL, so->texture_shader_state,
595 &state_unpacked);
596
597 return &so->base;
598 }
599
600 static void
601 vc5_sampler_view_destroy(struct pipe_context *pctx,
602 struct pipe_sampler_view *view)
603 {
604 pipe_resource_reference(&view->texture, NULL);
605 free(view);
606 }
607
608 static void
609 vc5_set_sampler_views(struct pipe_context *pctx,
610 enum pipe_shader_type shader,
611 unsigned start, unsigned nr,
612 struct pipe_sampler_view **views)
613 {
614 struct vc5_context *vc5 = vc5_context(pctx);
615 struct vc5_texture_stateobj *stage_tex = vc5_get_stage_tex(vc5, shader);
616 unsigned i;
617 unsigned new_nr = 0;
618
619 assert(start == 0);
620
621 for (i = 0; i < nr; i++) {
622 if (views[i])
623 new_nr = i + 1;
624 pipe_sampler_view_reference(&stage_tex->textures[i], views[i]);
625 }
626
627 for (; i < stage_tex->num_textures; i++) {
628 pipe_sampler_view_reference(&stage_tex->textures[i], NULL);
629 }
630
631 stage_tex->num_textures = new_nr;
632 }
633
634 static struct pipe_stream_output_target *
635 vc5_create_stream_output_target(struct pipe_context *pctx,
636 struct pipe_resource *prsc,
637 unsigned buffer_offset,
638 unsigned buffer_size)
639 {
640 struct pipe_stream_output_target *target;
641
642 target = CALLOC_STRUCT(pipe_stream_output_target);
643 if (!target)
644 return NULL;
645
646 pipe_reference_init(&target->reference, 1);
647 pipe_resource_reference(&target->buffer, prsc);
648
649 target->context = pctx;
650 target->buffer_offset = buffer_offset;
651 target->buffer_size = buffer_size;
652
653 return target;
654 }
655
656 static void
657 vc5_stream_output_target_destroy(struct pipe_context *pctx,
658 struct pipe_stream_output_target *target)
659 {
660 pipe_resource_reference(&target->buffer, NULL);
661 free(target);
662 }
663
664 static void
665 vc5_set_stream_output_targets(struct pipe_context *pctx,
666 unsigned num_targets,
667 struct pipe_stream_output_target **targets,
668 const unsigned *offsets)
669 {
670 struct vc5_context *ctx = vc5_context(pctx);
671 struct vc5_streamout_stateobj *so = &ctx->streamout;
672 unsigned i;
673
674 assert(num_targets <= ARRAY_SIZE(so->targets));
675
676 for (i = 0; i < num_targets; i++)
677 pipe_so_target_reference(&so->targets[i], targets[i]);
678
679 for (; i < so->num_targets; i++)
680 pipe_so_target_reference(&so->targets[i], NULL);
681
682 so->num_targets = num_targets;
683
684 ctx->dirty |= VC5_DIRTY_STREAMOUT;
685 }
686
687 void
688 vc5_state_init(struct pipe_context *pctx)
689 {
690 pctx->set_blend_color = vc5_set_blend_color;
691 pctx->set_stencil_ref = vc5_set_stencil_ref;
692 pctx->set_clip_state = vc5_set_clip_state;
693 pctx->set_sample_mask = vc5_set_sample_mask;
694 pctx->set_constant_buffer = vc5_set_constant_buffer;
695 pctx->set_framebuffer_state = vc5_set_framebuffer_state;
696 pctx->set_polygon_stipple = vc5_set_polygon_stipple;
697 pctx->set_scissor_states = vc5_set_scissor_states;
698 pctx->set_viewport_states = vc5_set_viewport_states;
699
700 pctx->set_vertex_buffers = vc5_set_vertex_buffers;
701
702 pctx->create_blend_state = vc5_create_blend_state;
703 pctx->bind_blend_state = vc5_blend_state_bind;
704 pctx->delete_blend_state = vc5_generic_cso_state_delete;
705
706 pctx->create_rasterizer_state = vc5_create_rasterizer_state;
707 pctx->bind_rasterizer_state = vc5_rasterizer_state_bind;
708 pctx->delete_rasterizer_state = vc5_generic_cso_state_delete;
709
710 pctx->create_depth_stencil_alpha_state = vc5_create_depth_stencil_alpha_state;
711 pctx->bind_depth_stencil_alpha_state = vc5_zsa_state_bind;
712 pctx->delete_depth_stencil_alpha_state = vc5_generic_cso_state_delete;
713
714 pctx->create_vertex_elements_state = vc5_vertex_state_create;
715 pctx->delete_vertex_elements_state = vc5_generic_cso_state_delete;
716 pctx->bind_vertex_elements_state = vc5_vertex_state_bind;
717
718 pctx->create_sampler_state = vc5_create_sampler_state;
719 pctx->delete_sampler_state = vc5_generic_cso_state_delete;
720 pctx->bind_sampler_states = vc5_sampler_states_bind;
721
722 pctx->create_sampler_view = vc5_create_sampler_view;
723 pctx->sampler_view_destroy = vc5_sampler_view_destroy;
724 pctx->set_sampler_views = vc5_set_sampler_views;
725
726 pctx->create_stream_output_target = vc5_create_stream_output_target;
727 pctx->stream_output_target_destroy = vc5_stream_output_target_destroy;
728 pctx->set_stream_output_targets = vc5_set_stream_output_targets;
729 }