2 * Copyright 2014, 2015 Red Hat.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_shader_tokens.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31 #include "util/u_inlines.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_prim.h"
35 #include "util/u_transfer.h"
36 #include "util/u_helpers.h"
37 #include "util/slab.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_blitter.h"
40 #include "tgsi/tgsi_text.h"
41 #include "indices/u_primconvert.h"
43 #include "pipebuffer/pb_buffer.h"
45 #include "virgl_encode.h"
46 #include "virgl_context.h"
47 #include "virgl_protocol.h"
48 #include "virgl_resource.h"
49 #include "virgl_screen.h"
51 struct virgl_vertex_elements_state
{
53 uint8_t binding_map
[PIPE_MAX_ATTRIBS
];
57 static uint32_t next_handle
;
58 uint32_t virgl_object_assign_handle(void)
64 virgl_can_rebind_resource(struct virgl_context
*vctx
,
65 struct pipe_resource
*res
)
67 /* We cannot rebind resources that are referenced by host objects, which
70 * - VIRGL_OBJECT_SURFACE
71 * - VIRGL_OBJECT_SAMPLER_VIEW
72 * - VIRGL_OBJECT_STREAMOUT_TARGET
74 * Because surfaces cannot be created from buffers, we require the resource
75 * to be a buffer instead (and avoid tracking VIRGL_OBJECT_SURFACE binds).
77 const unsigned unsupported_bind
= (PIPE_BIND_SAMPLER_VIEW
|
78 PIPE_BIND_STREAM_OUTPUT
);
79 const unsigned bind_history
= virgl_resource(res
)->bind_history
;
80 return res
->target
== PIPE_BUFFER
&& !(bind_history
& unsupported_bind
);
84 virgl_rebind_resource(struct virgl_context
*vctx
,
85 struct pipe_resource
*res
)
87 /* Queries use internally created buffers and do not go through transfers.
88 * Index buffers are not bindable. They are not tracked.
90 MAYBE_UNUSED
const unsigned tracked_bind
= (PIPE_BIND_VERTEX_BUFFER
|
91 PIPE_BIND_CONSTANT_BUFFER
|
92 PIPE_BIND_SHADER_BUFFER
|
93 PIPE_BIND_SHADER_IMAGE
);
94 const unsigned bind_history
= virgl_resource(res
)->bind_history
;
97 assert(virgl_can_rebind_resource(vctx
, res
) &&
98 (bind_history
& tracked_bind
) == bind_history
);
100 if (bind_history
& PIPE_BIND_VERTEX_BUFFER
) {
101 for (i
= 0; i
< vctx
->num_vertex_buffers
; i
++) {
102 if (vctx
->vertex_buffer
[i
].buffer
.resource
== res
) {
103 vctx
->vertex_array_dirty
= true;
109 if (bind_history
& PIPE_BIND_SHADER_BUFFER
) {
110 uint32_t remaining_mask
= vctx
->atomic_buffer_enabled_mask
;
111 while (remaining_mask
) {
112 int i
= u_bit_scan(&remaining_mask
);
113 if (vctx
->atomic_buffers
[i
].buffer
== res
) {
114 const struct pipe_shader_buffer
*abo
= &vctx
->atomic_buffers
[i
];
115 virgl_encode_set_hw_atomic_buffers(vctx
, i
, 1, abo
);
120 /* check per-stage shader bindings */
121 if (bind_history
& (PIPE_BIND_CONSTANT_BUFFER
|
122 PIPE_BIND_SHADER_BUFFER
|
123 PIPE_BIND_SHADER_IMAGE
)) {
124 enum pipe_shader_type shader_type
;
125 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
126 const struct virgl_shader_binding_state
*binding
=
127 &vctx
->shader_bindings
[shader_type
];
129 if (bind_history
& PIPE_BIND_CONSTANT_BUFFER
) {
130 uint32_t remaining_mask
= binding
->ubo_enabled_mask
;
131 while (remaining_mask
) {
132 int i
= u_bit_scan(&remaining_mask
);
133 if (binding
->ubos
[i
].buffer
== res
) {
134 const struct pipe_constant_buffer
*ubo
= &binding
->ubos
[i
];
135 virgl_encoder_set_uniform_buffer(vctx
, shader_type
, i
,
138 virgl_resource(res
));
143 if (bind_history
& PIPE_BIND_SHADER_BUFFER
) {
144 uint32_t remaining_mask
= binding
->ssbo_enabled_mask
;
145 while (remaining_mask
) {
146 int i
= u_bit_scan(&remaining_mask
);
147 if (binding
->ssbos
[i
].buffer
== res
) {
148 const struct pipe_shader_buffer
*ssbo
= &binding
->ssbos
[i
];
149 virgl_encode_set_shader_buffers(vctx
, shader_type
, i
, 1,
155 if (bind_history
& PIPE_BIND_SHADER_IMAGE
) {
156 uint32_t remaining_mask
= binding
->image_enabled_mask
;
157 while (remaining_mask
) {
158 int i
= u_bit_scan(&remaining_mask
);
159 if (binding
->images
[i
].resource
== res
) {
160 const struct pipe_image_view
*image
= &binding
->images
[i
];
161 virgl_encode_set_shader_images(vctx
, shader_type
, i
, 1,
170 static void virgl_attach_res_framebuffer(struct virgl_context
*vctx
)
172 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
173 struct pipe_surface
*surf
;
174 struct virgl_resource
*res
;
177 surf
= vctx
->framebuffer
.zsbuf
;
179 res
= virgl_resource(surf
->texture
);
181 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
182 virgl_resource_dirty(res
, surf
->u
.tex
.level
);
185 for (i
= 0; i
< vctx
->framebuffer
.nr_cbufs
; i
++) {
186 surf
= vctx
->framebuffer
.cbufs
[i
];
188 res
= virgl_resource(surf
->texture
);
190 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
191 virgl_resource_dirty(res
, surf
->u
.tex
.level
);
197 static void virgl_attach_res_sampler_views(struct virgl_context
*vctx
,
198 enum pipe_shader_type shader_type
)
200 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
201 const struct virgl_shader_binding_state
*binding
=
202 &vctx
->shader_bindings
[shader_type
];
203 uint32_t remaining_mask
= binding
->view_enabled_mask
;
204 struct virgl_resource
*res
;
206 while (remaining_mask
) {
207 int i
= u_bit_scan(&remaining_mask
);
208 assert(binding
->views
[i
] && binding
->views
[i
]->texture
);
209 res
= virgl_resource(binding
->views
[i
]->texture
);
210 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
214 static void virgl_attach_res_vertex_buffers(struct virgl_context
*vctx
)
216 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
217 struct virgl_resource
*res
;
220 for (i
= 0; i
< vctx
->num_vertex_buffers
; i
++) {
221 res
= virgl_resource(vctx
->vertex_buffer
[i
].buffer
.resource
);
223 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
227 static void virgl_attach_res_index_buffer(struct virgl_context
*vctx
,
228 struct virgl_indexbuf
*ib
)
230 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
231 struct virgl_resource
*res
;
233 res
= virgl_resource(ib
->buffer
);
235 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
238 static void virgl_attach_res_so_targets(struct virgl_context
*vctx
)
240 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
241 struct virgl_resource
*res
;
244 for (i
= 0; i
< vctx
->num_so_targets
; i
++) {
245 res
= virgl_resource(vctx
->so_targets
[i
].base
.buffer
);
247 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
251 static void virgl_attach_res_uniform_buffers(struct virgl_context
*vctx
,
252 enum pipe_shader_type shader_type
)
254 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
255 const struct virgl_shader_binding_state
*binding
=
256 &vctx
->shader_bindings
[shader_type
];
257 uint32_t remaining_mask
= binding
->ubo_enabled_mask
;
258 struct virgl_resource
*res
;
260 while (remaining_mask
) {
261 int i
= u_bit_scan(&remaining_mask
);
262 res
= virgl_resource(binding
->ubos
[i
].buffer
);
264 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
268 static void virgl_attach_res_shader_buffers(struct virgl_context
*vctx
,
269 enum pipe_shader_type shader_type
)
271 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
272 const struct virgl_shader_binding_state
*binding
=
273 &vctx
->shader_bindings
[shader_type
];
274 uint32_t remaining_mask
= binding
->ssbo_enabled_mask
;
275 struct virgl_resource
*res
;
277 while (remaining_mask
) {
278 int i
= u_bit_scan(&remaining_mask
);
279 res
= virgl_resource(binding
->ssbos
[i
].buffer
);
281 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
285 static void virgl_attach_res_shader_images(struct virgl_context
*vctx
,
286 enum pipe_shader_type shader_type
)
288 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
289 const struct virgl_shader_binding_state
*binding
=
290 &vctx
->shader_bindings
[shader_type
];
291 uint32_t remaining_mask
= binding
->image_enabled_mask
;
292 struct virgl_resource
*res
;
294 while (remaining_mask
) {
295 int i
= u_bit_scan(&remaining_mask
);
296 res
= virgl_resource(binding
->images
[i
].resource
);
298 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
302 static void virgl_attach_res_atomic_buffers(struct virgl_context
*vctx
)
304 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
305 uint32_t remaining_mask
= vctx
->atomic_buffer_enabled_mask
;
306 struct virgl_resource
*res
;
308 while (remaining_mask
) {
309 int i
= u_bit_scan(&remaining_mask
);
310 res
= virgl_resource(vctx
->atomic_buffers
[i
].buffer
);
312 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
317 * after flushing, the hw context still has a bunch of
318 * resources bound, so we need to rebind those here.
320 static void virgl_reemit_draw_resources(struct virgl_context
*vctx
)
322 enum pipe_shader_type shader_type
;
324 /* reattach any flushed resources */
325 /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
326 virgl_attach_res_framebuffer(vctx
);
328 for (shader_type
= 0; shader_type
< PIPE_SHADER_COMPUTE
; shader_type
++) {
329 virgl_attach_res_sampler_views(vctx
, shader_type
);
330 virgl_attach_res_uniform_buffers(vctx
, shader_type
);
331 virgl_attach_res_shader_buffers(vctx
, shader_type
);
332 virgl_attach_res_shader_images(vctx
, shader_type
);
334 virgl_attach_res_atomic_buffers(vctx
);
335 virgl_attach_res_vertex_buffers(vctx
);
336 virgl_attach_res_so_targets(vctx
);
339 static void virgl_reemit_compute_resources(struct virgl_context
*vctx
)
341 virgl_attach_res_sampler_views(vctx
, PIPE_SHADER_COMPUTE
);
342 virgl_attach_res_uniform_buffers(vctx
, PIPE_SHADER_COMPUTE
);
343 virgl_attach_res_shader_buffers(vctx
, PIPE_SHADER_COMPUTE
);
344 virgl_attach_res_shader_images(vctx
, PIPE_SHADER_COMPUTE
);
346 virgl_attach_res_atomic_buffers(vctx
);
349 static struct pipe_surface
*virgl_create_surface(struct pipe_context
*ctx
,
350 struct pipe_resource
*resource
,
351 const struct pipe_surface
*templ
)
353 struct virgl_context
*vctx
= virgl_context(ctx
);
354 struct virgl_surface
*surf
;
355 struct virgl_resource
*res
= virgl_resource(resource
);
358 /* no support for buffer surfaces */
359 if (resource
->target
== PIPE_BUFFER
)
362 surf
= CALLOC_STRUCT(virgl_surface
);
366 assert(ctx
->screen
->get_param(ctx
->screen
,
367 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL
) ||
368 (util_format_is_srgb(templ
->format
) ==
369 util_format_is_srgb(resource
->format
)));
371 virgl_resource_dirty(res
, 0);
372 handle
= virgl_object_assign_handle();
373 pipe_reference_init(&surf
->base
.reference
, 1);
374 pipe_resource_reference(&surf
->base
.texture
, resource
);
375 surf
->base
.context
= ctx
;
376 surf
->base
.format
= templ
->format
;
378 surf
->base
.width
= u_minify(resource
->width0
, templ
->u
.tex
.level
);
379 surf
->base
.height
= u_minify(resource
->height0
, templ
->u
.tex
.level
);
380 surf
->base
.u
.tex
.level
= templ
->u
.tex
.level
;
381 surf
->base
.u
.tex
.first_layer
= templ
->u
.tex
.first_layer
;
382 surf
->base
.u
.tex
.last_layer
= templ
->u
.tex
.last_layer
;
384 virgl_encoder_create_surface(vctx
, handle
, res
, &surf
->base
);
385 surf
->handle
= handle
;
389 static void virgl_surface_destroy(struct pipe_context
*ctx
,
390 struct pipe_surface
*psurf
)
392 struct virgl_context
*vctx
= virgl_context(ctx
);
393 struct virgl_surface
*surf
= virgl_surface(psurf
);
395 pipe_resource_reference(&surf
->base
.texture
, NULL
);
396 virgl_encode_delete_object(vctx
, surf
->handle
, VIRGL_OBJECT_SURFACE
);
400 static void *virgl_create_blend_state(struct pipe_context
*ctx
,
401 const struct pipe_blend_state
*blend_state
)
403 struct virgl_context
*vctx
= virgl_context(ctx
);
405 handle
= virgl_object_assign_handle();
407 virgl_encode_blend_state(vctx
, handle
, blend_state
);
408 return (void *)(unsigned long)handle
;
412 static void virgl_bind_blend_state(struct pipe_context
*ctx
,
415 struct virgl_context
*vctx
= virgl_context(ctx
);
416 uint32_t handle
= (unsigned long)blend_state
;
417 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
420 static void virgl_delete_blend_state(struct pipe_context
*ctx
,
423 struct virgl_context
*vctx
= virgl_context(ctx
);
424 uint32_t handle
= (unsigned long)blend_state
;
425 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
428 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context
*ctx
,
429 const struct pipe_depth_stencil_alpha_state
*blend_state
)
431 struct virgl_context
*vctx
= virgl_context(ctx
);
433 handle
= virgl_object_assign_handle();
435 virgl_encode_dsa_state(vctx
, handle
, blend_state
);
436 return (void *)(unsigned long)handle
;
439 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context
*ctx
,
442 struct virgl_context
*vctx
= virgl_context(ctx
);
443 uint32_t handle
= (unsigned long)blend_state
;
444 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
447 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context
*ctx
,
450 struct virgl_context
*vctx
= virgl_context(ctx
);
451 uint32_t handle
= (unsigned long)dsa_state
;
452 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
455 static void *virgl_create_rasterizer_state(struct pipe_context
*ctx
,
456 const struct pipe_rasterizer_state
*rs_state
)
458 struct virgl_context
*vctx
= virgl_context(ctx
);
459 struct virgl_rasterizer_state
*vrs
= CALLOC_STRUCT(virgl_rasterizer_state
);
464 vrs
->handle
= virgl_object_assign_handle();
466 virgl_encode_rasterizer_state(vctx
, vrs
->handle
, rs_state
);
470 static void virgl_bind_rasterizer_state(struct pipe_context
*ctx
,
473 struct virgl_context
*vctx
= virgl_context(ctx
);
476 struct virgl_rasterizer_state
*vrs
= rs_state
;
477 vctx
->rs_state
= *vrs
;
478 handle
= vrs
->handle
;
480 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
483 static void virgl_delete_rasterizer_state(struct pipe_context
*ctx
,
486 struct virgl_context
*vctx
= virgl_context(ctx
);
487 struct virgl_rasterizer_state
*vrs
= rs_state
;
488 virgl_encode_delete_object(vctx
, vrs
->handle
, VIRGL_OBJECT_RASTERIZER
);
492 static void virgl_set_framebuffer_state(struct pipe_context
*ctx
,
493 const struct pipe_framebuffer_state
*state
)
495 struct virgl_context
*vctx
= virgl_context(ctx
);
497 vctx
->framebuffer
= *state
;
498 virgl_encoder_set_framebuffer_state(vctx
, state
);
499 virgl_attach_res_framebuffer(vctx
);
502 static void virgl_set_viewport_states(struct pipe_context
*ctx
,
504 unsigned num_viewports
,
505 const struct pipe_viewport_state
*state
)
507 struct virgl_context
*vctx
= virgl_context(ctx
);
508 virgl_encoder_set_viewport_states(vctx
, start_slot
, num_viewports
, state
);
511 static void *virgl_create_vertex_elements_state(struct pipe_context
*ctx
,
512 unsigned num_elements
,
513 const struct pipe_vertex_element
*elements
)
515 struct pipe_vertex_element new_elements
[PIPE_MAX_ATTRIBS
];
516 struct virgl_context
*vctx
= virgl_context(ctx
);
517 struct virgl_vertex_elements_state
*state
=
518 CALLOC_STRUCT(virgl_vertex_elements_state
);
520 for (int i
= 0; i
< num_elements
; ++i
) {
521 if (elements
[i
].instance_divisor
) {
522 /* Virglrenderer doesn't deal with instance_divisor correctly if
523 * there isn't a 1:1 relationship between elements and bindings.
524 * So let's make sure there is, by duplicating bindings.
526 for (int j
= 0; j
< num_elements
; ++j
) {
527 new_elements
[j
] = elements
[j
];
528 new_elements
[j
].vertex_buffer_index
= j
;
529 state
->binding_map
[j
] = elements
[j
].vertex_buffer_index
;
531 elements
= new_elements
;
532 state
->num_bindings
= num_elements
;
537 state
->handle
= virgl_object_assign_handle();
538 virgl_encoder_create_vertex_elements(vctx
, state
->handle
,
539 num_elements
, elements
);
543 static void virgl_delete_vertex_elements_state(struct pipe_context
*ctx
,
546 struct virgl_context
*vctx
= virgl_context(ctx
);
547 struct virgl_vertex_elements_state
*state
=
548 (struct virgl_vertex_elements_state
*)ve
;
549 virgl_encode_delete_object(vctx
, state
->handle
, VIRGL_OBJECT_VERTEX_ELEMENTS
);
553 static void virgl_bind_vertex_elements_state(struct pipe_context
*ctx
,
556 struct virgl_context
*vctx
= virgl_context(ctx
);
557 struct virgl_vertex_elements_state
*state
=
558 (struct virgl_vertex_elements_state
*)ve
;
559 vctx
->vertex_elements
= state
;
560 virgl_encode_bind_object(vctx
, state
? state
->handle
: 0,
561 VIRGL_OBJECT_VERTEX_ELEMENTS
);
562 vctx
->vertex_array_dirty
= TRUE
;
565 static void virgl_set_vertex_buffers(struct pipe_context
*ctx
,
567 unsigned num_buffers
,
568 const struct pipe_vertex_buffer
*buffers
)
570 struct virgl_context
*vctx
= virgl_context(ctx
);
572 util_set_vertex_buffers_count(vctx
->vertex_buffer
,
573 &vctx
->num_vertex_buffers
,
574 buffers
, start_slot
, num_buffers
);
577 for (unsigned i
= 0; i
< num_buffers
; i
++) {
578 struct virgl_resource
*res
=
579 virgl_resource(buffers
[i
].buffer
.resource
);
580 if (res
&& !buffers
[i
].is_user_buffer
)
581 res
->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
585 vctx
->vertex_array_dirty
= TRUE
;
588 static void virgl_hw_set_vertex_buffers(struct virgl_context
*vctx
)
590 if (vctx
->vertex_array_dirty
) {
591 struct virgl_vertex_elements_state
*ve
= vctx
->vertex_elements
;
593 if (ve
->num_bindings
) {
594 struct pipe_vertex_buffer vertex_buffers
[PIPE_MAX_ATTRIBS
];
595 for (int i
= 0; i
< ve
->num_bindings
; ++i
)
596 vertex_buffers
[i
] = vctx
->vertex_buffer
[ve
->binding_map
[i
]];
598 virgl_encoder_set_vertex_buffers(vctx
, ve
->num_bindings
, vertex_buffers
);
600 virgl_encoder_set_vertex_buffers(vctx
, vctx
->num_vertex_buffers
, vctx
->vertex_buffer
);
602 virgl_attach_res_vertex_buffers(vctx
);
604 vctx
->vertex_array_dirty
= FALSE
;
608 static void virgl_set_stencil_ref(struct pipe_context
*ctx
,
609 const struct pipe_stencil_ref
*ref
)
611 struct virgl_context
*vctx
= virgl_context(ctx
);
612 virgl_encoder_set_stencil_ref(vctx
, ref
);
615 static void virgl_set_blend_color(struct pipe_context
*ctx
,
616 const struct pipe_blend_color
*color
)
618 struct virgl_context
*vctx
= virgl_context(ctx
);
619 virgl_encoder_set_blend_color(vctx
, color
);
622 static void virgl_hw_set_index_buffer(struct virgl_context
*vctx
,
623 struct virgl_indexbuf
*ib
)
625 virgl_encoder_set_index_buffer(vctx
, ib
);
626 virgl_attach_res_index_buffer(vctx
, ib
);
629 static void virgl_set_constant_buffer(struct pipe_context
*ctx
,
630 enum pipe_shader_type shader
, uint index
,
631 const struct pipe_constant_buffer
*buf
)
633 struct virgl_context
*vctx
= virgl_context(ctx
);
634 struct virgl_shader_binding_state
*binding
=
635 &vctx
->shader_bindings
[shader
];
637 if (buf
&& buf
->buffer
) {
638 struct virgl_resource
*res
= virgl_resource(buf
->buffer
);
639 res
->bind_history
|= PIPE_BIND_CONSTANT_BUFFER
;
641 virgl_encoder_set_uniform_buffer(vctx
, shader
, index
,
643 buf
->buffer_size
, res
);
645 pipe_resource_reference(&binding
->ubos
[index
].buffer
, buf
->buffer
);
646 binding
->ubos
[index
] = *buf
;
647 binding
->ubo_enabled_mask
|= 1 << index
;
649 static const struct pipe_constant_buffer dummy_ubo
;
652 virgl_encoder_write_constant_buffer(vctx
, shader
, index
,
653 buf
->buffer_size
/ 4,
656 pipe_resource_reference(&binding
->ubos
[index
].buffer
, NULL
);
657 binding
->ubo_enabled_mask
&= ~(1 << index
);
661 static void *virgl_shader_encoder(struct pipe_context
*ctx
,
662 const struct pipe_shader_state
*shader
,
665 struct virgl_context
*vctx
= virgl_context(ctx
);
667 struct tgsi_token
*new_tokens
;
670 new_tokens
= virgl_tgsi_transform(vctx
, shader
->tokens
);
674 handle
= virgl_object_assign_handle();
675 /* encode VS state */
676 ret
= virgl_encode_shader_state(vctx
, handle
, type
,
677 &shader
->stream_output
, 0,
684 return (void *)(unsigned long)handle
;
687 static void *virgl_create_vs_state(struct pipe_context
*ctx
,
688 const struct pipe_shader_state
*shader
)
690 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_VERTEX
);
693 static void *virgl_create_tcs_state(struct pipe_context
*ctx
,
694 const struct pipe_shader_state
*shader
)
696 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_CTRL
);
699 static void *virgl_create_tes_state(struct pipe_context
*ctx
,
700 const struct pipe_shader_state
*shader
)
702 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_EVAL
);
705 static void *virgl_create_gs_state(struct pipe_context
*ctx
,
706 const struct pipe_shader_state
*shader
)
708 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_GEOMETRY
);
711 static void *virgl_create_fs_state(struct pipe_context
*ctx
,
712 const struct pipe_shader_state
*shader
)
714 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_FRAGMENT
);
718 virgl_delete_fs_state(struct pipe_context
*ctx
,
721 uint32_t handle
= (unsigned long)fs
;
722 struct virgl_context
*vctx
= virgl_context(ctx
);
724 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
728 virgl_delete_gs_state(struct pipe_context
*ctx
,
731 uint32_t handle
= (unsigned long)gs
;
732 struct virgl_context
*vctx
= virgl_context(ctx
);
734 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
738 virgl_delete_vs_state(struct pipe_context
*ctx
,
741 uint32_t handle
= (unsigned long)vs
;
742 struct virgl_context
*vctx
= virgl_context(ctx
);
744 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
748 virgl_delete_tcs_state(struct pipe_context
*ctx
,
751 uint32_t handle
= (unsigned long)tcs
;
752 struct virgl_context
*vctx
= virgl_context(ctx
);
754 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
758 virgl_delete_tes_state(struct pipe_context
*ctx
,
761 uint32_t handle
= (unsigned long)tes
;
762 struct virgl_context
*vctx
= virgl_context(ctx
);
764 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
767 static void virgl_bind_vs_state(struct pipe_context
*ctx
,
770 uint32_t handle
= (unsigned long)vss
;
771 struct virgl_context
*vctx
= virgl_context(ctx
);
773 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_VERTEX
);
776 static void virgl_bind_tcs_state(struct pipe_context
*ctx
,
779 uint32_t handle
= (unsigned long)vss
;
780 struct virgl_context
*vctx
= virgl_context(ctx
);
782 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_CTRL
);
785 static void virgl_bind_tes_state(struct pipe_context
*ctx
,
788 uint32_t handle
= (unsigned long)vss
;
789 struct virgl_context
*vctx
= virgl_context(ctx
);
791 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_EVAL
);
794 static void virgl_bind_gs_state(struct pipe_context
*ctx
,
797 uint32_t handle
= (unsigned long)vss
;
798 struct virgl_context
*vctx
= virgl_context(ctx
);
800 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_GEOMETRY
);
804 static void virgl_bind_fs_state(struct pipe_context
*ctx
,
807 uint32_t handle
= (unsigned long)vss
;
808 struct virgl_context
*vctx
= virgl_context(ctx
);
810 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_FRAGMENT
);
813 static void virgl_clear(struct pipe_context
*ctx
,
815 const union pipe_color_union
*color
,
816 double depth
, unsigned stencil
)
818 struct virgl_context
*vctx
= virgl_context(ctx
);
820 if (!vctx
->num_draws
)
821 virgl_reemit_draw_resources(vctx
);
824 virgl_encode_clear(vctx
, buffers
, color
, depth
, stencil
);
827 static void virgl_draw_vbo(struct pipe_context
*ctx
,
828 const struct pipe_draw_info
*dinfo
)
830 struct virgl_context
*vctx
= virgl_context(ctx
);
831 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
832 struct virgl_indexbuf ib
= {};
833 struct pipe_draw_info info
= *dinfo
;
835 if (!dinfo
->count_from_stream_output
&& !dinfo
->indirect
&&
836 !dinfo
->primitive_restart
&&
837 !u_trim_pipe_prim(dinfo
->mode
, (unsigned*)&dinfo
->count
))
840 if (!(rs
->caps
.caps
.v1
.prim_mask
& (1 << dinfo
->mode
))) {
841 util_primconvert_save_rasterizer_state(vctx
->primconvert
, &vctx
->rs_state
.rs
);
842 util_primconvert_draw_vbo(vctx
->primconvert
, dinfo
);
845 if (info
.index_size
) {
846 pipe_resource_reference(&ib
.buffer
, info
.has_user_indices
? NULL
: info
.index
.resource
);
847 ib
.user_buffer
= info
.has_user_indices
? info
.index
.user
: NULL
;
848 ib
.index_size
= dinfo
->index_size
;
849 ib
.offset
= info
.start
* ib
.index_size
;
851 if (ib
.user_buffer
) {
852 u_upload_data(vctx
->uploader
, 0, info
.count
* ib
.index_size
, 4,
853 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
854 ib
.user_buffer
= NULL
;
858 if (!vctx
->num_draws
)
859 virgl_reemit_draw_resources(vctx
);
862 virgl_hw_set_vertex_buffers(vctx
);
864 virgl_hw_set_index_buffer(vctx
, &ib
);
866 virgl_encoder_draw_vbo(vctx
, &info
);
868 pipe_resource_reference(&ib
.buffer
, NULL
);
872 static void virgl_flush_eq(struct virgl_context
*ctx
, void *closure
,
873 struct pipe_fence_handle
**fence
)
875 struct virgl_screen
*rs
= virgl_screen(ctx
->base
.screen
);
877 /* skip empty cbuf */
878 if (ctx
->cbuf
->cdw
== ctx
->cbuf_initial_cdw
&&
879 ctx
->queue
.num_dwords
== 0 &&
884 u_upload_unmap(ctx
->uploader
);
886 /* send the buffer to the remote side for decoding */
887 ctx
->num_draws
= ctx
->num_compute
= 0;
889 virgl_transfer_queue_clear(&ctx
->queue
, ctx
->cbuf
);
890 rs
->vws
->submit_cmd(rs
->vws
, ctx
->cbuf
, fence
);
892 /* Reserve some space for transfers. */
893 if (ctx
->encoded_transfers
)
894 ctx
->cbuf
->cdw
= VIRGL_MAX_TBUF_DWORDS
;
896 virgl_encoder_set_sub_ctx(ctx
, ctx
->hw_sub_ctx_id
);
898 ctx
->cbuf_initial_cdw
= ctx
->cbuf
->cdw
;
900 /* We have flushed the command queue, including any pending copy transfers
901 * involving staging resources.
903 ctx
->queued_staging_res_size
= 0;
906 static void virgl_flush_from_st(struct pipe_context
*ctx
,
907 struct pipe_fence_handle
**fence
,
908 enum pipe_flush_flags flags
)
910 struct virgl_context
*vctx
= virgl_context(ctx
);
912 virgl_flush_eq(vctx
, vctx
, fence
);
915 static struct pipe_sampler_view
*virgl_create_sampler_view(struct pipe_context
*ctx
,
916 struct pipe_resource
*texture
,
917 const struct pipe_sampler_view
*state
)
919 struct virgl_context
*vctx
= virgl_context(ctx
);
920 struct virgl_sampler_view
*grview
;
922 struct virgl_resource
*res
;
927 grview
= CALLOC_STRUCT(virgl_sampler_view
);
931 res
= virgl_resource(texture
);
932 handle
= virgl_object_assign_handle();
933 virgl_encode_sampler_view(vctx
, handle
, res
, state
);
935 grview
->base
= *state
;
936 grview
->base
.reference
.count
= 1;
938 grview
->base
.texture
= NULL
;
939 grview
->base
.context
= ctx
;
940 pipe_resource_reference(&grview
->base
.texture
, texture
);
941 grview
->handle
= handle
;
942 return &grview
->base
;
945 static void virgl_set_sampler_views(struct pipe_context
*ctx
,
946 enum pipe_shader_type shader_type
,
949 struct pipe_sampler_view
**views
)
951 struct virgl_context
*vctx
= virgl_context(ctx
);
952 struct virgl_shader_binding_state
*binding
=
953 &vctx
->shader_bindings
[shader_type
];
955 binding
->view_enabled_mask
&= ~u_bit_consecutive(start_slot
, num_views
);
956 for (unsigned i
= 0; i
< num_views
; i
++) {
957 unsigned idx
= start_slot
+ i
;
958 if (views
&& views
[i
]) {
959 struct virgl_resource
*res
= virgl_resource(views
[i
]->texture
);
960 res
->bind_history
|= PIPE_BIND_SAMPLER_VIEW
;
962 pipe_sampler_view_reference(&binding
->views
[idx
], views
[i
]);
963 binding
->view_enabled_mask
|= 1 << idx
;
965 pipe_sampler_view_reference(&binding
->views
[idx
], NULL
);
969 virgl_encode_set_sampler_views(vctx
, shader_type
,
970 start_slot
, num_views
, (struct virgl_sampler_view
**)binding
->views
);
971 virgl_attach_res_sampler_views(vctx
, shader_type
);
975 virgl_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
977 struct virgl_context
*vctx
= virgl_context(ctx
);
978 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
980 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_BARRIER
))
982 virgl_encode_texture_barrier(vctx
, flags
);
985 static void virgl_destroy_sampler_view(struct pipe_context
*ctx
,
986 struct pipe_sampler_view
*view
)
988 struct virgl_context
*vctx
= virgl_context(ctx
);
989 struct virgl_sampler_view
*grview
= virgl_sampler_view(view
);
991 virgl_encode_delete_object(vctx
, grview
->handle
, VIRGL_OBJECT_SAMPLER_VIEW
);
992 pipe_resource_reference(&view
->texture
, NULL
);
996 static void *virgl_create_sampler_state(struct pipe_context
*ctx
,
997 const struct pipe_sampler_state
*state
)
999 struct virgl_context
*vctx
= virgl_context(ctx
);
1002 handle
= virgl_object_assign_handle();
1004 virgl_encode_sampler_state(vctx
, handle
, state
);
1005 return (void *)(unsigned long)handle
;
1008 static void virgl_delete_sampler_state(struct pipe_context
*ctx
,
1011 struct virgl_context
*vctx
= virgl_context(ctx
);
1012 uint32_t handle
= (unsigned long)ss
;
1014 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SAMPLER_STATE
);
1017 static void virgl_bind_sampler_states(struct pipe_context
*ctx
,
1018 enum pipe_shader_type shader
,
1019 unsigned start_slot
,
1020 unsigned num_samplers
,
1023 struct virgl_context
*vctx
= virgl_context(ctx
);
1024 uint32_t handles
[32];
1026 for (i
= 0; i
< num_samplers
; i
++) {
1027 handles
[i
] = (unsigned long)(samplers
[i
]);
1029 virgl_encode_bind_sampler_states(vctx
, shader
, start_slot
, num_samplers
, handles
);
1032 static void virgl_set_polygon_stipple(struct pipe_context
*ctx
,
1033 const struct pipe_poly_stipple
*ps
)
1035 struct virgl_context
*vctx
= virgl_context(ctx
);
1036 virgl_encoder_set_polygon_stipple(vctx
, ps
);
1039 static void virgl_set_scissor_states(struct pipe_context
*ctx
,
1040 unsigned start_slot
,
1041 unsigned num_scissor
,
1042 const struct pipe_scissor_state
*ss
)
1044 struct virgl_context
*vctx
= virgl_context(ctx
);
1045 virgl_encoder_set_scissor_state(vctx
, start_slot
, num_scissor
, ss
);
1048 static void virgl_set_sample_mask(struct pipe_context
*ctx
,
1049 unsigned sample_mask
)
1051 struct virgl_context
*vctx
= virgl_context(ctx
);
1052 virgl_encoder_set_sample_mask(vctx
, sample_mask
);
1055 static void virgl_set_min_samples(struct pipe_context
*ctx
,
1056 unsigned min_samples
)
1058 struct virgl_context
*vctx
= virgl_context(ctx
);
1059 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1061 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SET_MIN_SAMPLES
))
1063 virgl_encoder_set_min_samples(vctx
, min_samples
);
1066 static void virgl_set_clip_state(struct pipe_context
*ctx
,
1067 const struct pipe_clip_state
*clip
)
1069 struct virgl_context
*vctx
= virgl_context(ctx
);
1070 virgl_encoder_set_clip_state(vctx
, clip
);
1073 static void virgl_set_tess_state(struct pipe_context
*ctx
,
1074 const float default_outer_level
[4],
1075 const float default_inner_level
[2])
1077 struct virgl_context
*vctx
= virgl_context(ctx
);
1078 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1080 if (!rs
->caps
.caps
.v1
.bset
.has_tessellation_shaders
)
1082 virgl_encode_set_tess_state(vctx
, default_outer_level
, default_inner_level
);
1085 static void virgl_resource_copy_region(struct pipe_context
*ctx
,
1086 struct pipe_resource
*dst
,
1088 unsigned dstx
, unsigned dsty
, unsigned dstz
,
1089 struct pipe_resource
*src
,
1091 const struct pipe_box
*src_box
)
1093 struct virgl_context
*vctx
= virgl_context(ctx
);
1094 struct virgl_resource
*dres
= virgl_resource(dst
);
1095 struct virgl_resource
*sres
= virgl_resource(src
);
1097 if (dres
->u
.b
.target
== PIPE_BUFFER
)
1098 util_range_add(&dres
->valid_buffer_range
, dstx
, dstx
+ src_box
->width
);
1099 virgl_resource_dirty(dres
, dst_level
);
1101 virgl_encode_resource_copy_region(vctx
, dres
,
1102 dst_level
, dstx
, dsty
, dstz
,
1108 virgl_flush_resource(struct pipe_context
*pipe
,
1109 struct pipe_resource
*resource
)
1113 static void virgl_blit(struct pipe_context
*ctx
,
1114 const struct pipe_blit_info
*blit
)
1116 struct virgl_context
*vctx
= virgl_context(ctx
);
1117 struct virgl_resource
*dres
= virgl_resource(blit
->dst
.resource
);
1118 struct virgl_resource
*sres
= virgl_resource(blit
->src
.resource
);
1120 assert(ctx
->screen
->get_param(ctx
->screen
,
1121 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL
) ||
1122 (util_format_is_srgb(blit
->dst
.resource
->format
) ==
1123 util_format_is_srgb(blit
->dst
.format
)));
1125 virgl_resource_dirty(dres
, blit
->dst
.level
);
1126 virgl_encode_blit(vctx
, dres
, sres
,
1130 static void virgl_set_hw_atomic_buffers(struct pipe_context
*ctx
,
1131 unsigned start_slot
,
1133 const struct pipe_shader_buffer
*buffers
)
1135 struct virgl_context
*vctx
= virgl_context(ctx
);
1137 vctx
->atomic_buffer_enabled_mask
&= ~u_bit_consecutive(start_slot
, count
);
1138 for (unsigned i
= 0; i
< count
; i
++) {
1139 unsigned idx
= start_slot
+ i
;
1140 if (buffers
&& buffers
[i
].buffer
) {
1141 struct virgl_resource
*res
= virgl_resource(buffers
[i
].buffer
);
1142 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1144 pipe_resource_reference(&vctx
->atomic_buffers
[idx
].buffer
,
1146 vctx
->atomic_buffers
[idx
] = buffers
[i
];
1147 vctx
->atomic_buffer_enabled_mask
|= 1 << idx
;
1149 pipe_resource_reference(&vctx
->atomic_buffers
[idx
].buffer
, NULL
);
1153 virgl_encode_set_hw_atomic_buffers(vctx
, start_slot
, count
, buffers
);
1156 static void virgl_set_shader_buffers(struct pipe_context
*ctx
,
1157 enum pipe_shader_type shader
,
1158 unsigned start_slot
, unsigned count
,
1159 const struct pipe_shader_buffer
*buffers
,
1160 unsigned writable_bitmask
)
1162 struct virgl_context
*vctx
= virgl_context(ctx
);
1163 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1164 struct virgl_shader_binding_state
*binding
=
1165 &vctx
->shader_bindings
[shader
];
1167 binding
->ssbo_enabled_mask
&= ~u_bit_consecutive(start_slot
, count
);
1168 for (unsigned i
= 0; i
< count
; i
++) {
1169 unsigned idx
= start_slot
+ i
;
1170 if (buffers
&& buffers
[i
].buffer
) {
1171 struct virgl_resource
*res
= virgl_resource(buffers
[i
].buffer
);
1172 res
->bind_history
|= PIPE_BIND_SHADER_BUFFER
;
1174 pipe_resource_reference(&binding
->ssbos
[idx
].buffer
, buffers
[i
].buffer
);
1175 binding
->ssbos
[idx
] = buffers
[i
];
1176 binding
->ssbo_enabled_mask
|= 1 << idx
;
1178 pipe_resource_reference(&binding
->ssbos
[idx
].buffer
, NULL
);
1182 uint32_t max_shader_buffer
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1183 rs
->caps
.caps
.v2
.max_shader_buffer_frag_compute
:
1184 rs
->caps
.caps
.v2
.max_shader_buffer_other_stages
;
1185 if (!max_shader_buffer
)
1187 virgl_encode_set_shader_buffers(vctx
, shader
, start_slot
, count
, buffers
);
1190 static void virgl_create_fence_fd(struct pipe_context
*ctx
,
1191 struct pipe_fence_handle
**fence
,
1193 enum pipe_fd_type type
)
1195 assert(type
== PIPE_FD_TYPE_NATIVE_SYNC
);
1196 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1198 if (rs
->vws
->cs_create_fence
)
1199 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, fd
);
1202 static void virgl_fence_server_sync(struct pipe_context
*ctx
,
1203 struct pipe_fence_handle
*fence
)
1205 struct virgl_context
*vctx
= virgl_context(ctx
);
1206 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1208 if (rs
->vws
->fence_server_sync
)
1209 rs
->vws
->fence_server_sync(rs
->vws
, vctx
->cbuf
, fence
);
1212 static void virgl_set_shader_images(struct pipe_context
*ctx
,
1213 enum pipe_shader_type shader
,
1214 unsigned start_slot
, unsigned count
,
1215 const struct pipe_image_view
*images
)
1217 struct virgl_context
*vctx
= virgl_context(ctx
);
1218 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1219 struct virgl_shader_binding_state
*binding
=
1220 &vctx
->shader_bindings
[shader
];
1222 binding
->image_enabled_mask
&= ~u_bit_consecutive(start_slot
, count
);
1223 for (unsigned i
= 0; i
< count
; i
++) {
1224 unsigned idx
= start_slot
+ i
;
1225 if (images
&& images
[i
].resource
) {
1226 struct virgl_resource
*res
= virgl_resource(images
[i
].resource
);
1227 res
->bind_history
|= PIPE_BIND_SHADER_IMAGE
;
1229 pipe_resource_reference(&binding
->images
[idx
].resource
,
1230 images
[i
].resource
);
1231 binding
->images
[idx
] = images
[i
];
1232 binding
->image_enabled_mask
|= 1 << idx
;
1234 pipe_resource_reference(&binding
->images
[idx
].resource
, NULL
);
1238 uint32_t max_shader_images
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1239 rs
->caps
.caps
.v2
.max_shader_image_frag_compute
:
1240 rs
->caps
.caps
.v2
.max_shader_image_other_stages
;
1241 if (!max_shader_images
)
1243 virgl_encode_set_shader_images(vctx
, shader
, start_slot
, count
, images
);
1246 static void virgl_memory_barrier(struct pipe_context
*ctx
,
1249 struct virgl_context
*vctx
= virgl_context(ctx
);
1250 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1252 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_MEMORY_BARRIER
))
1254 virgl_encode_memory_barrier(vctx
, flags
);
1257 static void *virgl_create_compute_state(struct pipe_context
*ctx
,
1258 const struct pipe_compute_state
*state
)
1260 struct virgl_context
*vctx
= virgl_context(ctx
);
1262 const struct tgsi_token
*new_tokens
= state
->prog
;
1263 struct pipe_stream_output_info so_info
= {};
1266 handle
= virgl_object_assign_handle();
1267 ret
= virgl_encode_shader_state(vctx
, handle
, PIPE_SHADER_COMPUTE
,
1269 state
->req_local_mem
,
1275 return (void *)(unsigned long)handle
;
1278 static void virgl_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1280 uint32_t handle
= (unsigned long)state
;
1281 struct virgl_context
*vctx
= virgl_context(ctx
);
1283 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_COMPUTE
);
1286 static void virgl_delete_compute_state(struct pipe_context
*ctx
, void *state
)
1288 uint32_t handle
= (unsigned long)state
;
1289 struct virgl_context
*vctx
= virgl_context(ctx
);
1291 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
1294 static void virgl_launch_grid(struct pipe_context
*ctx
,
1295 const struct pipe_grid_info
*info
)
1297 struct virgl_context
*vctx
= virgl_context(ctx
);
1299 if (!vctx
->num_compute
)
1300 virgl_reemit_compute_resources(vctx
);
1301 vctx
->num_compute
++;
1303 virgl_encode_launch_grid(vctx
, info
);
1307 virgl_release_shader_binding(struct virgl_context
*vctx
,
1308 enum pipe_shader_type shader_type
)
1310 struct virgl_shader_binding_state
*binding
=
1311 &vctx
->shader_bindings
[shader_type
];
1313 while (binding
->view_enabled_mask
) {
1314 int i
= u_bit_scan(&binding
->view_enabled_mask
);
1315 pipe_sampler_view_reference(
1316 (struct pipe_sampler_view
**)&binding
->views
[i
], NULL
);
1319 while (binding
->ubo_enabled_mask
) {
1320 int i
= u_bit_scan(&binding
->ubo_enabled_mask
);
1321 pipe_resource_reference(&binding
->ubos
[i
].buffer
, NULL
);
1324 while (binding
->ssbo_enabled_mask
) {
1325 int i
= u_bit_scan(&binding
->ssbo_enabled_mask
);
1326 pipe_resource_reference(&binding
->ssbos
[i
].buffer
, NULL
);
1329 while (binding
->image_enabled_mask
) {
1330 int i
= u_bit_scan(&binding
->image_enabled_mask
);
1331 pipe_resource_reference(&binding
->images
[i
].resource
, NULL
);
1336 virgl_context_destroy( struct pipe_context
*ctx
)
1338 struct virgl_context
*vctx
= virgl_context(ctx
);
1339 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1340 enum pipe_shader_type shader_type
;
1342 vctx
->framebuffer
.zsbuf
= NULL
;
1343 vctx
->framebuffer
.nr_cbufs
= 0;
1344 virgl_encoder_destroy_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1345 virgl_flush_eq(vctx
, vctx
, NULL
);
1347 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++)
1348 virgl_release_shader_binding(vctx
, shader_type
);
1350 while (vctx
->atomic_buffer_enabled_mask
) {
1351 int i
= u_bit_scan(&vctx
->atomic_buffer_enabled_mask
);
1352 pipe_resource_reference(&vctx
->atomic_buffers
[i
].buffer
, NULL
);
1355 rs
->vws
->cmd_buf_destroy(vctx
->cbuf
);
1357 u_upload_destroy(vctx
->uploader
);
1358 if (vctx
->transfer_uploader
)
1359 u_upload_destroy(vctx
->transfer_uploader
);
1360 util_primconvert_destroy(vctx
->primconvert
);
1361 virgl_transfer_queue_fini(&vctx
->queue
);
1363 slab_destroy_child(&vctx
->transfer_pool
);
1367 static void virgl_get_sample_position(struct pipe_context
*ctx
,
1368 unsigned sample_count
,
1372 struct virgl_context
*vctx
= virgl_context(ctx
);
1373 struct virgl_screen
*vs
= virgl_screen(vctx
->base
.screen
);
1375 if (sample_count
> vs
->caps
.caps
.v1
.max_samples
) {
1376 debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1377 sample_count
, vs
->caps
.caps
.v1
.max_samples
);
1381 /* The following is basically copied from dri/i965gen6_get_sample_position
1382 * The only addition is that we hold the msaa positions for all sample
1383 * counts in a flat array. */
1385 if (sample_count
== 1) {
1386 out_value
[0] = out_value
[1] = 0.5f
;
1388 } else if (sample_count
== 2) {
1389 bits
= vs
->caps
.caps
.v2
.sample_locations
[0] >> (8 * index
);
1390 } else if (sample_count
<= 4) {
1391 bits
= vs
->caps
.caps
.v2
.sample_locations
[1] >> (8 * index
);
1392 } else if (sample_count
<= 8) {
1393 bits
= vs
->caps
.caps
.v2
.sample_locations
[2 + (index
>> 2)] >> (8 * (index
& 3));
1394 } else if (sample_count
<= 16) {
1395 bits
= vs
->caps
.caps
.v2
.sample_locations
[4 + (index
>> 2)] >> (8 * (index
& 3));
1397 out_value
[0] = ((bits
>> 4) & 0xf) / 16.0f
;
1398 out_value
[1] = (bits
& 0xf) / 16.0f
;
1400 if (virgl_debug
& VIRGL_DEBUG_VERBOSE
)
1401 debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1402 index
, sample_count
, out_value
[0], out_value
[1]);
1405 struct pipe_context
*virgl_context_create(struct pipe_screen
*pscreen
,
1409 struct virgl_context
*vctx
;
1410 struct virgl_screen
*rs
= virgl_screen(pscreen
);
1411 vctx
= CALLOC_STRUCT(virgl_context
);
1412 const char *host_debug_flagstring
;
1414 vctx
->cbuf
= rs
->vws
->cmd_buf_create(rs
->vws
, VIRGL_MAX_CMDBUF_DWORDS
);
1420 vctx
->base
.destroy
= virgl_context_destroy
;
1421 vctx
->base
.create_surface
= virgl_create_surface
;
1422 vctx
->base
.surface_destroy
= virgl_surface_destroy
;
1423 vctx
->base
.set_framebuffer_state
= virgl_set_framebuffer_state
;
1424 vctx
->base
.create_blend_state
= virgl_create_blend_state
;
1425 vctx
->base
.bind_blend_state
= virgl_bind_blend_state
;
1426 vctx
->base
.delete_blend_state
= virgl_delete_blend_state
;
1427 vctx
->base
.create_depth_stencil_alpha_state
= virgl_create_depth_stencil_alpha_state
;
1428 vctx
->base
.bind_depth_stencil_alpha_state
= virgl_bind_depth_stencil_alpha_state
;
1429 vctx
->base
.delete_depth_stencil_alpha_state
= virgl_delete_depth_stencil_alpha_state
;
1430 vctx
->base
.create_rasterizer_state
= virgl_create_rasterizer_state
;
1431 vctx
->base
.bind_rasterizer_state
= virgl_bind_rasterizer_state
;
1432 vctx
->base
.delete_rasterizer_state
= virgl_delete_rasterizer_state
;
1434 vctx
->base
.set_viewport_states
= virgl_set_viewport_states
;
1435 vctx
->base
.create_vertex_elements_state
= virgl_create_vertex_elements_state
;
1436 vctx
->base
.bind_vertex_elements_state
= virgl_bind_vertex_elements_state
;
1437 vctx
->base
.delete_vertex_elements_state
= virgl_delete_vertex_elements_state
;
1438 vctx
->base
.set_vertex_buffers
= virgl_set_vertex_buffers
;
1439 vctx
->base
.set_constant_buffer
= virgl_set_constant_buffer
;
1441 vctx
->base
.set_tess_state
= virgl_set_tess_state
;
1442 vctx
->base
.create_vs_state
= virgl_create_vs_state
;
1443 vctx
->base
.create_tcs_state
= virgl_create_tcs_state
;
1444 vctx
->base
.create_tes_state
= virgl_create_tes_state
;
1445 vctx
->base
.create_gs_state
= virgl_create_gs_state
;
1446 vctx
->base
.create_fs_state
= virgl_create_fs_state
;
1448 vctx
->base
.bind_vs_state
= virgl_bind_vs_state
;
1449 vctx
->base
.bind_tcs_state
= virgl_bind_tcs_state
;
1450 vctx
->base
.bind_tes_state
= virgl_bind_tes_state
;
1451 vctx
->base
.bind_gs_state
= virgl_bind_gs_state
;
1452 vctx
->base
.bind_fs_state
= virgl_bind_fs_state
;
1454 vctx
->base
.delete_vs_state
= virgl_delete_vs_state
;
1455 vctx
->base
.delete_tcs_state
= virgl_delete_tcs_state
;
1456 vctx
->base
.delete_tes_state
= virgl_delete_tes_state
;
1457 vctx
->base
.delete_gs_state
= virgl_delete_gs_state
;
1458 vctx
->base
.delete_fs_state
= virgl_delete_fs_state
;
1460 vctx
->base
.create_compute_state
= virgl_create_compute_state
;
1461 vctx
->base
.bind_compute_state
= virgl_bind_compute_state
;
1462 vctx
->base
.delete_compute_state
= virgl_delete_compute_state
;
1463 vctx
->base
.launch_grid
= virgl_launch_grid
;
1465 vctx
->base
.clear
= virgl_clear
;
1466 vctx
->base
.draw_vbo
= virgl_draw_vbo
;
1467 vctx
->base
.flush
= virgl_flush_from_st
;
1468 vctx
->base
.screen
= pscreen
;
1469 vctx
->base
.create_sampler_view
= virgl_create_sampler_view
;
1470 vctx
->base
.sampler_view_destroy
= virgl_destroy_sampler_view
;
1471 vctx
->base
.set_sampler_views
= virgl_set_sampler_views
;
1472 vctx
->base
.texture_barrier
= virgl_texture_barrier
;
1474 vctx
->base
.create_sampler_state
= virgl_create_sampler_state
;
1475 vctx
->base
.delete_sampler_state
= virgl_delete_sampler_state
;
1476 vctx
->base
.bind_sampler_states
= virgl_bind_sampler_states
;
1478 vctx
->base
.set_polygon_stipple
= virgl_set_polygon_stipple
;
1479 vctx
->base
.set_scissor_states
= virgl_set_scissor_states
;
1480 vctx
->base
.set_sample_mask
= virgl_set_sample_mask
;
1481 vctx
->base
.set_min_samples
= virgl_set_min_samples
;
1482 vctx
->base
.set_stencil_ref
= virgl_set_stencil_ref
;
1483 vctx
->base
.set_clip_state
= virgl_set_clip_state
;
1485 vctx
->base
.set_blend_color
= virgl_set_blend_color
;
1487 vctx
->base
.get_sample_position
= virgl_get_sample_position
;
1489 vctx
->base
.resource_copy_region
= virgl_resource_copy_region
;
1490 vctx
->base
.flush_resource
= virgl_flush_resource
;
1491 vctx
->base
.blit
= virgl_blit
;
1492 vctx
->base
.create_fence_fd
= virgl_create_fence_fd
;
1493 vctx
->base
.fence_server_sync
= virgl_fence_server_sync
;
1495 vctx
->base
.set_shader_buffers
= virgl_set_shader_buffers
;
1496 vctx
->base
.set_hw_atomic_buffers
= virgl_set_hw_atomic_buffers
;
1497 vctx
->base
.set_shader_images
= virgl_set_shader_images
;
1498 vctx
->base
.memory_barrier
= virgl_memory_barrier
;
1500 virgl_init_context_resource_functions(&vctx
->base
);
1501 virgl_init_query_functions(vctx
);
1502 virgl_init_so_functions(vctx
);
1504 slab_create_child(&vctx
->transfer_pool
, &rs
->transfer_pool
);
1505 virgl_transfer_queue_init(&vctx
->queue
, vctx
);
1506 vctx
->encoded_transfers
= (rs
->vws
->supports_encoded_transfers
&&
1507 (rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TRANSFER
));
1509 /* Reserve some space for transfers. */
1510 if (vctx
->encoded_transfers
)
1511 vctx
->cbuf
->cdw
= VIRGL_MAX_TBUF_DWORDS
;
1513 vctx
->primconvert
= util_primconvert_create(&vctx
->base
, rs
->caps
.caps
.v1
.prim_mask
);
1514 vctx
->uploader
= u_upload_create(&vctx
->base
, 1024 * 1024,
1515 PIPE_BIND_INDEX_BUFFER
, PIPE_USAGE_STREAM
, 0);
1516 if (!vctx
->uploader
)
1518 vctx
->base
.stream_uploader
= vctx
->uploader
;
1519 vctx
->base
.const_uploader
= vctx
->uploader
;
1520 /* Use a custom/staging buffer for the transfer uploader, since we are
1521 * using it only for copies to other resources.
1523 if ((rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_COPY_TRANSFER
) &&
1524 vctx
->encoded_transfers
) {
1525 vctx
->transfer_uploader
= u_upload_create(&vctx
->base
, 1024 * 1024,
1528 VIRGL_RESOURCE_FLAG_STAGING
);
1529 if (!vctx
->transfer_uploader
)
1533 vctx
->hw_sub_ctx_id
= rs
->sub_ctx_id
++;
1534 virgl_encoder_create_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1536 virgl_encoder_set_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1538 if (rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_GUEST_MAY_INIT_LOG
) {
1539 host_debug_flagstring
= getenv("VIRGL_HOST_DEBUG");
1540 if (host_debug_flagstring
)
1541 virgl_encode_host_debug_flagstring(vctx
, host_debug_flagstring
);
1546 virgl_context_destroy(&vctx
->base
);