2 * Copyright 2014, 2015 Red Hat.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_shader_tokens.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31 #include "util/u_inlines.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_prim.h"
35 #include "util/u_transfer.h"
36 #include "util/u_helpers.h"
37 #include "util/slab.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_blitter.h"
40 #include "tgsi/tgsi_text.h"
41 #include "indices/u_primconvert.h"
43 #include "pipebuffer/pb_buffer.h"
45 #include "virgl_encode.h"
46 #include "virgl_context.h"
47 #include "virgl_protocol.h"
48 #include "virgl_resource.h"
49 #include "virgl_screen.h"
51 struct virgl_vertex_elements_state
{
53 uint8_t binding_map
[PIPE_MAX_ATTRIBS
];
57 static uint32_t next_handle
;
58 uint32_t virgl_object_assign_handle(void)
63 static void virgl_attach_res_framebuffer(struct virgl_context
*vctx
)
65 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
66 struct pipe_surface
*surf
;
67 struct virgl_resource
*res
;
70 surf
= vctx
->framebuffer
.zsbuf
;
72 res
= virgl_resource(surf
->texture
);
74 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
75 virgl_resource_dirty(res
, surf
->u
.tex
.level
);
78 for (i
= 0; i
< vctx
->framebuffer
.nr_cbufs
; i
++) {
79 surf
= vctx
->framebuffer
.cbufs
[i
];
81 res
= virgl_resource(surf
->texture
);
83 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
84 virgl_resource_dirty(res
, surf
->u
.tex
.level
);
90 static void virgl_attach_res_sampler_views(struct virgl_context
*vctx
,
91 enum pipe_shader_type shader_type
)
93 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
94 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
95 struct virgl_resource
*res
;
96 uint32_t remaining_mask
= tinfo
->enabled_mask
;
98 while (remaining_mask
) {
99 i
= u_bit_scan(&remaining_mask
);
100 assert(tinfo
->views
[i
]);
102 res
= virgl_resource(tinfo
->views
[i
]->base
.texture
);
104 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
108 static void virgl_attach_res_vertex_buffers(struct virgl_context
*vctx
)
110 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
111 struct virgl_resource
*res
;
114 for (i
= 0; i
< vctx
->num_vertex_buffers
; i
++) {
115 res
= virgl_resource(vctx
->vertex_buffer
[i
].buffer
.resource
);
117 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
121 static void virgl_attach_res_index_buffer(struct virgl_context
*vctx
,
122 struct virgl_indexbuf
*ib
)
124 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
125 struct virgl_resource
*res
;
127 res
= virgl_resource(ib
->buffer
);
129 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
132 static void virgl_attach_res_so_targets(struct virgl_context
*vctx
)
134 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
135 struct virgl_resource
*res
;
138 for (i
= 0; i
< vctx
->num_so_targets
; i
++) {
139 res
= virgl_resource(vctx
->so_targets
[i
].base
.buffer
);
141 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
145 static void virgl_attach_res_uniform_buffers(struct virgl_context
*vctx
,
146 enum pipe_shader_type shader_type
)
148 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
149 struct virgl_resource
*res
;
151 for (i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
152 res
= virgl_resource(vctx
->ubos
[shader_type
][i
]);
154 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
159 static void virgl_attach_res_shader_buffers(struct virgl_context
*vctx
,
160 enum pipe_shader_type shader_type
)
162 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
163 struct virgl_resource
*res
;
165 for (i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
166 res
= virgl_resource(vctx
->ssbos
[shader_type
][i
]);
168 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
173 static void virgl_attach_res_shader_images(struct virgl_context
*vctx
,
174 enum pipe_shader_type shader_type
)
176 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
177 struct virgl_resource
*res
;
179 for (i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
180 res
= virgl_resource(vctx
->images
[shader_type
][i
]);
182 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
187 static void virgl_attach_res_atomic_buffers(struct virgl_context
*vctx
)
189 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
190 struct virgl_resource
*res
;
192 for (i
= 0; i
< PIPE_MAX_HW_ATOMIC_BUFFERS
; i
++) {
193 res
= virgl_resource(vctx
->atomic_buffers
[i
]);
195 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
201 * after flushing, the hw context still has a bunch of
202 * resources bound, so we need to rebind those here.
204 static void virgl_reemit_res(struct virgl_context
*vctx
)
206 enum pipe_shader_type shader_type
;
208 /* reattach any flushed resources */
209 /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
210 virgl_attach_res_framebuffer(vctx
);
212 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
213 virgl_attach_res_sampler_views(vctx
, shader_type
);
214 virgl_attach_res_uniform_buffers(vctx
, shader_type
);
215 virgl_attach_res_shader_buffers(vctx
, shader_type
);
216 virgl_attach_res_shader_images(vctx
, shader_type
);
218 virgl_attach_res_atomic_buffers(vctx
);
219 virgl_attach_res_vertex_buffers(vctx
);
220 virgl_attach_res_so_targets(vctx
);
223 static struct pipe_surface
*virgl_create_surface(struct pipe_context
*ctx
,
224 struct pipe_resource
*resource
,
225 const struct pipe_surface
*templ
)
227 struct virgl_context
*vctx
= virgl_context(ctx
);
228 struct virgl_surface
*surf
;
229 struct virgl_resource
*res
= virgl_resource(resource
);
232 surf
= CALLOC_STRUCT(virgl_surface
);
236 assert(ctx
->screen
->get_param(ctx
->screen
,
237 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL
) ||
238 (util_format_is_srgb(templ
->format
) ==
239 util_format_is_srgb(resource
->format
)));
241 virgl_resource_dirty(res
, 0);
242 handle
= virgl_object_assign_handle();
243 pipe_reference_init(&surf
->base
.reference
, 1);
244 pipe_resource_reference(&surf
->base
.texture
, resource
);
245 surf
->base
.context
= ctx
;
246 surf
->base
.format
= templ
->format
;
247 if (resource
->target
!= PIPE_BUFFER
) {
248 surf
->base
.width
= u_minify(resource
->width0
, templ
->u
.tex
.level
);
249 surf
->base
.height
= u_minify(resource
->height0
, templ
->u
.tex
.level
);
250 surf
->base
.u
.tex
.level
= templ
->u
.tex
.level
;
251 surf
->base
.u
.tex
.first_layer
= templ
->u
.tex
.first_layer
;
252 surf
->base
.u
.tex
.last_layer
= templ
->u
.tex
.last_layer
;
254 surf
->base
.width
= templ
->u
.buf
.last_element
- templ
->u
.buf
.first_element
+ 1;
255 surf
->base
.height
= resource
->height0
;
256 surf
->base
.u
.buf
.first_element
= templ
->u
.buf
.first_element
;
257 surf
->base
.u
.buf
.last_element
= templ
->u
.buf
.last_element
;
259 virgl_encoder_create_surface(vctx
, handle
, res
, &surf
->base
);
260 surf
->handle
= handle
;
264 static void virgl_surface_destroy(struct pipe_context
*ctx
,
265 struct pipe_surface
*psurf
)
267 struct virgl_context
*vctx
= virgl_context(ctx
);
268 struct virgl_surface
*surf
= virgl_surface(psurf
);
270 pipe_resource_reference(&surf
->base
.texture
, NULL
);
271 virgl_encode_delete_object(vctx
, surf
->handle
, VIRGL_OBJECT_SURFACE
);
275 static void *virgl_create_blend_state(struct pipe_context
*ctx
,
276 const struct pipe_blend_state
*blend_state
)
278 struct virgl_context
*vctx
= virgl_context(ctx
);
280 handle
= virgl_object_assign_handle();
282 virgl_encode_blend_state(vctx
, handle
, blend_state
);
283 return (void *)(unsigned long)handle
;
287 static void virgl_bind_blend_state(struct pipe_context
*ctx
,
290 struct virgl_context
*vctx
= virgl_context(ctx
);
291 uint32_t handle
= (unsigned long)blend_state
;
292 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
295 static void virgl_delete_blend_state(struct pipe_context
*ctx
,
298 struct virgl_context
*vctx
= virgl_context(ctx
);
299 uint32_t handle
= (unsigned long)blend_state
;
300 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
303 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context
*ctx
,
304 const struct pipe_depth_stencil_alpha_state
*blend_state
)
306 struct virgl_context
*vctx
= virgl_context(ctx
);
308 handle
= virgl_object_assign_handle();
310 virgl_encode_dsa_state(vctx
, handle
, blend_state
);
311 return (void *)(unsigned long)handle
;
314 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context
*ctx
,
317 struct virgl_context
*vctx
= virgl_context(ctx
);
318 uint32_t handle
= (unsigned long)blend_state
;
319 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
322 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context
*ctx
,
325 struct virgl_context
*vctx
= virgl_context(ctx
);
326 uint32_t handle
= (unsigned long)dsa_state
;
327 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
330 static void *virgl_create_rasterizer_state(struct pipe_context
*ctx
,
331 const struct pipe_rasterizer_state
*rs_state
)
333 struct virgl_context
*vctx
= virgl_context(ctx
);
334 struct virgl_rasterizer_state
*vrs
= CALLOC_STRUCT(virgl_rasterizer_state
);
339 vrs
->handle
= virgl_object_assign_handle();
341 virgl_encode_rasterizer_state(vctx
, vrs
->handle
, rs_state
);
345 static void virgl_bind_rasterizer_state(struct pipe_context
*ctx
,
348 struct virgl_context
*vctx
= virgl_context(ctx
);
351 struct virgl_rasterizer_state
*vrs
= rs_state
;
352 vctx
->rs_state
= *vrs
;
353 handle
= vrs
->handle
;
355 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
358 static void virgl_delete_rasterizer_state(struct pipe_context
*ctx
,
361 struct virgl_context
*vctx
= virgl_context(ctx
);
362 struct virgl_rasterizer_state
*vrs
= rs_state
;
363 virgl_encode_delete_object(vctx
, vrs
->handle
, VIRGL_OBJECT_RASTERIZER
);
367 static void virgl_set_framebuffer_state(struct pipe_context
*ctx
,
368 const struct pipe_framebuffer_state
*state
)
370 struct virgl_context
*vctx
= virgl_context(ctx
);
372 vctx
->framebuffer
= *state
;
373 virgl_encoder_set_framebuffer_state(vctx
, state
);
374 virgl_attach_res_framebuffer(vctx
);
377 static void virgl_set_viewport_states(struct pipe_context
*ctx
,
379 unsigned num_viewports
,
380 const struct pipe_viewport_state
*state
)
382 struct virgl_context
*vctx
= virgl_context(ctx
);
383 virgl_encoder_set_viewport_states(vctx
, start_slot
, num_viewports
, state
);
386 static void *virgl_create_vertex_elements_state(struct pipe_context
*ctx
,
387 unsigned num_elements
,
388 const struct pipe_vertex_element
*elements
)
390 struct pipe_vertex_element new_elements
[PIPE_MAX_ATTRIBS
];
391 struct virgl_context
*vctx
= virgl_context(ctx
);
392 struct virgl_vertex_elements_state
*state
=
393 CALLOC_STRUCT(virgl_vertex_elements_state
);
395 for (int i
= 0; i
< num_elements
; ++i
) {
396 if (elements
[i
].instance_divisor
) {
397 /* Virglrenderer doesn't deal with instance_divisor correctly if
398 * there isn't a 1:1 relationship between elements and bindings.
399 * So let's make sure there is, by duplicating bindings.
401 for (int j
= 0; j
< num_elements
; ++j
) {
402 new_elements
[j
] = elements
[j
];
403 new_elements
[j
].vertex_buffer_index
= j
;
404 state
->binding_map
[j
] = elements
[j
].vertex_buffer_index
;
406 elements
= new_elements
;
407 state
->num_bindings
= num_elements
;
412 state
->handle
= virgl_object_assign_handle();
413 virgl_encoder_create_vertex_elements(vctx
, state
->handle
,
414 num_elements
, elements
);
418 static void virgl_delete_vertex_elements_state(struct pipe_context
*ctx
,
421 struct virgl_context
*vctx
= virgl_context(ctx
);
422 struct virgl_vertex_elements_state
*state
=
423 (struct virgl_vertex_elements_state
*)ve
;
424 virgl_encode_delete_object(vctx
, state
->handle
, VIRGL_OBJECT_VERTEX_ELEMENTS
);
428 static void virgl_bind_vertex_elements_state(struct pipe_context
*ctx
,
431 struct virgl_context
*vctx
= virgl_context(ctx
);
432 struct virgl_vertex_elements_state
*state
=
433 (struct virgl_vertex_elements_state
*)ve
;
434 vctx
->vertex_elements
= state
;
435 virgl_encode_bind_object(vctx
, state
? state
->handle
: 0,
436 VIRGL_OBJECT_VERTEX_ELEMENTS
);
437 vctx
->vertex_array_dirty
= TRUE
;
440 static void virgl_set_vertex_buffers(struct pipe_context
*ctx
,
442 unsigned num_buffers
,
443 const struct pipe_vertex_buffer
*buffers
)
445 struct virgl_context
*vctx
= virgl_context(ctx
);
447 util_set_vertex_buffers_count(vctx
->vertex_buffer
,
448 &vctx
->num_vertex_buffers
,
449 buffers
, start_slot
, num_buffers
);
451 vctx
->vertex_array_dirty
= TRUE
;
454 static void virgl_hw_set_vertex_buffers(struct virgl_context
*vctx
)
456 if (vctx
->vertex_array_dirty
) {
457 struct virgl_vertex_elements_state
*ve
= vctx
->vertex_elements
;
459 if (ve
->num_bindings
) {
460 struct pipe_vertex_buffer vertex_buffers
[PIPE_MAX_ATTRIBS
];
461 for (int i
= 0; i
< ve
->num_bindings
; ++i
)
462 vertex_buffers
[i
] = vctx
->vertex_buffer
[ve
->binding_map
[i
]];
464 virgl_encoder_set_vertex_buffers(vctx
, ve
->num_bindings
, vertex_buffers
);
466 virgl_encoder_set_vertex_buffers(vctx
, vctx
->num_vertex_buffers
, vctx
->vertex_buffer
);
468 virgl_attach_res_vertex_buffers(vctx
);
472 static void virgl_set_stencil_ref(struct pipe_context
*ctx
,
473 const struct pipe_stencil_ref
*ref
)
475 struct virgl_context
*vctx
= virgl_context(ctx
);
476 virgl_encoder_set_stencil_ref(vctx
, ref
);
479 static void virgl_set_blend_color(struct pipe_context
*ctx
,
480 const struct pipe_blend_color
*color
)
482 struct virgl_context
*vctx
= virgl_context(ctx
);
483 virgl_encoder_set_blend_color(vctx
, color
);
486 static void virgl_hw_set_index_buffer(struct virgl_context
*vctx
,
487 struct virgl_indexbuf
*ib
)
489 virgl_encoder_set_index_buffer(vctx
, ib
);
490 virgl_attach_res_index_buffer(vctx
, ib
);
493 static void virgl_set_constant_buffer(struct pipe_context
*ctx
,
494 enum pipe_shader_type shader
, uint index
,
495 const struct pipe_constant_buffer
*buf
)
497 struct virgl_context
*vctx
= virgl_context(ctx
);
500 if (!buf
->user_buffer
){
501 struct virgl_resource
*res
= virgl_resource(buf
->buffer
);
502 virgl_encoder_set_uniform_buffer(vctx
, shader
, index
, buf
->buffer_offset
,
503 buf
->buffer_size
, res
);
504 pipe_resource_reference(&vctx
->ubos
[shader
][index
], buf
->buffer
);
507 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
508 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, buf
->buffer_size
/ 4, buf
->user_buffer
);
510 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, 0, NULL
);
511 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
515 void virgl_transfer_inline_write(struct pipe_context
*ctx
,
516 struct pipe_resource
*res
,
519 const struct pipe_box
*box
,
522 unsigned layer_stride
)
524 struct virgl_context
*vctx
= virgl_context(ctx
);
525 struct virgl_screen
*vs
= virgl_screen(ctx
->screen
);
526 struct virgl_resource
*grres
= virgl_resource(res
);
528 virgl_resource_dirty(grres
, 0);
530 if (virgl_res_needs_flush_wait(vctx
, grres
, usage
)) {
531 ctx
->flush(ctx
, NULL
, 0);
533 vs
->vws
->resource_wait(vs
->vws
, grres
->hw_res
);
536 virgl_encoder_inline_write(vctx
, grres
, level
, usage
,
537 box
, data
, stride
, layer_stride
);
540 static void *virgl_shader_encoder(struct pipe_context
*ctx
,
541 const struct pipe_shader_state
*shader
,
544 struct virgl_context
*vctx
= virgl_context(ctx
);
546 struct tgsi_token
*new_tokens
;
549 new_tokens
= virgl_tgsi_transform(vctx
, shader
->tokens
);
553 handle
= virgl_object_assign_handle();
554 /* encode VS state */
555 ret
= virgl_encode_shader_state(vctx
, handle
, type
,
556 &shader
->stream_output
, 0,
563 return (void *)(unsigned long)handle
;
566 static void *virgl_create_vs_state(struct pipe_context
*ctx
,
567 const struct pipe_shader_state
*shader
)
569 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_VERTEX
);
572 static void *virgl_create_tcs_state(struct pipe_context
*ctx
,
573 const struct pipe_shader_state
*shader
)
575 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_CTRL
);
578 static void *virgl_create_tes_state(struct pipe_context
*ctx
,
579 const struct pipe_shader_state
*shader
)
581 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_EVAL
);
584 static void *virgl_create_gs_state(struct pipe_context
*ctx
,
585 const struct pipe_shader_state
*shader
)
587 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_GEOMETRY
);
590 static void *virgl_create_fs_state(struct pipe_context
*ctx
,
591 const struct pipe_shader_state
*shader
)
593 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_FRAGMENT
);
597 virgl_delete_fs_state(struct pipe_context
*ctx
,
600 uint32_t handle
= (unsigned long)fs
;
601 struct virgl_context
*vctx
= virgl_context(ctx
);
603 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
607 virgl_delete_gs_state(struct pipe_context
*ctx
,
610 uint32_t handle
= (unsigned long)gs
;
611 struct virgl_context
*vctx
= virgl_context(ctx
);
613 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
617 virgl_delete_vs_state(struct pipe_context
*ctx
,
620 uint32_t handle
= (unsigned long)vs
;
621 struct virgl_context
*vctx
= virgl_context(ctx
);
623 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
627 virgl_delete_tcs_state(struct pipe_context
*ctx
,
630 uint32_t handle
= (unsigned long)tcs
;
631 struct virgl_context
*vctx
= virgl_context(ctx
);
633 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
637 virgl_delete_tes_state(struct pipe_context
*ctx
,
640 uint32_t handle
= (unsigned long)tes
;
641 struct virgl_context
*vctx
= virgl_context(ctx
);
643 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
646 static void virgl_bind_vs_state(struct pipe_context
*ctx
,
649 uint32_t handle
= (unsigned long)vss
;
650 struct virgl_context
*vctx
= virgl_context(ctx
);
652 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_VERTEX
);
655 static void virgl_bind_tcs_state(struct pipe_context
*ctx
,
658 uint32_t handle
= (unsigned long)vss
;
659 struct virgl_context
*vctx
= virgl_context(ctx
);
661 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_CTRL
);
664 static void virgl_bind_tes_state(struct pipe_context
*ctx
,
667 uint32_t handle
= (unsigned long)vss
;
668 struct virgl_context
*vctx
= virgl_context(ctx
);
670 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_EVAL
);
673 static void virgl_bind_gs_state(struct pipe_context
*ctx
,
676 uint32_t handle
= (unsigned long)vss
;
677 struct virgl_context
*vctx
= virgl_context(ctx
);
679 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_GEOMETRY
);
683 static void virgl_bind_fs_state(struct pipe_context
*ctx
,
686 uint32_t handle
= (unsigned long)vss
;
687 struct virgl_context
*vctx
= virgl_context(ctx
);
689 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_FRAGMENT
);
692 static void virgl_clear(struct pipe_context
*ctx
,
694 const union pipe_color_union
*color
,
695 double depth
, unsigned stencil
)
697 struct virgl_context
*vctx
= virgl_context(ctx
);
699 virgl_encode_clear(vctx
, buffers
, color
, depth
, stencil
);
702 static void virgl_draw_vbo(struct pipe_context
*ctx
,
703 const struct pipe_draw_info
*dinfo
)
705 struct virgl_context
*vctx
= virgl_context(ctx
);
706 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
707 struct virgl_indexbuf ib
= {};
708 struct pipe_draw_info info
= *dinfo
;
710 if (!dinfo
->count_from_stream_output
&& !dinfo
->indirect
&&
711 !dinfo
->primitive_restart
&&
712 !u_trim_pipe_prim(dinfo
->mode
, (unsigned*)&dinfo
->count
))
715 if (!(rs
->caps
.caps
.v1
.prim_mask
& (1 << dinfo
->mode
))) {
716 util_primconvert_save_rasterizer_state(vctx
->primconvert
, &vctx
->rs_state
.rs
);
717 util_primconvert_draw_vbo(vctx
->primconvert
, dinfo
);
720 if (info
.index_size
) {
721 pipe_resource_reference(&ib
.buffer
, info
.has_user_indices
? NULL
: info
.index
.resource
);
722 ib
.user_buffer
= info
.has_user_indices
? info
.index
.user
: NULL
;
723 ib
.index_size
= dinfo
->index_size
;
724 ib
.offset
= info
.start
* ib
.index_size
;
726 if (ib
.user_buffer
) {
727 u_upload_data(vctx
->uploader
, 0, info
.count
* ib
.index_size
, 4,
728 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
729 ib
.user_buffer
= NULL
;
734 virgl_hw_set_vertex_buffers(vctx
);
736 virgl_hw_set_index_buffer(vctx
, &ib
);
738 virgl_encoder_draw_vbo(vctx
, &info
);
740 pipe_resource_reference(&ib
.buffer
, NULL
);
744 static void virgl_flush_eq(struct virgl_context
*ctx
, void *closure
,
745 struct pipe_fence_handle
**fence
)
747 struct virgl_screen
*rs
= virgl_screen(ctx
->base
.screen
);
748 int out_fence_fd
= -1;
751 u_upload_unmap(ctx
->uploader
);
753 /* send the buffer to the remote side for decoding */
754 ctx
->num_transfers
= ctx
->num_draws
= ctx
->num_compute
= 0;
756 rs
->vws
->submit_cmd(rs
->vws
, ctx
->cbuf
, ctx
->cbuf
->in_fence_fd
,
757 ctx
->cbuf
->needs_out_fence_fd
? &out_fence_fd
: NULL
);
760 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, out_fence_fd
);
762 virgl_encoder_set_sub_ctx(ctx
, ctx
->hw_sub_ctx_id
);
764 /* add back current framebuffer resources to reference list? */
765 virgl_reemit_res(ctx
);
768 static void virgl_flush_from_st(struct pipe_context
*ctx
,
769 struct pipe_fence_handle
**fence
,
770 enum pipe_flush_flags flags
)
772 struct virgl_context
*vctx
= virgl_context(ctx
);
773 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
775 if (flags
& PIPE_FLUSH_FENCE_FD
)
776 vctx
->cbuf
->needs_out_fence_fd
= true;
778 virgl_flush_eq(vctx
, vctx
, fence
);
780 if (vctx
->cbuf
->in_fence_fd
!= -1) {
781 close(vctx
->cbuf
->in_fence_fd
);
782 vctx
->cbuf
->in_fence_fd
= -1;
784 vctx
->cbuf
->needs_out_fence_fd
= false;
787 static struct pipe_sampler_view
*virgl_create_sampler_view(struct pipe_context
*ctx
,
788 struct pipe_resource
*texture
,
789 const struct pipe_sampler_view
*state
)
791 struct virgl_context
*vctx
= virgl_context(ctx
);
792 struct virgl_sampler_view
*grview
;
794 struct virgl_resource
*res
;
799 grview
= CALLOC_STRUCT(virgl_sampler_view
);
803 res
= virgl_resource(texture
);
804 handle
= virgl_object_assign_handle();
805 virgl_encode_sampler_view(vctx
, handle
, res
, state
);
807 grview
->base
= *state
;
808 grview
->base
.reference
.count
= 1;
810 grview
->base
.texture
= NULL
;
811 grview
->base
.context
= ctx
;
812 pipe_resource_reference(&grview
->base
.texture
, texture
);
813 grview
->handle
= handle
;
814 return &grview
->base
;
817 static void virgl_set_sampler_views(struct pipe_context
*ctx
,
818 enum pipe_shader_type shader_type
,
821 struct pipe_sampler_view
**views
)
823 struct virgl_context
*vctx
= virgl_context(ctx
);
825 uint32_t disable_mask
= ~((1ull << num_views
) - 1);
826 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
827 uint32_t new_mask
= 0;
828 uint32_t remaining_mask
;
830 remaining_mask
= tinfo
->enabled_mask
& disable_mask
;
832 while (remaining_mask
) {
833 i
= u_bit_scan(&remaining_mask
);
834 assert(tinfo
->views
[i
]);
836 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
839 for (i
= 0; i
< num_views
; i
++) {
840 struct virgl_sampler_view
*grview
= virgl_sampler_view(views
[i
]);
842 if (views
[i
] == (struct pipe_sampler_view
*)tinfo
->views
[i
])
847 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], views
[i
]);
849 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
850 disable_mask
|= 1 << i
;
854 tinfo
->enabled_mask
&= ~disable_mask
;
855 tinfo
->enabled_mask
|= new_mask
;
856 virgl_encode_set_sampler_views(vctx
, shader_type
, start_slot
, num_views
, tinfo
->views
);
857 virgl_attach_res_sampler_views(vctx
, shader_type
);
861 virgl_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
863 struct virgl_context
*vctx
= virgl_context(ctx
);
864 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
866 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_BARRIER
))
868 virgl_encode_texture_barrier(vctx
, flags
);
871 static void virgl_destroy_sampler_view(struct pipe_context
*ctx
,
872 struct pipe_sampler_view
*view
)
874 struct virgl_context
*vctx
= virgl_context(ctx
);
875 struct virgl_sampler_view
*grview
= virgl_sampler_view(view
);
877 virgl_encode_delete_object(vctx
, grview
->handle
, VIRGL_OBJECT_SAMPLER_VIEW
);
878 pipe_resource_reference(&view
->texture
, NULL
);
882 static void *virgl_create_sampler_state(struct pipe_context
*ctx
,
883 const struct pipe_sampler_state
*state
)
885 struct virgl_context
*vctx
= virgl_context(ctx
);
888 handle
= virgl_object_assign_handle();
890 virgl_encode_sampler_state(vctx
, handle
, state
);
891 return (void *)(unsigned long)handle
;
894 static void virgl_delete_sampler_state(struct pipe_context
*ctx
,
897 struct virgl_context
*vctx
= virgl_context(ctx
);
898 uint32_t handle
= (unsigned long)ss
;
900 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SAMPLER_STATE
);
903 static void virgl_bind_sampler_states(struct pipe_context
*ctx
,
904 enum pipe_shader_type shader
,
906 unsigned num_samplers
,
909 struct virgl_context
*vctx
= virgl_context(ctx
);
910 uint32_t handles
[32];
912 for (i
= 0; i
< num_samplers
; i
++) {
913 handles
[i
] = (unsigned long)(samplers
[i
]);
915 virgl_encode_bind_sampler_states(vctx
, shader
, start_slot
, num_samplers
, handles
);
918 static void virgl_set_polygon_stipple(struct pipe_context
*ctx
,
919 const struct pipe_poly_stipple
*ps
)
921 struct virgl_context
*vctx
= virgl_context(ctx
);
922 virgl_encoder_set_polygon_stipple(vctx
, ps
);
925 static void virgl_set_scissor_states(struct pipe_context
*ctx
,
927 unsigned num_scissor
,
928 const struct pipe_scissor_state
*ss
)
930 struct virgl_context
*vctx
= virgl_context(ctx
);
931 virgl_encoder_set_scissor_state(vctx
, start_slot
, num_scissor
, ss
);
934 static void virgl_set_sample_mask(struct pipe_context
*ctx
,
935 unsigned sample_mask
)
937 struct virgl_context
*vctx
= virgl_context(ctx
);
938 virgl_encoder_set_sample_mask(vctx
, sample_mask
);
941 static void virgl_set_min_samples(struct pipe_context
*ctx
,
942 unsigned min_samples
)
944 struct virgl_context
*vctx
= virgl_context(ctx
);
945 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
947 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SET_MIN_SAMPLES
))
949 virgl_encoder_set_min_samples(vctx
, min_samples
);
952 static void virgl_set_clip_state(struct pipe_context
*ctx
,
953 const struct pipe_clip_state
*clip
)
955 struct virgl_context
*vctx
= virgl_context(ctx
);
956 virgl_encoder_set_clip_state(vctx
, clip
);
959 static void virgl_set_tess_state(struct pipe_context
*ctx
,
960 const float default_outer_level
[4],
961 const float default_inner_level
[2])
963 struct virgl_context
*vctx
= virgl_context(ctx
);
964 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
966 if (!rs
->caps
.caps
.v1
.bset
.has_tessellation_shaders
)
968 virgl_encode_set_tess_state(vctx
, default_outer_level
, default_inner_level
);
971 static void virgl_resource_copy_region(struct pipe_context
*ctx
,
972 struct pipe_resource
*dst
,
974 unsigned dstx
, unsigned dsty
, unsigned dstz
,
975 struct pipe_resource
*src
,
977 const struct pipe_box
*src_box
)
979 struct virgl_context
*vctx
= virgl_context(ctx
);
980 struct virgl_resource
*dres
= virgl_resource(dst
);
981 struct virgl_resource
*sres
= virgl_resource(src
);
983 virgl_resource_dirty(dres
, dst_level
);
984 virgl_encode_resource_copy_region(vctx
, dres
,
985 dst_level
, dstx
, dsty
, dstz
,
991 virgl_flush_resource(struct pipe_context
*pipe
,
992 struct pipe_resource
*resource
)
996 static void virgl_blit(struct pipe_context
*ctx
,
997 const struct pipe_blit_info
*blit
)
999 struct virgl_context
*vctx
= virgl_context(ctx
);
1000 struct virgl_resource
*dres
= virgl_resource(blit
->dst
.resource
);
1001 struct virgl_resource
*sres
= virgl_resource(blit
->src
.resource
);
1003 assert(ctx
->screen
->get_param(ctx
->screen
,
1004 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL
) ||
1005 (util_format_is_srgb(blit
->dst
.resource
->format
) ==
1006 util_format_is_srgb(blit
->dst
.format
)));
1008 virgl_resource_dirty(dres
, blit
->dst
.level
);
1009 virgl_encode_blit(vctx
, dres
, sres
,
1013 static void virgl_set_hw_atomic_buffers(struct pipe_context
*ctx
,
1014 unsigned start_slot
,
1016 const struct pipe_shader_buffer
*buffers
)
1018 struct virgl_context
*vctx
= virgl_context(ctx
);
1020 for (unsigned i
= 0; i
< count
; i
++) {
1021 unsigned idx
= start_slot
+ i
;
1024 if (buffers
[i
].buffer
) {
1025 pipe_resource_reference(&vctx
->atomic_buffers
[idx
],
1030 pipe_resource_reference(&vctx
->atomic_buffers
[idx
], NULL
);
1032 virgl_encode_set_hw_atomic_buffers(vctx
, start_slot
, count
, buffers
);
1035 static void virgl_set_shader_buffers(struct pipe_context
*ctx
,
1036 enum pipe_shader_type shader
,
1037 unsigned start_slot
, unsigned count
,
1038 const struct pipe_shader_buffer
*buffers
)
1040 struct virgl_context
*vctx
= virgl_context(ctx
);
1041 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1043 for (unsigned i
= 0; i
< count
; i
++) {
1044 unsigned idx
= start_slot
+ i
;
1047 if (buffers
[i
].buffer
) {
1048 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], buffers
[i
].buffer
);
1052 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], NULL
);
1055 uint32_t max_shader_buffer
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1056 rs
->caps
.caps
.v2
.max_shader_buffer_frag_compute
:
1057 rs
->caps
.caps
.v2
.max_shader_buffer_other_stages
;
1058 if (!max_shader_buffer
)
1060 virgl_encode_set_shader_buffers(vctx
, shader
, start_slot
, count
, buffers
);
1063 static void virgl_create_fence_fd(struct pipe_context
*ctx
,
1064 struct pipe_fence_handle
**fence
,
1066 enum pipe_fd_type type
)
1068 assert(type
== PIPE_FD_TYPE_NATIVE_SYNC
);
1069 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1071 if (rs
->vws
->cs_create_fence
)
1072 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, fd
);
1075 static void virgl_fence_server_sync(struct pipe_context
*ctx
,
1076 struct pipe_fence_handle
*fence
)
1078 struct virgl_context
*vctx
= virgl_context(ctx
);
1079 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1081 if (rs
->vws
->fence_server_sync
)
1082 rs
->vws
->fence_server_sync(rs
->vws
, vctx
->cbuf
, fence
);
1085 static void virgl_set_shader_images(struct pipe_context
*ctx
,
1086 enum pipe_shader_type shader
,
1087 unsigned start_slot
, unsigned count
,
1088 const struct pipe_image_view
*images
)
1090 struct virgl_context
*vctx
= virgl_context(ctx
);
1091 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1093 for (unsigned i
= 0; i
< count
; i
++) {
1094 unsigned idx
= start_slot
+ i
;
1097 if (images
[i
].resource
) {
1098 pipe_resource_reference(&vctx
->images
[shader
][idx
], images
[i
].resource
);
1102 pipe_resource_reference(&vctx
->images
[shader
][idx
], NULL
);
1105 uint32_t max_shader_images
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1106 rs
->caps
.caps
.v2
.max_shader_image_frag_compute
:
1107 rs
->caps
.caps
.v2
.max_shader_image_other_stages
;
1108 if (!max_shader_images
)
1110 virgl_encode_set_shader_images(vctx
, shader
, start_slot
, count
, images
);
1113 static void virgl_memory_barrier(struct pipe_context
*ctx
,
1116 struct virgl_context
*vctx
= virgl_context(ctx
);
1117 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1119 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_MEMORY_BARRIER
))
1121 virgl_encode_memory_barrier(vctx
, flags
);
1124 static void *virgl_create_compute_state(struct pipe_context
*ctx
,
1125 const struct pipe_compute_state
*state
)
1127 struct virgl_context
*vctx
= virgl_context(ctx
);
1129 const struct tgsi_token
*new_tokens
= state
->prog
;
1130 struct pipe_stream_output_info so_info
= {};
1133 handle
= virgl_object_assign_handle();
1134 ret
= virgl_encode_shader_state(vctx
, handle
, PIPE_SHADER_COMPUTE
,
1136 state
->req_local_mem
,
1142 return (void *)(unsigned long)handle
;
1145 static void virgl_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1147 uint32_t handle
= (unsigned long)state
;
1148 struct virgl_context
*vctx
= virgl_context(ctx
);
1150 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_COMPUTE
);
1153 static void virgl_delete_compute_state(struct pipe_context
*ctx
, void *state
)
1155 uint32_t handle
= (unsigned long)state
;
1156 struct virgl_context
*vctx
= virgl_context(ctx
);
1158 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
1161 static void virgl_launch_grid(struct pipe_context
*ctx
,
1162 const struct pipe_grid_info
*info
)
1164 struct virgl_context
*vctx
= virgl_context(ctx
);
1165 virgl_encode_launch_grid(vctx
, info
);
1166 vctx
->num_compute
++;
1170 virgl_context_destroy( struct pipe_context
*ctx
)
1172 struct virgl_context
*vctx
= virgl_context(ctx
);
1173 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1175 vctx
->framebuffer
.zsbuf
= NULL
;
1176 vctx
->framebuffer
.nr_cbufs
= 0;
1177 virgl_encoder_destroy_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1178 virgl_flush_eq(vctx
, vctx
, NULL
);
1180 rs
->vws
->cmd_buf_destroy(vctx
->cbuf
);
1182 u_upload_destroy(vctx
->uploader
);
1183 util_primconvert_destroy(vctx
->primconvert
);
1185 slab_destroy_child(&vctx
->transfer_pool
);
1189 static void virgl_get_sample_position(struct pipe_context
*ctx
,
1190 unsigned sample_count
,
1194 struct virgl_context
*vctx
= virgl_context(ctx
);
1195 struct virgl_screen
*vs
= virgl_screen(vctx
->base
.screen
);
1197 if (sample_count
> vs
->caps
.caps
.v1
.max_samples
) {
1198 debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1199 sample_count
, vs
->caps
.caps
.v1
.max_samples
);
1203 /* The following is basically copied from dri/i965gen6_get_sample_position
1204 * The only addition is that we hold the msaa positions for all sample
1205 * counts in a flat array. */
1207 if (sample_count
== 1) {
1208 out_value
[0] = out_value
[1] = 0.5f
;
1210 } else if (sample_count
== 2) {
1211 bits
= vs
->caps
.caps
.v2
.sample_locations
[0] >> (8 * index
);
1212 } else if (sample_count
<= 4) {
1213 bits
= vs
->caps
.caps
.v2
.sample_locations
[1] >> (8 * index
);
1214 } else if (sample_count
<= 8) {
1215 bits
= vs
->caps
.caps
.v2
.sample_locations
[2 + (index
>> 2)] >> (8 * (index
& 3));
1216 } else if (sample_count
<= 16) {
1217 bits
= vs
->caps
.caps
.v2
.sample_locations
[4 + (index
>> 2)] >> (8 * (index
& 3));
1219 out_value
[0] = ((bits
>> 4) & 0xf) / 16.0f
;
1220 out_value
[1] = (bits
& 0xf) / 16.0f
;
1222 if (virgl_debug
& VIRGL_DEBUG_VERBOSE
)
1223 debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1224 index
, sample_count
, out_value
[0], out_value
[1]);
1227 struct pipe_context
*virgl_context_create(struct pipe_screen
*pscreen
,
1231 struct virgl_context
*vctx
;
1232 struct virgl_screen
*rs
= virgl_screen(pscreen
);
1233 vctx
= CALLOC_STRUCT(virgl_context
);
1234 const char *host_debug_flagstring
;
1236 vctx
->cbuf
= rs
->vws
->cmd_buf_create(rs
->vws
);
1242 vctx
->base
.destroy
= virgl_context_destroy
;
1243 vctx
->base
.create_surface
= virgl_create_surface
;
1244 vctx
->base
.surface_destroy
= virgl_surface_destroy
;
1245 vctx
->base
.set_framebuffer_state
= virgl_set_framebuffer_state
;
1246 vctx
->base
.create_blend_state
= virgl_create_blend_state
;
1247 vctx
->base
.bind_blend_state
= virgl_bind_blend_state
;
1248 vctx
->base
.delete_blend_state
= virgl_delete_blend_state
;
1249 vctx
->base
.create_depth_stencil_alpha_state
= virgl_create_depth_stencil_alpha_state
;
1250 vctx
->base
.bind_depth_stencil_alpha_state
= virgl_bind_depth_stencil_alpha_state
;
1251 vctx
->base
.delete_depth_stencil_alpha_state
= virgl_delete_depth_stencil_alpha_state
;
1252 vctx
->base
.create_rasterizer_state
= virgl_create_rasterizer_state
;
1253 vctx
->base
.bind_rasterizer_state
= virgl_bind_rasterizer_state
;
1254 vctx
->base
.delete_rasterizer_state
= virgl_delete_rasterizer_state
;
1256 vctx
->base
.set_viewport_states
= virgl_set_viewport_states
;
1257 vctx
->base
.create_vertex_elements_state
= virgl_create_vertex_elements_state
;
1258 vctx
->base
.bind_vertex_elements_state
= virgl_bind_vertex_elements_state
;
1259 vctx
->base
.delete_vertex_elements_state
= virgl_delete_vertex_elements_state
;
1260 vctx
->base
.set_vertex_buffers
= virgl_set_vertex_buffers
;
1261 vctx
->base
.set_constant_buffer
= virgl_set_constant_buffer
;
1263 vctx
->base
.set_tess_state
= virgl_set_tess_state
;
1264 vctx
->base
.create_vs_state
= virgl_create_vs_state
;
1265 vctx
->base
.create_tcs_state
= virgl_create_tcs_state
;
1266 vctx
->base
.create_tes_state
= virgl_create_tes_state
;
1267 vctx
->base
.create_gs_state
= virgl_create_gs_state
;
1268 vctx
->base
.create_fs_state
= virgl_create_fs_state
;
1270 vctx
->base
.bind_vs_state
= virgl_bind_vs_state
;
1271 vctx
->base
.bind_tcs_state
= virgl_bind_tcs_state
;
1272 vctx
->base
.bind_tes_state
= virgl_bind_tes_state
;
1273 vctx
->base
.bind_gs_state
= virgl_bind_gs_state
;
1274 vctx
->base
.bind_fs_state
= virgl_bind_fs_state
;
1276 vctx
->base
.delete_vs_state
= virgl_delete_vs_state
;
1277 vctx
->base
.delete_tcs_state
= virgl_delete_tcs_state
;
1278 vctx
->base
.delete_tes_state
= virgl_delete_tes_state
;
1279 vctx
->base
.delete_gs_state
= virgl_delete_gs_state
;
1280 vctx
->base
.delete_fs_state
= virgl_delete_fs_state
;
1282 vctx
->base
.create_compute_state
= virgl_create_compute_state
;
1283 vctx
->base
.bind_compute_state
= virgl_bind_compute_state
;
1284 vctx
->base
.delete_compute_state
= virgl_delete_compute_state
;
1285 vctx
->base
.launch_grid
= virgl_launch_grid
;
1287 vctx
->base
.clear
= virgl_clear
;
1288 vctx
->base
.draw_vbo
= virgl_draw_vbo
;
1289 vctx
->base
.flush
= virgl_flush_from_st
;
1290 vctx
->base
.screen
= pscreen
;
1291 vctx
->base
.create_sampler_view
= virgl_create_sampler_view
;
1292 vctx
->base
.sampler_view_destroy
= virgl_destroy_sampler_view
;
1293 vctx
->base
.set_sampler_views
= virgl_set_sampler_views
;
1294 vctx
->base
.texture_barrier
= virgl_texture_barrier
;
1296 vctx
->base
.create_sampler_state
= virgl_create_sampler_state
;
1297 vctx
->base
.delete_sampler_state
= virgl_delete_sampler_state
;
1298 vctx
->base
.bind_sampler_states
= virgl_bind_sampler_states
;
1300 vctx
->base
.set_polygon_stipple
= virgl_set_polygon_stipple
;
1301 vctx
->base
.set_scissor_states
= virgl_set_scissor_states
;
1302 vctx
->base
.set_sample_mask
= virgl_set_sample_mask
;
1303 vctx
->base
.set_min_samples
= virgl_set_min_samples
;
1304 vctx
->base
.set_stencil_ref
= virgl_set_stencil_ref
;
1305 vctx
->base
.set_clip_state
= virgl_set_clip_state
;
1307 vctx
->base
.set_blend_color
= virgl_set_blend_color
;
1309 vctx
->base
.get_sample_position
= virgl_get_sample_position
;
1311 vctx
->base
.resource_copy_region
= virgl_resource_copy_region
;
1312 vctx
->base
.flush_resource
= virgl_flush_resource
;
1313 vctx
->base
.blit
= virgl_blit
;
1314 vctx
->base
.create_fence_fd
= virgl_create_fence_fd
;
1315 vctx
->base
.fence_server_sync
= virgl_fence_server_sync
;
1317 vctx
->base
.set_shader_buffers
= virgl_set_shader_buffers
;
1318 vctx
->base
.set_hw_atomic_buffers
= virgl_set_hw_atomic_buffers
;
1319 vctx
->base
.set_shader_images
= virgl_set_shader_images
;
1320 vctx
->base
.memory_barrier
= virgl_memory_barrier
;
1322 virgl_init_context_resource_functions(&vctx
->base
);
1323 virgl_init_query_functions(vctx
);
1324 virgl_init_so_functions(vctx
);
1326 slab_create_child(&vctx
->transfer_pool
, &rs
->transfer_pool
);
1328 vctx
->primconvert
= util_primconvert_create(&vctx
->base
, rs
->caps
.caps
.v1
.prim_mask
);
1329 vctx
->uploader
= u_upload_create(&vctx
->base
, 1024 * 1024,
1330 PIPE_BIND_INDEX_BUFFER
, PIPE_USAGE_STREAM
, 0);
1331 if (!vctx
->uploader
)
1333 vctx
->base
.stream_uploader
= vctx
->uploader
;
1334 vctx
->base
.const_uploader
= vctx
->uploader
;
1336 vctx
->hw_sub_ctx_id
= rs
->sub_ctx_id
++;
1337 virgl_encoder_create_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1339 virgl_encoder_set_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1341 if (rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_GUEST_MAY_INIT_LOG
) {
1342 host_debug_flagstring
= getenv("VIRGL_HOST_DEBUG");
1343 if (host_debug_flagstring
)
1344 virgl_encode_host_debug_flagstring(vctx
, host_debug_flagstring
);