2 * Copyright 2014, 2015 Red Hat.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_shader_tokens.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31 #include "util/u_inlines.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_prim.h"
35 #include "util/u_transfer.h"
36 #include "util/u_helpers.h"
37 #include "util/slab.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_blitter.h"
40 #include "tgsi/tgsi_text.h"
41 #include "indices/u_primconvert.h"
43 #include "pipebuffer/pb_buffer.h"
45 #include "virgl_encode.h"
46 #include "virgl_context.h"
47 #include "virgl_protocol.h"
48 #include "virgl_resource.h"
49 #include "virgl_screen.h"
51 struct virgl_vertex_elements_state
{
53 uint8_t binding_map
[PIPE_MAX_ATTRIBS
];
57 static uint32_t next_handle
;
58 uint32_t virgl_object_assign_handle(void)
63 static void virgl_attach_res_framebuffer(struct virgl_context
*vctx
)
65 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
66 struct pipe_surface
*surf
;
67 struct virgl_resource
*res
;
70 surf
= vctx
->framebuffer
.zsbuf
;
72 res
= virgl_resource(surf
->texture
);
74 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
76 for (i
= 0; i
< vctx
->framebuffer
.nr_cbufs
; i
++) {
77 surf
= vctx
->framebuffer
.cbufs
[i
];
79 res
= virgl_resource(surf
->texture
);
81 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
86 static void virgl_attach_res_sampler_views(struct virgl_context
*vctx
,
87 enum pipe_shader_type shader_type
)
89 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
90 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
91 struct virgl_resource
*res
;
92 uint32_t remaining_mask
= tinfo
->enabled_mask
;
94 while (remaining_mask
) {
95 i
= u_bit_scan(&remaining_mask
);
96 assert(tinfo
->views
[i
]);
98 res
= virgl_resource(tinfo
->views
[i
]->base
.texture
);
100 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
104 static void virgl_attach_res_vertex_buffers(struct virgl_context
*vctx
)
106 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
107 struct virgl_resource
*res
;
110 for (i
= 0; i
< vctx
->num_vertex_buffers
; i
++) {
111 res
= virgl_resource(vctx
->vertex_buffer
[i
].buffer
.resource
);
113 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
117 static void virgl_attach_res_index_buffer(struct virgl_context
*vctx
,
118 struct virgl_indexbuf
*ib
)
120 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
121 struct virgl_resource
*res
;
123 res
= virgl_resource(ib
->buffer
);
125 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
128 static void virgl_attach_res_so_targets(struct virgl_context
*vctx
)
130 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
131 struct virgl_resource
*res
;
134 for (i
= 0; i
< vctx
->num_so_targets
; i
++) {
135 res
= virgl_resource(vctx
->so_targets
[i
].base
.buffer
);
137 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
141 static void virgl_attach_res_uniform_buffers(struct virgl_context
*vctx
,
142 enum pipe_shader_type shader_type
)
144 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
145 struct virgl_resource
*res
;
147 for (i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
148 res
= virgl_resource(vctx
->ubos
[shader_type
][i
]);
150 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
155 static void virgl_attach_res_shader_buffers(struct virgl_context
*vctx
,
156 enum pipe_shader_type shader_type
)
158 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
159 struct virgl_resource
*res
;
161 for (i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
162 res
= virgl_resource(vctx
->ssbos
[shader_type
][i
]);
164 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
169 static void virgl_attach_res_shader_images(struct virgl_context
*vctx
,
170 enum pipe_shader_type shader_type
)
172 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
173 struct virgl_resource
*res
;
175 for (i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
176 res
= virgl_resource(vctx
->images
[shader_type
][i
]);
178 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
183 static void virgl_attach_res_atomic_buffers(struct virgl_context
*vctx
)
185 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
186 struct virgl_resource
*res
;
188 for (i
= 0; i
< PIPE_MAX_HW_ATOMIC_BUFFERS
; i
++) {
189 res
= virgl_resource(vctx
->atomic_buffers
[i
]);
191 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
197 * after flushing, the hw context still has a bunch of
198 * resources bound, so we need to rebind those here.
200 static void virgl_reemit_res(struct virgl_context
*vctx
)
202 enum pipe_shader_type shader_type
;
204 /* reattach any flushed resources */
205 /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
206 virgl_attach_res_framebuffer(vctx
);
208 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
209 virgl_attach_res_sampler_views(vctx
, shader_type
);
210 virgl_attach_res_uniform_buffers(vctx
, shader_type
);
211 virgl_attach_res_shader_buffers(vctx
, shader_type
);
212 virgl_attach_res_shader_images(vctx
, shader_type
);
214 virgl_attach_res_atomic_buffers(vctx
);
215 virgl_attach_res_vertex_buffers(vctx
);
216 virgl_attach_res_so_targets(vctx
);
219 static struct pipe_surface
*virgl_create_surface(struct pipe_context
*ctx
,
220 struct pipe_resource
*resource
,
221 const struct pipe_surface
*templ
)
223 struct virgl_context
*vctx
= virgl_context(ctx
);
224 struct virgl_surface
*surf
;
225 struct virgl_resource
*res
= virgl_resource(resource
);
228 surf
= CALLOC_STRUCT(virgl_surface
);
233 handle
= virgl_object_assign_handle();
234 pipe_reference_init(&surf
->base
.reference
, 1);
235 pipe_resource_reference(&surf
->base
.texture
, resource
);
236 surf
->base
.context
= ctx
;
237 surf
->base
.format
= templ
->format
;
238 if (resource
->target
!= PIPE_BUFFER
) {
239 surf
->base
.width
= u_minify(resource
->width0
, templ
->u
.tex
.level
);
240 surf
->base
.height
= u_minify(resource
->height0
, templ
->u
.tex
.level
);
241 surf
->base
.u
.tex
.level
= templ
->u
.tex
.level
;
242 surf
->base
.u
.tex
.first_layer
= templ
->u
.tex
.first_layer
;
243 surf
->base
.u
.tex
.last_layer
= templ
->u
.tex
.last_layer
;
245 surf
->base
.width
= templ
->u
.buf
.last_element
- templ
->u
.buf
.first_element
+ 1;
246 surf
->base
.height
= resource
->height0
;
247 surf
->base
.u
.buf
.first_element
= templ
->u
.buf
.first_element
;
248 surf
->base
.u
.buf
.last_element
= templ
->u
.buf
.last_element
;
250 virgl_encoder_create_surface(vctx
, handle
, res
, &surf
->base
);
251 surf
->handle
= handle
;
255 static void virgl_surface_destroy(struct pipe_context
*ctx
,
256 struct pipe_surface
*psurf
)
258 struct virgl_context
*vctx
= virgl_context(ctx
);
259 struct virgl_surface
*surf
= virgl_surface(psurf
);
261 pipe_resource_reference(&surf
->base
.texture
, NULL
);
262 virgl_encode_delete_object(vctx
, surf
->handle
, VIRGL_OBJECT_SURFACE
);
266 static void *virgl_create_blend_state(struct pipe_context
*ctx
,
267 const struct pipe_blend_state
*blend_state
)
269 struct virgl_context
*vctx
= virgl_context(ctx
);
271 handle
= virgl_object_assign_handle();
273 virgl_encode_blend_state(vctx
, handle
, blend_state
);
274 return (void *)(unsigned long)handle
;
278 static void virgl_bind_blend_state(struct pipe_context
*ctx
,
281 struct virgl_context
*vctx
= virgl_context(ctx
);
282 uint32_t handle
= (unsigned long)blend_state
;
283 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
286 static void virgl_delete_blend_state(struct pipe_context
*ctx
,
289 struct virgl_context
*vctx
= virgl_context(ctx
);
290 uint32_t handle
= (unsigned long)blend_state
;
291 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
294 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context
*ctx
,
295 const struct pipe_depth_stencil_alpha_state
*blend_state
)
297 struct virgl_context
*vctx
= virgl_context(ctx
);
299 handle
= virgl_object_assign_handle();
301 virgl_encode_dsa_state(vctx
, handle
, blend_state
);
302 return (void *)(unsigned long)handle
;
305 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context
*ctx
,
308 struct virgl_context
*vctx
= virgl_context(ctx
);
309 uint32_t handle
= (unsigned long)blend_state
;
310 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
313 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context
*ctx
,
316 struct virgl_context
*vctx
= virgl_context(ctx
);
317 uint32_t handle
= (unsigned long)dsa_state
;
318 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
321 static void *virgl_create_rasterizer_state(struct pipe_context
*ctx
,
322 const struct pipe_rasterizer_state
*rs_state
)
324 struct virgl_context
*vctx
= virgl_context(ctx
);
326 handle
= virgl_object_assign_handle();
328 virgl_encode_rasterizer_state(vctx
, handle
, rs_state
);
329 return (void *)(unsigned long)handle
;
332 static void virgl_bind_rasterizer_state(struct pipe_context
*ctx
,
335 struct virgl_context
*vctx
= virgl_context(ctx
);
336 uint32_t handle
= (unsigned long)rs_state
;
338 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
341 static void virgl_delete_rasterizer_state(struct pipe_context
*ctx
,
344 struct virgl_context
*vctx
= virgl_context(ctx
);
345 uint32_t handle
= (unsigned long)rs_state
;
346 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
349 static void virgl_set_framebuffer_state(struct pipe_context
*ctx
,
350 const struct pipe_framebuffer_state
*state
)
352 struct virgl_context
*vctx
= virgl_context(ctx
);
354 vctx
->framebuffer
= *state
;
355 virgl_encoder_set_framebuffer_state(vctx
, state
);
356 virgl_attach_res_framebuffer(vctx
);
359 static void virgl_set_viewport_states(struct pipe_context
*ctx
,
361 unsigned num_viewports
,
362 const struct pipe_viewport_state
*state
)
364 struct virgl_context
*vctx
= virgl_context(ctx
);
365 virgl_encoder_set_viewport_states(vctx
, start_slot
, num_viewports
, state
);
368 static void *virgl_create_vertex_elements_state(struct pipe_context
*ctx
,
369 unsigned num_elements
,
370 const struct pipe_vertex_element
*elements
)
372 struct pipe_vertex_element new_elements
[PIPE_MAX_ATTRIBS
];
373 struct virgl_context
*vctx
= virgl_context(ctx
);
374 struct virgl_vertex_elements_state
*state
=
375 CALLOC_STRUCT(virgl_vertex_elements_state
);
377 for (int i
= 0; i
< num_elements
; ++i
) {
378 if (elements
[i
].instance_divisor
) {
379 /* Virglrenderer doesn't deal with instance_divisor correctly if
380 * there isn't a 1:1 relationship between elements and bindings.
381 * So let's make sure there is, by duplicating bindings.
383 for (int j
= 0; j
< num_elements
; ++j
) {
384 new_elements
[j
] = elements
[j
];
385 new_elements
[j
].vertex_buffer_index
= j
;
386 state
->binding_map
[j
] = elements
[j
].vertex_buffer_index
;
388 elements
= new_elements
;
389 state
->num_bindings
= num_elements
;
394 state
->handle
= virgl_object_assign_handle();
395 virgl_encoder_create_vertex_elements(vctx
, state
->handle
,
396 num_elements
, elements
);
400 static void virgl_delete_vertex_elements_state(struct pipe_context
*ctx
,
403 struct virgl_context
*vctx
= virgl_context(ctx
);
404 struct virgl_vertex_elements_state
*state
=
405 (struct virgl_vertex_elements_state
*)ve
;
406 virgl_encode_delete_object(vctx
, state
->handle
, VIRGL_OBJECT_VERTEX_ELEMENTS
);
410 static void virgl_bind_vertex_elements_state(struct pipe_context
*ctx
,
413 struct virgl_context
*vctx
= virgl_context(ctx
);
414 struct virgl_vertex_elements_state
*state
=
415 (struct virgl_vertex_elements_state
*)ve
;
416 vctx
->vertex_elements
= state
;
417 virgl_encode_bind_object(vctx
, state
? state
->handle
: 0,
418 VIRGL_OBJECT_VERTEX_ELEMENTS
);
419 vctx
->vertex_array_dirty
= TRUE
;
422 static void virgl_set_vertex_buffers(struct pipe_context
*ctx
,
424 unsigned num_buffers
,
425 const struct pipe_vertex_buffer
*buffers
)
427 struct virgl_context
*vctx
= virgl_context(ctx
);
429 util_set_vertex_buffers_count(vctx
->vertex_buffer
,
430 &vctx
->num_vertex_buffers
,
431 buffers
, start_slot
, num_buffers
);
433 vctx
->vertex_array_dirty
= TRUE
;
436 static void virgl_hw_set_vertex_buffers(struct virgl_context
*vctx
)
438 if (vctx
->vertex_array_dirty
) {
439 struct virgl_vertex_elements_state
*ve
= vctx
->vertex_elements
;
441 if (ve
->num_bindings
) {
442 struct pipe_vertex_buffer vertex_buffers
[PIPE_MAX_ATTRIBS
];
443 for (int i
= 0; i
< ve
->num_bindings
; ++i
)
444 vertex_buffers
[i
] = vctx
->vertex_buffer
[ve
->binding_map
[i
]];
446 virgl_encoder_set_vertex_buffers(vctx
, ve
->num_bindings
, vertex_buffers
);
448 virgl_encoder_set_vertex_buffers(vctx
, vctx
->num_vertex_buffers
, vctx
->vertex_buffer
);
450 virgl_attach_res_vertex_buffers(vctx
);
454 static void virgl_set_stencil_ref(struct pipe_context
*ctx
,
455 const struct pipe_stencil_ref
*ref
)
457 struct virgl_context
*vctx
= virgl_context(ctx
);
458 virgl_encoder_set_stencil_ref(vctx
, ref
);
461 static void virgl_set_blend_color(struct pipe_context
*ctx
,
462 const struct pipe_blend_color
*color
)
464 struct virgl_context
*vctx
= virgl_context(ctx
);
465 virgl_encoder_set_blend_color(vctx
, color
);
468 static void virgl_hw_set_index_buffer(struct virgl_context
*vctx
,
469 struct virgl_indexbuf
*ib
)
471 virgl_encoder_set_index_buffer(vctx
, ib
);
472 virgl_attach_res_index_buffer(vctx
, ib
);
475 static void virgl_set_constant_buffer(struct pipe_context
*ctx
,
476 enum pipe_shader_type shader
, uint index
,
477 const struct pipe_constant_buffer
*buf
)
479 struct virgl_context
*vctx
= virgl_context(ctx
);
482 if (!buf
->user_buffer
){
483 struct virgl_resource
*res
= virgl_resource(buf
->buffer
);
484 virgl_encoder_set_uniform_buffer(vctx
, shader
, index
, buf
->buffer_offset
,
485 buf
->buffer_size
, res
);
486 pipe_resource_reference(&vctx
->ubos
[shader
][index
], buf
->buffer
);
489 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
490 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, buf
->buffer_size
/ 4, buf
->user_buffer
);
492 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, 0, NULL
);
493 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
497 void virgl_transfer_inline_write(struct pipe_context
*ctx
,
498 struct pipe_resource
*res
,
501 const struct pipe_box
*box
,
504 unsigned layer_stride
)
506 struct virgl_context
*vctx
= virgl_context(ctx
);
507 struct virgl_screen
*vs
= virgl_screen(ctx
->screen
);
508 struct virgl_resource
*grres
= virgl_resource(res
);
509 struct virgl_buffer
*vbuf
= virgl_buffer(res
);
511 grres
->clean
= FALSE
;
513 if (virgl_res_needs_flush_wait(vctx
, &vbuf
->base
, usage
)) {
514 ctx
->flush(ctx
, NULL
, 0);
516 vs
->vws
->resource_wait(vs
->vws
, vbuf
->base
.hw_res
);
519 virgl_encoder_inline_write(vctx
, grres
, level
, usage
,
520 box
, data
, stride
, layer_stride
);
523 static void *virgl_shader_encoder(struct pipe_context
*ctx
,
524 const struct pipe_shader_state
*shader
,
527 struct virgl_context
*vctx
= virgl_context(ctx
);
529 struct tgsi_token
*new_tokens
;
532 new_tokens
= virgl_tgsi_transform(vctx
, shader
->tokens
);
536 handle
= virgl_object_assign_handle();
537 /* encode VS state */
538 ret
= virgl_encode_shader_state(vctx
, handle
, type
,
539 &shader
->stream_output
, 0,
546 return (void *)(unsigned long)handle
;
549 static void *virgl_create_vs_state(struct pipe_context
*ctx
,
550 const struct pipe_shader_state
*shader
)
552 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_VERTEX
);
555 static void *virgl_create_tcs_state(struct pipe_context
*ctx
,
556 const struct pipe_shader_state
*shader
)
558 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_CTRL
);
561 static void *virgl_create_tes_state(struct pipe_context
*ctx
,
562 const struct pipe_shader_state
*shader
)
564 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_EVAL
);
567 static void *virgl_create_gs_state(struct pipe_context
*ctx
,
568 const struct pipe_shader_state
*shader
)
570 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_GEOMETRY
);
573 static void *virgl_create_fs_state(struct pipe_context
*ctx
,
574 const struct pipe_shader_state
*shader
)
576 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_FRAGMENT
);
580 virgl_delete_fs_state(struct pipe_context
*ctx
,
583 uint32_t handle
= (unsigned long)fs
;
584 struct virgl_context
*vctx
= virgl_context(ctx
);
586 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
590 virgl_delete_gs_state(struct pipe_context
*ctx
,
593 uint32_t handle
= (unsigned long)gs
;
594 struct virgl_context
*vctx
= virgl_context(ctx
);
596 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
600 virgl_delete_vs_state(struct pipe_context
*ctx
,
603 uint32_t handle
= (unsigned long)vs
;
604 struct virgl_context
*vctx
= virgl_context(ctx
);
606 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
610 virgl_delete_tcs_state(struct pipe_context
*ctx
,
613 uint32_t handle
= (unsigned long)tcs
;
614 struct virgl_context
*vctx
= virgl_context(ctx
);
616 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
620 virgl_delete_tes_state(struct pipe_context
*ctx
,
623 uint32_t handle
= (unsigned long)tes
;
624 struct virgl_context
*vctx
= virgl_context(ctx
);
626 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
629 static void virgl_bind_vs_state(struct pipe_context
*ctx
,
632 uint32_t handle
= (unsigned long)vss
;
633 struct virgl_context
*vctx
= virgl_context(ctx
);
635 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_VERTEX
);
638 static void virgl_bind_tcs_state(struct pipe_context
*ctx
,
641 uint32_t handle
= (unsigned long)vss
;
642 struct virgl_context
*vctx
= virgl_context(ctx
);
644 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_CTRL
);
647 static void virgl_bind_tes_state(struct pipe_context
*ctx
,
650 uint32_t handle
= (unsigned long)vss
;
651 struct virgl_context
*vctx
= virgl_context(ctx
);
653 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_EVAL
);
656 static void virgl_bind_gs_state(struct pipe_context
*ctx
,
659 uint32_t handle
= (unsigned long)vss
;
660 struct virgl_context
*vctx
= virgl_context(ctx
);
662 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_GEOMETRY
);
666 static void virgl_bind_fs_state(struct pipe_context
*ctx
,
669 uint32_t handle
= (unsigned long)vss
;
670 struct virgl_context
*vctx
= virgl_context(ctx
);
672 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_FRAGMENT
);
675 static void virgl_clear(struct pipe_context
*ctx
,
677 const union pipe_color_union
*color
,
678 double depth
, unsigned stencil
)
680 struct virgl_context
*vctx
= virgl_context(ctx
);
682 virgl_encode_clear(vctx
, buffers
, color
, depth
, stencil
);
685 static void virgl_draw_vbo(struct pipe_context
*ctx
,
686 const struct pipe_draw_info
*dinfo
)
688 struct virgl_context
*vctx
= virgl_context(ctx
);
689 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
690 struct virgl_indexbuf ib
= {};
691 struct pipe_draw_info info
= *dinfo
;
693 if (!dinfo
->count_from_stream_output
&& !dinfo
->indirect
&&
694 !dinfo
->primitive_restart
&&
695 !u_trim_pipe_prim(dinfo
->mode
, (unsigned*)&dinfo
->count
))
698 if (!(rs
->caps
.caps
.v1
.prim_mask
& (1 << dinfo
->mode
))) {
699 util_primconvert_draw_vbo(vctx
->primconvert
, dinfo
);
702 if (info
.index_size
) {
703 pipe_resource_reference(&ib
.buffer
, info
.has_user_indices
? NULL
: info
.index
.resource
);
704 ib
.user_buffer
= info
.has_user_indices
? info
.index
.user
: NULL
;
705 ib
.index_size
= dinfo
->index_size
;
706 ib
.offset
= info
.start
* ib
.index_size
;
708 if (ib
.user_buffer
) {
709 u_upload_data(vctx
->uploader
, 0, info
.count
* ib
.index_size
, 256,
710 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
711 ib
.user_buffer
= NULL
;
715 u_upload_unmap(vctx
->uploader
);
718 virgl_hw_set_vertex_buffers(vctx
);
720 virgl_hw_set_index_buffer(vctx
, &ib
);
722 virgl_encoder_draw_vbo(vctx
, &info
);
724 pipe_resource_reference(&ib
.buffer
, NULL
);
728 static void virgl_flush_eq(struct virgl_context
*ctx
, void *closure
,
729 struct pipe_fence_handle
**fence
)
731 struct virgl_screen
*rs
= virgl_screen(ctx
->base
.screen
);
732 int out_fence_fd
= -1;
734 /* send the buffer to the remote side for decoding */
735 ctx
->num_transfers
= ctx
->num_draws
= 0;
737 rs
->vws
->submit_cmd(rs
->vws
, ctx
->cbuf
, ctx
->cbuf
->in_fence_fd
,
738 ctx
->cbuf
->needs_out_fence_fd
? &out_fence_fd
: NULL
);
741 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, out_fence_fd
);
743 virgl_encoder_set_sub_ctx(ctx
, ctx
->hw_sub_ctx_id
);
745 /* add back current framebuffer resources to reference list? */
746 virgl_reemit_res(ctx
);
749 static void virgl_flush_from_st(struct pipe_context
*ctx
,
750 struct pipe_fence_handle
**fence
,
751 enum pipe_flush_flags flags
)
753 struct virgl_context
*vctx
= virgl_context(ctx
);
754 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
756 if (flags
& PIPE_FLUSH_FENCE_FD
)
757 vctx
->cbuf
->needs_out_fence_fd
= true;
759 virgl_flush_eq(vctx
, vctx
, fence
);
761 if (vctx
->cbuf
->in_fence_fd
!= -1) {
762 close(vctx
->cbuf
->in_fence_fd
);
763 vctx
->cbuf
->in_fence_fd
= -1;
765 vctx
->cbuf
->needs_out_fence_fd
= false;
768 static struct pipe_sampler_view
*virgl_create_sampler_view(struct pipe_context
*ctx
,
769 struct pipe_resource
*texture
,
770 const struct pipe_sampler_view
*state
)
772 struct virgl_context
*vctx
= virgl_context(ctx
);
773 struct virgl_sampler_view
*grview
;
775 struct virgl_resource
*res
;
780 grview
= CALLOC_STRUCT(virgl_sampler_view
);
784 res
= virgl_resource(texture
);
785 handle
= virgl_object_assign_handle();
786 virgl_encode_sampler_view(vctx
, handle
, res
, state
);
788 grview
->base
= *state
;
789 grview
->base
.reference
.count
= 1;
791 grview
->base
.texture
= NULL
;
792 grview
->base
.context
= ctx
;
793 pipe_resource_reference(&grview
->base
.texture
, texture
);
794 grview
->handle
= handle
;
795 return &grview
->base
;
798 static void virgl_set_sampler_views(struct pipe_context
*ctx
,
799 enum pipe_shader_type shader_type
,
802 struct pipe_sampler_view
**views
)
804 struct virgl_context
*vctx
= virgl_context(ctx
);
806 uint32_t disable_mask
= ~((1ull << num_views
) - 1);
807 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
808 uint32_t new_mask
= 0;
809 uint32_t remaining_mask
;
811 remaining_mask
= tinfo
->enabled_mask
& disable_mask
;
813 while (remaining_mask
) {
814 i
= u_bit_scan(&remaining_mask
);
815 assert(tinfo
->views
[i
]);
817 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
820 for (i
= 0; i
< num_views
; i
++) {
821 struct virgl_sampler_view
*grview
= virgl_sampler_view(views
[i
]);
823 if (views
[i
] == (struct pipe_sampler_view
*)tinfo
->views
[i
])
828 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], views
[i
]);
830 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
831 disable_mask
|= 1 << i
;
835 tinfo
->enabled_mask
&= ~disable_mask
;
836 tinfo
->enabled_mask
|= new_mask
;
837 virgl_encode_set_sampler_views(vctx
, shader_type
, start_slot
, num_views
, tinfo
->views
);
838 virgl_attach_res_sampler_views(vctx
, shader_type
);
842 virgl_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
844 struct virgl_context
*vctx
= virgl_context(ctx
);
845 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
847 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_BARRIER
))
849 virgl_encode_texture_barrier(vctx
, flags
);
852 static void virgl_destroy_sampler_view(struct pipe_context
*ctx
,
853 struct pipe_sampler_view
*view
)
855 struct virgl_context
*vctx
= virgl_context(ctx
);
856 struct virgl_sampler_view
*grview
= virgl_sampler_view(view
);
858 virgl_encode_delete_object(vctx
, grview
->handle
, VIRGL_OBJECT_SAMPLER_VIEW
);
859 pipe_resource_reference(&view
->texture
, NULL
);
863 static void *virgl_create_sampler_state(struct pipe_context
*ctx
,
864 const struct pipe_sampler_state
*state
)
866 struct virgl_context
*vctx
= virgl_context(ctx
);
869 handle
= virgl_object_assign_handle();
871 virgl_encode_sampler_state(vctx
, handle
, state
);
872 return (void *)(unsigned long)handle
;
875 static void virgl_delete_sampler_state(struct pipe_context
*ctx
,
878 struct virgl_context
*vctx
= virgl_context(ctx
);
879 uint32_t handle
= (unsigned long)ss
;
881 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SAMPLER_STATE
);
884 static void virgl_bind_sampler_states(struct pipe_context
*ctx
,
885 enum pipe_shader_type shader
,
887 unsigned num_samplers
,
890 struct virgl_context
*vctx
= virgl_context(ctx
);
891 uint32_t handles
[32];
893 for (i
= 0; i
< num_samplers
; i
++) {
894 handles
[i
] = (unsigned long)(samplers
[i
]);
896 virgl_encode_bind_sampler_states(vctx
, shader
, start_slot
, num_samplers
, handles
);
899 static void virgl_set_polygon_stipple(struct pipe_context
*ctx
,
900 const struct pipe_poly_stipple
*ps
)
902 struct virgl_context
*vctx
= virgl_context(ctx
);
903 virgl_encoder_set_polygon_stipple(vctx
, ps
);
906 static void virgl_set_scissor_states(struct pipe_context
*ctx
,
908 unsigned num_scissor
,
909 const struct pipe_scissor_state
*ss
)
911 struct virgl_context
*vctx
= virgl_context(ctx
);
912 virgl_encoder_set_scissor_state(vctx
, start_slot
, num_scissor
, ss
);
915 static void virgl_set_sample_mask(struct pipe_context
*ctx
,
916 unsigned sample_mask
)
918 struct virgl_context
*vctx
= virgl_context(ctx
);
919 virgl_encoder_set_sample_mask(vctx
, sample_mask
);
922 static void virgl_set_min_samples(struct pipe_context
*ctx
,
923 unsigned min_samples
)
925 struct virgl_context
*vctx
= virgl_context(ctx
);
926 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
928 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SET_MIN_SAMPLES
))
930 virgl_encoder_set_min_samples(vctx
, min_samples
);
933 static void virgl_set_clip_state(struct pipe_context
*ctx
,
934 const struct pipe_clip_state
*clip
)
936 struct virgl_context
*vctx
= virgl_context(ctx
);
937 virgl_encoder_set_clip_state(vctx
, clip
);
940 static void virgl_set_tess_state(struct pipe_context
*ctx
,
941 const float default_outer_level
[4],
942 const float default_inner_level
[2])
944 struct virgl_context
*vctx
= virgl_context(ctx
);
945 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
947 if (!rs
->caps
.caps
.v1
.bset
.has_tessellation_shaders
)
949 virgl_encode_set_tess_state(vctx
, default_outer_level
, default_inner_level
);
952 static void virgl_resource_copy_region(struct pipe_context
*ctx
,
953 struct pipe_resource
*dst
,
955 unsigned dstx
, unsigned dsty
, unsigned dstz
,
956 struct pipe_resource
*src
,
958 const struct pipe_box
*src_box
)
960 struct virgl_context
*vctx
= virgl_context(ctx
);
961 struct virgl_resource
*dres
= virgl_resource(dst
);
962 struct virgl_resource
*sres
= virgl_resource(src
);
965 virgl_encode_resource_copy_region(vctx
, dres
,
966 dst_level
, dstx
, dsty
, dstz
,
972 virgl_flush_resource(struct pipe_context
*pipe
,
973 struct pipe_resource
*resource
)
977 static void virgl_blit(struct pipe_context
*ctx
,
978 const struct pipe_blit_info
*blit
)
980 struct virgl_context
*vctx
= virgl_context(ctx
);
981 struct virgl_resource
*dres
= virgl_resource(blit
->dst
.resource
);
982 struct virgl_resource
*sres
= virgl_resource(blit
->src
.resource
);
985 virgl_encode_blit(vctx
, dres
, sres
,
989 static void virgl_set_hw_atomic_buffers(struct pipe_context
*ctx
,
992 const struct pipe_shader_buffer
*buffers
)
994 struct virgl_context
*vctx
= virgl_context(ctx
);
996 for (unsigned i
= 0; i
< count
; i
++) {
997 unsigned idx
= start_slot
+ i
;
1000 if (buffers
[i
].buffer
) {
1001 pipe_resource_reference(&vctx
->atomic_buffers
[idx
],
1006 pipe_resource_reference(&vctx
->atomic_buffers
[idx
], NULL
);
1008 virgl_encode_set_hw_atomic_buffers(vctx
, start_slot
, count
, buffers
);
1011 static void virgl_set_shader_buffers(struct pipe_context
*ctx
,
1012 enum pipe_shader_type shader
,
1013 unsigned start_slot
, unsigned count
,
1014 const struct pipe_shader_buffer
*buffers
)
1016 struct virgl_context
*vctx
= virgl_context(ctx
);
1017 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1019 for (unsigned i
= 0; i
< count
; i
++) {
1020 unsigned idx
= start_slot
+ i
;
1023 if (buffers
[i
].buffer
) {
1024 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], buffers
[i
].buffer
);
1028 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], NULL
);
1031 uint32_t max_shader_buffer
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1032 rs
->caps
.caps
.v2
.max_shader_buffer_frag_compute
:
1033 rs
->caps
.caps
.v2
.max_shader_buffer_other_stages
;
1034 if (!max_shader_buffer
)
1036 virgl_encode_set_shader_buffers(vctx
, shader
, start_slot
, count
, buffers
);
1039 static void virgl_create_fence_fd(struct pipe_context
*ctx
,
1040 struct pipe_fence_handle
**fence
,
1042 enum pipe_fd_type type
)
1044 assert(type
== PIPE_FD_TYPE_NATIVE_SYNC
);
1045 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1047 if (rs
->vws
->cs_create_fence
)
1048 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, fd
);
1051 static void virgl_fence_server_sync(struct pipe_context
*ctx
,
1052 struct pipe_fence_handle
*fence
)
1054 struct virgl_context
*vctx
= virgl_context(ctx
);
1055 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1057 if (rs
->vws
->fence_server_sync
)
1058 rs
->vws
->fence_server_sync(rs
->vws
, vctx
->cbuf
, fence
);
1061 static void virgl_set_shader_images(struct pipe_context
*ctx
,
1062 enum pipe_shader_type shader
,
1063 unsigned start_slot
, unsigned count
,
1064 const struct pipe_image_view
*images
)
1066 struct virgl_context
*vctx
= virgl_context(ctx
);
1067 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1069 for (unsigned i
= 0; i
< count
; i
++) {
1070 unsigned idx
= start_slot
+ i
;
1073 if (images
[i
].resource
) {
1074 pipe_resource_reference(&vctx
->images
[shader
][idx
], images
[i
].resource
);
1078 pipe_resource_reference(&vctx
->images
[shader
][idx
], NULL
);
1081 uint32_t max_shader_images
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1082 rs
->caps
.caps
.v2
.max_shader_image_frag_compute
:
1083 rs
->caps
.caps
.v2
.max_shader_image_other_stages
;
1084 if (!max_shader_images
)
1086 virgl_encode_set_shader_images(vctx
, shader
, start_slot
, count
, images
);
1089 static void virgl_memory_barrier(struct pipe_context
*ctx
,
1092 struct virgl_context
*vctx
= virgl_context(ctx
);
1093 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1095 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_MEMORY_BARRIER
))
1097 virgl_encode_memory_barrier(vctx
, flags
);
1100 static void *virgl_create_compute_state(struct pipe_context
*ctx
,
1101 const struct pipe_compute_state
*state
)
1103 struct virgl_context
*vctx
= virgl_context(ctx
);
1105 const struct tgsi_token
*new_tokens
= state
->prog
;
1106 struct pipe_stream_output_info so_info
= {};
1109 handle
= virgl_object_assign_handle();
1110 ret
= virgl_encode_shader_state(vctx
, handle
, PIPE_SHADER_COMPUTE
,
1112 state
->req_local_mem
,
1118 return (void *)(unsigned long)handle
;
1121 static void virgl_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1123 uint32_t handle
= (unsigned long)state
;
1124 struct virgl_context
*vctx
= virgl_context(ctx
);
1126 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_COMPUTE
);
1129 static void virgl_delete_compute_state(struct pipe_context
*ctx
, void *state
)
1131 uint32_t handle
= (unsigned long)state
;
1132 struct virgl_context
*vctx
= virgl_context(ctx
);
1134 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
1137 static void virgl_launch_grid(struct pipe_context
*ctx
,
1138 const struct pipe_grid_info
*info
)
1140 struct virgl_context
*vctx
= virgl_context(ctx
);
1141 virgl_encode_launch_grid(vctx
, info
);
1145 virgl_context_destroy( struct pipe_context
*ctx
)
1147 struct virgl_context
*vctx
= virgl_context(ctx
);
1148 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1150 vctx
->framebuffer
.zsbuf
= NULL
;
1151 vctx
->framebuffer
.nr_cbufs
= 0;
1152 virgl_encoder_destroy_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1153 virgl_flush_eq(vctx
, vctx
, NULL
);
1155 rs
->vws
->cmd_buf_destroy(vctx
->cbuf
);
1157 u_upload_destroy(vctx
->uploader
);
1158 util_primconvert_destroy(vctx
->primconvert
);
1160 slab_destroy_child(&vctx
->transfer_pool
);
1164 static void virgl_get_sample_position(struct pipe_context
*ctx
,
1165 unsigned sample_count
,
1169 struct virgl_context
*vctx
= virgl_context(ctx
);
1170 struct virgl_screen
*vs
= virgl_screen(vctx
->base
.screen
);
1172 if (sample_count
> vs
->caps
.caps
.v1
.max_samples
) {
1173 debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1174 sample_count
, vs
->caps
.caps
.v1
.max_samples
);
1178 /* The following is basically copied from dri/i965gen6_get_sample_position
1179 * The only addition is that we hold the msaa positions for all sample
1180 * counts in a flat array. */
1182 if (sample_count
== 1) {
1183 out_value
[0] = out_value
[1] = 0.5f
;
1185 } else if (sample_count
== 2) {
1186 bits
= vs
->caps
.caps
.v2
.sample_locations
[0] >> (8 * index
);
1187 } else if (sample_count
<= 4) {
1188 bits
= vs
->caps
.caps
.v2
.sample_locations
[1] >> (8 * index
);
1189 } else if (sample_count
<= 8) {
1190 bits
= vs
->caps
.caps
.v2
.sample_locations
[2 + (index
>> 2)] >> (8 * (index
& 3));
1191 } else if (sample_count
<= 16) {
1192 bits
= vs
->caps
.caps
.v2
.sample_locations
[4 + (index
>> 2)] >> (8 * (index
& 3));
1194 out_value
[0] = ((bits
>> 4) & 0xf) / 16.0f
;
1195 out_value
[1] = (bits
& 0xf) / 16.0f
;
1197 if (virgl_debug
& VIRGL_DEBUG_VERBOSE
)
1198 debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1199 index
, sample_count
, out_value
[0], out_value
[1]);
1202 struct pipe_context
*virgl_context_create(struct pipe_screen
*pscreen
,
1206 struct virgl_context
*vctx
;
1207 struct virgl_screen
*rs
= virgl_screen(pscreen
);
1208 vctx
= CALLOC_STRUCT(virgl_context
);
1209 const char *host_debug_flagstring
;
1211 vctx
->cbuf
= rs
->vws
->cmd_buf_create(rs
->vws
);
1217 vctx
->base
.destroy
= virgl_context_destroy
;
1218 vctx
->base
.create_surface
= virgl_create_surface
;
1219 vctx
->base
.surface_destroy
= virgl_surface_destroy
;
1220 vctx
->base
.set_framebuffer_state
= virgl_set_framebuffer_state
;
1221 vctx
->base
.create_blend_state
= virgl_create_blend_state
;
1222 vctx
->base
.bind_blend_state
= virgl_bind_blend_state
;
1223 vctx
->base
.delete_blend_state
= virgl_delete_blend_state
;
1224 vctx
->base
.create_depth_stencil_alpha_state
= virgl_create_depth_stencil_alpha_state
;
1225 vctx
->base
.bind_depth_stencil_alpha_state
= virgl_bind_depth_stencil_alpha_state
;
1226 vctx
->base
.delete_depth_stencil_alpha_state
= virgl_delete_depth_stencil_alpha_state
;
1227 vctx
->base
.create_rasterizer_state
= virgl_create_rasterizer_state
;
1228 vctx
->base
.bind_rasterizer_state
= virgl_bind_rasterizer_state
;
1229 vctx
->base
.delete_rasterizer_state
= virgl_delete_rasterizer_state
;
1231 vctx
->base
.set_viewport_states
= virgl_set_viewport_states
;
1232 vctx
->base
.create_vertex_elements_state
= virgl_create_vertex_elements_state
;
1233 vctx
->base
.bind_vertex_elements_state
= virgl_bind_vertex_elements_state
;
1234 vctx
->base
.delete_vertex_elements_state
= virgl_delete_vertex_elements_state
;
1235 vctx
->base
.set_vertex_buffers
= virgl_set_vertex_buffers
;
1236 vctx
->base
.set_constant_buffer
= virgl_set_constant_buffer
;
1238 vctx
->base
.set_tess_state
= virgl_set_tess_state
;
1239 vctx
->base
.create_vs_state
= virgl_create_vs_state
;
1240 vctx
->base
.create_tcs_state
= virgl_create_tcs_state
;
1241 vctx
->base
.create_tes_state
= virgl_create_tes_state
;
1242 vctx
->base
.create_gs_state
= virgl_create_gs_state
;
1243 vctx
->base
.create_fs_state
= virgl_create_fs_state
;
1245 vctx
->base
.bind_vs_state
= virgl_bind_vs_state
;
1246 vctx
->base
.bind_tcs_state
= virgl_bind_tcs_state
;
1247 vctx
->base
.bind_tes_state
= virgl_bind_tes_state
;
1248 vctx
->base
.bind_gs_state
= virgl_bind_gs_state
;
1249 vctx
->base
.bind_fs_state
= virgl_bind_fs_state
;
1251 vctx
->base
.delete_vs_state
= virgl_delete_vs_state
;
1252 vctx
->base
.delete_tcs_state
= virgl_delete_tcs_state
;
1253 vctx
->base
.delete_tes_state
= virgl_delete_tes_state
;
1254 vctx
->base
.delete_gs_state
= virgl_delete_gs_state
;
1255 vctx
->base
.delete_fs_state
= virgl_delete_fs_state
;
1257 vctx
->base
.create_compute_state
= virgl_create_compute_state
;
1258 vctx
->base
.bind_compute_state
= virgl_bind_compute_state
;
1259 vctx
->base
.delete_compute_state
= virgl_delete_compute_state
;
1260 vctx
->base
.launch_grid
= virgl_launch_grid
;
1262 vctx
->base
.clear
= virgl_clear
;
1263 vctx
->base
.draw_vbo
= virgl_draw_vbo
;
1264 vctx
->base
.flush
= virgl_flush_from_st
;
1265 vctx
->base
.screen
= pscreen
;
1266 vctx
->base
.create_sampler_view
= virgl_create_sampler_view
;
1267 vctx
->base
.sampler_view_destroy
= virgl_destroy_sampler_view
;
1268 vctx
->base
.set_sampler_views
= virgl_set_sampler_views
;
1269 vctx
->base
.texture_barrier
= virgl_texture_barrier
;
1271 vctx
->base
.create_sampler_state
= virgl_create_sampler_state
;
1272 vctx
->base
.delete_sampler_state
= virgl_delete_sampler_state
;
1273 vctx
->base
.bind_sampler_states
= virgl_bind_sampler_states
;
1275 vctx
->base
.set_polygon_stipple
= virgl_set_polygon_stipple
;
1276 vctx
->base
.set_scissor_states
= virgl_set_scissor_states
;
1277 vctx
->base
.set_sample_mask
= virgl_set_sample_mask
;
1278 vctx
->base
.set_min_samples
= virgl_set_min_samples
;
1279 vctx
->base
.set_stencil_ref
= virgl_set_stencil_ref
;
1280 vctx
->base
.set_clip_state
= virgl_set_clip_state
;
1282 vctx
->base
.set_blend_color
= virgl_set_blend_color
;
1284 vctx
->base
.get_sample_position
= virgl_get_sample_position
;
1286 vctx
->base
.resource_copy_region
= virgl_resource_copy_region
;
1287 vctx
->base
.flush_resource
= virgl_flush_resource
;
1288 vctx
->base
.blit
= virgl_blit
;
1289 vctx
->base
.create_fence_fd
= virgl_create_fence_fd
;
1290 vctx
->base
.fence_server_sync
= virgl_fence_server_sync
;
1292 vctx
->base
.set_shader_buffers
= virgl_set_shader_buffers
;
1293 vctx
->base
.set_hw_atomic_buffers
= virgl_set_hw_atomic_buffers
;
1294 vctx
->base
.set_shader_images
= virgl_set_shader_images
;
1295 vctx
->base
.memory_barrier
= virgl_memory_barrier
;
1297 virgl_init_context_resource_functions(&vctx
->base
);
1298 virgl_init_query_functions(vctx
);
1299 virgl_init_so_functions(vctx
);
1301 slab_create_child(&vctx
->transfer_pool
, &rs
->transfer_pool
);
1303 vctx
->primconvert
= util_primconvert_create(&vctx
->base
, rs
->caps
.caps
.v1
.prim_mask
);
1304 vctx
->uploader
= u_upload_create(&vctx
->base
, 1024 * 1024,
1305 PIPE_BIND_INDEX_BUFFER
, PIPE_USAGE_STREAM
, 0);
1306 if (!vctx
->uploader
)
1308 vctx
->base
.stream_uploader
= vctx
->uploader
;
1309 vctx
->base
.const_uploader
= vctx
->uploader
;
1311 vctx
->hw_sub_ctx_id
= rs
->sub_ctx_id
++;
1312 virgl_encoder_create_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1314 virgl_encoder_set_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1316 if (rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_GUEST_MAY_INIT_LOG
) {
1317 host_debug_flagstring
= getenv("VIRGL_HOST_DEBUG");
1318 if (host_debug_flagstring
)
1319 virgl_encode_host_debug_flagstring(vctx
, host_debug_flagstring
);