src/gallium/drivers/virgl/virgl_context.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <libsync.h>
  25 #include "pipe/p_shader_tokens.h"
  26
  27 #include "pipe/p_context.h"
  28 #include "pipe/p_defines.h"
  29 #include "pipe/p_screen.h"
  30 #include "pipe/p_state.h"
  31 #include "util/u_inlines.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_format.h"
  34 #include "util/u_prim.h"
  35 #include "util/u_transfer.h"
  36 #include "util/u_helpers.h"
  37 #include "util/slab.h"
  38 #include "util/u_upload_mgr.h"
  39 #include "util/u_blitter.h"
  40 #include "tgsi/tgsi_text.h"
  41 #include "indices/u_primconvert.h"
  42
  43 #include "pipebuffer/pb_buffer.h"
  44
  45 #include "virgl_encode.h"
  46 #include "virgl_context.h"
  47 #include "virgl_protocol.h"
  48 #include "virgl_resource.h"
  49 #include "virgl_screen.h"
  50
  51 struct virgl_vertex_elements_state {
  52    uint32_t handle;
  53    uint8_t binding_map[PIPE_MAX_ATTRIBS];
  54    uint8_t num_bindings;
  55 };
  56
  57 static uint32_t next_handle;
  58 uint32_t virgl_object_assign_handle(void)
  59 {
  60    return ++next_handle;
  61 }
  62
  63 static void virgl_attach_res_framebuffer(struct virgl_context *vctx)
  64 {
  65    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
  66    struct pipe_surface *surf;
  67    struct virgl_resource *res;
  68    unsigned i;
  69
  70    surf = vctx->framebuffer.zsbuf;
  71    if (surf) {
  72       res = virgl_resource(surf->texture);
  73       if (res) {
  74          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
  75          virgl_resource_dirty(res, surf->u.tex.level);
  76       }
  77    }
  78    for (i = 0; i < vctx->framebuffer.nr_cbufs; i++) {
  79       surf = vctx->framebuffer.cbufs[i];
  80       if (surf) {
  81          res = virgl_resource(surf->texture);
  82          if (res) {
  83             vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
  84             virgl_resource_dirty(res, surf->u.tex.level);
  85          }
  86       }
  87    }
  88 }
  89
  90 static void virgl_attach_res_sampler_views(struct virgl_context *vctx,
  91                                            enum pipe_shader_type shader_type)
  92 {
  93    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
  94    struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
  95    struct virgl_resource *res;
  96    uint32_t remaining_mask = tinfo->enabled_mask;
  97    unsigned i;
  98    while (remaining_mask) {
  99       i = u_bit_scan(&remaining_mask);
 100       assert(tinfo->views[i]);
 101
 102       res = virgl_resource(tinfo->views[i]->base.texture);
 103       if (res)
 104          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 105    }
 106 }
 107
 108 static void virgl_attach_res_vertex_buffers(struct virgl_context *vctx)
 109 {
 110    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 111    struct virgl_resource *res;
 112    unsigned i;
 113
 114    for (i = 0; i < vctx->num_vertex_buffers; i++) {
 115       res = virgl_resource(vctx->vertex_buffer[i].buffer.resource);
 116       if (res)
 117          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 118    }
 119 }
 120
 121 static void virgl_attach_res_index_buffer(struct virgl_context *vctx,
 122                                           struct virgl_indexbuf *ib)
 123 {
 124    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 125    struct virgl_resource *res;
 126
 127    res = virgl_resource(ib->buffer);
 128    if (res)
 129       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 130 }
 131
 132 static void virgl_attach_res_so_targets(struct virgl_context *vctx)
 133 {
 134    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 135    struct virgl_resource *res;
 136    unsigned i;
 137
 138    for (i = 0; i < vctx->num_so_targets; i++) {
 139       res = virgl_resource(vctx->so_targets[i].base.buffer);
 140       if (res)
 141          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 142    }
 143 }
 144
 145 static void virgl_attach_res_uniform_buffers(struct virgl_context *vctx,
 146                                              enum pipe_shader_type shader_type)
 147 {
 148    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 149    struct virgl_resource *res;
 150    unsigned i;
 151    for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
 152       res = virgl_resource(vctx->ubos[shader_type][i]);
 153       if (res) {
 154          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 155       }
 156    }
 157 }
 158
 159 static void virgl_attach_res_shader_buffers(struct virgl_context *vctx,
 160                                             enum pipe_shader_type shader_type)
 161 {
 162    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 163    struct virgl_resource *res;
 164    unsigned i;
 165    for (i = 0; i < PIPE_MAX_SHADER_BUFFERS; i++) {
 166       res = virgl_resource(vctx->ssbos[shader_type][i]);
 167       if (res) {
 168          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 169       }
 170    }
 171 }
 172
 173 static void virgl_attach_res_shader_images(struct virgl_context *vctx,
 174                                            enum pipe_shader_type shader_type)
 175 {
 176    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 177    struct virgl_resource *res;
 178    unsigned i;
 179    for (i = 0; i < PIPE_MAX_SHADER_IMAGES; i++) {
 180       res = virgl_resource(vctx->images[shader_type][i]);
 181       if (res) {
 182          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 183       }
 184    }
 185 }
 186
 187 static void virgl_attach_res_atomic_buffers(struct virgl_context *vctx)
 188 {
 189    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 190    struct virgl_resource *res;
 191    unsigned i;
 192    for (i = 0; i < PIPE_MAX_HW_ATOMIC_BUFFERS; i++) {
 193       res = virgl_resource(vctx->atomic_buffers[i]);
 194       if (res) {
 195          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 196       }
 197    }
 198 }
 199
 200 /*
 201  * after flushing, the hw context still has a bunch of
 202  * resources bound, so we need to rebind those here.
 203  */
 204 static void virgl_reemit_res(struct virgl_context *vctx)
 205 {
 206    enum pipe_shader_type shader_type;
 207
 208    /* reattach any flushed resources */
 209    /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
 210    virgl_attach_res_framebuffer(vctx);
 211
 212    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
 213       virgl_attach_res_sampler_views(vctx, shader_type);
 214       virgl_attach_res_uniform_buffers(vctx, shader_type);
 215       virgl_attach_res_shader_buffers(vctx, shader_type);
 216       virgl_attach_res_shader_images(vctx, shader_type);
 217    }
 218    virgl_attach_res_atomic_buffers(vctx);
 219    virgl_attach_res_vertex_buffers(vctx);
 220    virgl_attach_res_so_targets(vctx);
 221 }
 222
 223 static struct pipe_surface *virgl_create_surface(struct pipe_context *ctx,
 224                                                 struct pipe_resource *resource,
 225                                                 const struct pipe_surface *templ)
 226 {
 227    struct virgl_context *vctx = virgl_context(ctx);
 228    struct virgl_surface *surf;
 229    struct virgl_resource *res = virgl_resource(resource);
 230    uint32_t handle;
 231
 232    surf = CALLOC_STRUCT(virgl_surface);
 233    if (!surf)
 234       return NULL;
 235
 236    assert(ctx->screen->get_param(ctx->screen,
 237                                  PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
 238           (util_format_is_srgb(templ->format) ==
 239            util_format_is_srgb(resource->format)));
 240
 241    virgl_resource_dirty(res, 0);
 242    handle = virgl_object_assign_handle();
 243    pipe_reference_init(&surf->base.reference, 1);
 244    pipe_resource_reference(&surf->base.texture, resource);
 245    surf->base.context = ctx;
 246    surf->base.format = templ->format;
 247    if (resource->target != PIPE_BUFFER) {
 248       surf->base.width = u_minify(resource->width0, templ->u.tex.level);
 249       surf->base.height = u_minify(resource->height0, templ->u.tex.level);
 250       surf->base.u.tex.level = templ->u.tex.level;
 251       surf->base.u.tex.first_layer = templ->u.tex.first_layer;
 252       surf->base.u.tex.last_layer = templ->u.tex.last_layer;
 253    } else {
 254       surf->base.width = templ->u.buf.last_element - templ->u.buf.first_element + 1;
 255       surf->base.height = resource->height0;
 256       surf->base.u.buf.first_element = templ->u.buf.first_element;
 257       surf->base.u.buf.last_element = templ->u.buf.last_element;
 258    }
 259    virgl_encoder_create_surface(vctx, handle, res, &surf->base);
 260    surf->handle = handle;
 261    return &surf->base;
 262 }
 263
 264 static void virgl_surface_destroy(struct pipe_context *ctx,
 265                                  struct pipe_surface *psurf)
 266 {
 267    struct virgl_context *vctx = virgl_context(ctx);
 268    struct virgl_surface *surf = virgl_surface(psurf);
 269
 270    pipe_resource_reference(&surf->base.texture, NULL);
 271    virgl_encode_delete_object(vctx, surf->handle, VIRGL_OBJECT_SURFACE);
 272    FREE(surf);
 273 }
 274
 275 static void *virgl_create_blend_state(struct pipe_context *ctx,
 276                                               const struct pipe_blend_state *blend_state)
 277 {
 278    struct virgl_context *vctx = virgl_context(ctx);
 279    uint32_t handle;
 280    handle = virgl_object_assign_handle();
 281
 282    virgl_encode_blend_state(vctx, handle, blend_state);
 283    return (void *)(unsigned long)handle;
 284
 285 }
 286
 287 static void virgl_bind_blend_state(struct pipe_context *ctx,
 288                                            void *blend_state)
 289 {
 290    struct virgl_context *vctx = virgl_context(ctx);
 291    uint32_t handle = (unsigned long)blend_state;
 292    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_BLEND);
 293 }
 294
 295 static void virgl_delete_blend_state(struct pipe_context *ctx,
 296                                      void *blend_state)
 297 {
 298    struct virgl_context *vctx = virgl_context(ctx);
 299    uint32_t handle = (unsigned long)blend_state;
 300    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_BLEND);
 301 }
 302
 303 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context *ctx,
 304                                                    const struct pipe_depth_stencil_alpha_state *blend_state)
 305 {
 306    struct virgl_context *vctx = virgl_context(ctx);
 307    uint32_t handle;
 308    handle = virgl_object_assign_handle();
 309
 310    virgl_encode_dsa_state(vctx, handle, blend_state);
 311    return (void *)(unsigned long)handle;
 312 }
 313
 314 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context *ctx,
 315                                                 void *blend_state)
 316 {
 317    struct virgl_context *vctx = virgl_context(ctx);
 318    uint32_t handle = (unsigned long)blend_state;
 319    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_DSA);
 320 }
 321
 322 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context *ctx,
 323                                                   void *dsa_state)
 324 {
 325    struct virgl_context *vctx = virgl_context(ctx);
 326    uint32_t handle = (unsigned long)dsa_state;
 327    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_DSA);
 328 }
 329
 330 static void *virgl_create_rasterizer_state(struct pipe_context *ctx,
 331                                                    const struct pipe_rasterizer_state *rs_state)
 332 {
 333    struct virgl_context *vctx = virgl_context(ctx);
 334    struct virgl_rasterizer_state *vrs = CALLOC_STRUCT(virgl_rasterizer_state);
 335
 336    if (!vrs)
 337       return NULL;
 338    vrs->rs = *rs_state;
 339    vrs->handle = virgl_object_assign_handle();
 340
 341    virgl_encode_rasterizer_state(vctx, vrs->handle, rs_state);
 342    return (void *)vrs;
 343 }
 344
 345 static void virgl_bind_rasterizer_state(struct pipe_context *ctx,
 346                                                 void *rs_state)
 347 {
 348    struct virgl_context *vctx = virgl_context(ctx);
 349    uint32_t handle = 0;
 350    if (rs_state) {
 351       struct virgl_rasterizer_state *vrs = rs_state;
 352       vctx->rs_state = *vrs;
 353       handle = vrs->handle;
 354    }
 355    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
 356 }
 357
 358 static void virgl_delete_rasterizer_state(struct pipe_context *ctx,
 359                                          void *rs_state)
 360 {
 361    struct virgl_context *vctx = virgl_context(ctx);
 362    struct virgl_rasterizer_state *vrs = rs_state;
 363    virgl_encode_delete_object(vctx, vrs->handle, VIRGL_OBJECT_RASTERIZER);
 364    FREE(vrs);
 365 }
 366
 367 static void virgl_set_framebuffer_state(struct pipe_context *ctx,
 368                                                 const struct pipe_framebuffer_state *state)
 369 {
 370    struct virgl_context *vctx = virgl_context(ctx);
 371
 372    vctx->framebuffer = *state;
 373    virgl_encoder_set_framebuffer_state(vctx, state);
 374    virgl_attach_res_framebuffer(vctx);
 375 }
 376
 377 static void virgl_set_viewport_states(struct pipe_context *ctx,
 378                                      unsigned start_slot,
 379                                      unsigned num_viewports,
 380                                      const struct pipe_viewport_state *state)
 381 {
 382    struct virgl_context *vctx = virgl_context(ctx);
 383    virgl_encoder_set_viewport_states(vctx, start_slot, num_viewports, state);
 384 }
 385
 386 static void *virgl_create_vertex_elements_state(struct pipe_context *ctx,
 387                                                         unsigned num_elements,
 388                                                         const struct pipe_vertex_element *elements)
 389 {
 390    struct pipe_vertex_element new_elements[PIPE_MAX_ATTRIBS];
 391    struct virgl_context *vctx = virgl_context(ctx);
 392    struct virgl_vertex_elements_state *state =
 393       CALLOC_STRUCT(virgl_vertex_elements_state);
 394
 395    for (int i = 0; i < num_elements; ++i) {
 396       if (elements[i].instance_divisor) {
 397          /* Virglrenderer doesn't deal with instance_divisor correctly if
 398           * there isn't a 1:1 relationship between elements and bindings.
 399           * So let's make sure there is, by duplicating bindings.
 400           */
 401          for (int j = 0; j < num_elements; ++j) {
 402             new_elements[j] = elements[j];
 403             new_elements[j].vertex_buffer_index = j;
 404             state->binding_map[j] = elements[j].vertex_buffer_index;
 405          }
 406          elements = new_elements;
 407          state->num_bindings = num_elements;
 408          break;
 409       }
 410    }
 411
 412    state->handle = virgl_object_assign_handle();
 413    virgl_encoder_create_vertex_elements(vctx, state->handle,
 414                                        num_elements, elements);
 415    return state;
 416 }
 417
 418 static void virgl_delete_vertex_elements_state(struct pipe_context *ctx,
 419                                               void *ve)
 420 {
 421    struct virgl_context *vctx = virgl_context(ctx);
 422    struct virgl_vertex_elements_state *state =
 423       (struct virgl_vertex_elements_state *)ve;
 424    virgl_encode_delete_object(vctx, state->handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
 425    FREE(state);
 426 }
 427
 428 static void virgl_bind_vertex_elements_state(struct pipe_context *ctx,
 429                                                      void *ve)
 430 {
 431    struct virgl_context *vctx = virgl_context(ctx);
 432    struct virgl_vertex_elements_state *state =
 433       (struct virgl_vertex_elements_state *)ve;
 434    vctx->vertex_elements = state;
 435    virgl_encode_bind_object(vctx, state ? state->handle : 0,
 436                             VIRGL_OBJECT_VERTEX_ELEMENTS);
 437    vctx->vertex_array_dirty = TRUE;
 438 }
 439
 440 static void virgl_set_vertex_buffers(struct pipe_context *ctx,
 441                                     unsigned start_slot,
 442                                     unsigned num_buffers,
 443                                     const struct pipe_vertex_buffer *buffers)
 444 {
 445    struct virgl_context *vctx = virgl_context(ctx);
 446
 447    util_set_vertex_buffers_count(vctx->vertex_buffer,
 448                                  &vctx->num_vertex_buffers,
 449                                  buffers, start_slot, num_buffers);
 450
 451    vctx->vertex_array_dirty = TRUE;
 452 }
 453
 454 static void virgl_hw_set_vertex_buffers(struct virgl_context *vctx)
 455 {
 456    if (vctx->vertex_array_dirty) {
 457       struct virgl_vertex_elements_state *ve = vctx->vertex_elements;
 458
 459       if (ve->num_bindings) {
 460          struct pipe_vertex_buffer vertex_buffers[PIPE_MAX_ATTRIBS];
 461          for (int i = 0; i < ve->num_bindings; ++i)
 462             vertex_buffers[i] = vctx->vertex_buffer[ve->binding_map[i]];
 463
 464          virgl_encoder_set_vertex_buffers(vctx, ve->num_bindings, vertex_buffers);
 465       } else
 466          virgl_encoder_set_vertex_buffers(vctx, vctx->num_vertex_buffers, vctx->vertex_buffer);
 467
 468       virgl_attach_res_vertex_buffers(vctx);
 469    }
 470 }
 471
 472 static void virgl_set_stencil_ref(struct pipe_context *ctx,
 473                                  const struct pipe_stencil_ref *ref)
 474 {
 475    struct virgl_context *vctx = virgl_context(ctx);
 476    virgl_encoder_set_stencil_ref(vctx, ref);
 477 }
 478
 479 static void virgl_set_blend_color(struct pipe_context *ctx,
 480                                  const struct pipe_blend_color *color)
 481 {
 482    struct virgl_context *vctx = virgl_context(ctx);
 483    virgl_encoder_set_blend_color(vctx, color);
 484 }
 485
 486 static void virgl_hw_set_index_buffer(struct virgl_context *vctx,
 487                                      struct virgl_indexbuf *ib)
 488 {
 489    virgl_encoder_set_index_buffer(vctx, ib);
 490    virgl_attach_res_index_buffer(vctx, ib);
 491 }
 492
 493 static void virgl_set_constant_buffer(struct pipe_context *ctx,
 494                                      enum pipe_shader_type shader, uint index,
 495                                      const struct pipe_constant_buffer *buf)
 496 {
 497    struct virgl_context *vctx = virgl_context(ctx);
 498
 499    if (buf) {
 500       if (!buf->user_buffer){
 501          struct virgl_resource *res = virgl_resource(buf->buffer);
 502          virgl_encoder_set_uniform_buffer(vctx, shader, index, buf->buffer_offset,
 503                                           buf->buffer_size, res);
 504          pipe_resource_reference(&vctx->ubos[shader][index], buf->buffer);
 505          return;
 506       }
 507       pipe_resource_reference(&vctx->ubos[shader][index], NULL);
 508       virgl_encoder_write_constant_buffer(vctx, shader, index, buf->buffer_size / 4, buf->user_buffer);
 509    } else {
 510       virgl_encoder_write_constant_buffer(vctx, shader, index, 0, NULL);
 511       pipe_resource_reference(&vctx->ubos[shader][index], NULL);
 512    }
 513 }
 514
 515 void virgl_transfer_inline_write(struct pipe_context *ctx,
 516                                 struct pipe_resource *res,
 517                                 unsigned level,
 518                                 unsigned usage,
 519                                 const struct pipe_box *box,
 520                                 const void *data,
 521                                 unsigned stride,
 522                                 unsigned layer_stride)
 523 {
 524    struct virgl_context *vctx = virgl_context(ctx);
 525    struct virgl_resource *grres = virgl_resource(res);
 526    struct virgl_transfer trans = { 0 };
 527
 528    trans.base.resource = res;
 529    trans.base.level = level;
 530    trans.base.usage = usage;
 531    trans.base.box = *box;
 532    trans.base.stride = stride;
 533    trans.base.layer_stride = layer_stride;
 534    trans.offset = box->x;
 535
 536    virgl_resource_dirty(grres, 0);
 537
 538    if (virgl_res_needs_flush(vctx, &trans))
 539       ctx->flush(ctx, NULL, 0);
 540
 541    virgl_encoder_inline_write(vctx, grres, level, usage,
 542                               box, data, stride, layer_stride);
 543 }
 544
 545 static void *virgl_shader_encoder(struct pipe_context *ctx,
 546                                   const struct pipe_shader_state *shader,
 547                                   unsigned type)
 548 {
 549    struct virgl_context *vctx = virgl_context(ctx);
 550    uint32_t handle;
 551    struct tgsi_token *new_tokens;
 552    int ret;
 553
 554    new_tokens = virgl_tgsi_transform(vctx, shader->tokens);
 555    if (!new_tokens)
 556       return NULL;
 557
 558    handle = virgl_object_assign_handle();
 559    /* encode VS state */
 560    ret = virgl_encode_shader_state(vctx, handle, type,
 561                                    &shader->stream_output, 0,
 562                                    new_tokens);
 563    if (ret) {
 564       return NULL;
 565    }
 566
 567    FREE(new_tokens);
 568    return (void *)(unsigned long)handle;
 569
 570 }
 571 static void *virgl_create_vs_state(struct pipe_context *ctx,
 572                                    const struct pipe_shader_state *shader)
 573 {
 574    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_VERTEX);
 575 }
 576
 577 static void *virgl_create_tcs_state(struct pipe_context *ctx,
 578                                    const struct pipe_shader_state *shader)
 579 {
 580    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_CTRL);
 581 }
 582
 583 static void *virgl_create_tes_state(struct pipe_context *ctx,
 584                                    const struct pipe_shader_state *shader)
 585 {
 586    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_EVAL);
 587 }
 588
 589 static void *virgl_create_gs_state(struct pipe_context *ctx,
 590                                    const struct pipe_shader_state *shader)
 591 {
 592    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_GEOMETRY);
 593 }
 594
 595 static void *virgl_create_fs_state(struct pipe_context *ctx,
 596                                    const struct pipe_shader_state *shader)
 597 {
 598    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_FRAGMENT);
 599 }
 600
 601 static void
 602 virgl_delete_fs_state(struct pipe_context *ctx,
 603                      void *fs)
 604 {
 605    uint32_t handle = (unsigned long)fs;
 606    struct virgl_context *vctx = virgl_context(ctx);
 607
 608    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 609 }
 610
 611 static void
 612 virgl_delete_gs_state(struct pipe_context *ctx,
 613                      void *gs)
 614 {
 615    uint32_t handle = (unsigned long)gs;
 616    struct virgl_context *vctx = virgl_context(ctx);
 617
 618    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 619 }
 620
 621 static void
 622 virgl_delete_vs_state(struct pipe_context *ctx,
 623                      void *vs)
 624 {
 625    uint32_t handle = (unsigned long)vs;
 626    struct virgl_context *vctx = virgl_context(ctx);
 627
 628    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 629 }
 630
 631 static void
 632 virgl_delete_tcs_state(struct pipe_context *ctx,
 633                        void *tcs)
 634 {
 635    uint32_t handle = (unsigned long)tcs;
 636    struct virgl_context *vctx = virgl_context(ctx);
 637
 638    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 639 }
 640
 641 static void
 642 virgl_delete_tes_state(struct pipe_context *ctx,
 643                       void *tes)
 644 {
 645    uint32_t handle = (unsigned long)tes;
 646    struct virgl_context *vctx = virgl_context(ctx);
 647
 648    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 649 }
 650
 651 static void virgl_bind_vs_state(struct pipe_context *ctx,
 652                                         void *vss)
 653 {
 654    uint32_t handle = (unsigned long)vss;
 655    struct virgl_context *vctx = virgl_context(ctx);
 656
 657    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_VERTEX);
 658 }
 659
 660 static void virgl_bind_tcs_state(struct pipe_context *ctx,
 661                                void *vss)
 662 {
 663    uint32_t handle = (unsigned long)vss;
 664    struct virgl_context *vctx = virgl_context(ctx);
 665
 666    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_CTRL);
 667 }
 668
 669 static void virgl_bind_tes_state(struct pipe_context *ctx,
 670                                void *vss)
 671 {
 672    uint32_t handle = (unsigned long)vss;
 673    struct virgl_context *vctx = virgl_context(ctx);
 674
 675    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_EVAL);
 676 }
 677
 678 static void virgl_bind_gs_state(struct pipe_context *ctx,
 679                                void *vss)
 680 {
 681    uint32_t handle = (unsigned long)vss;
 682    struct virgl_context *vctx = virgl_context(ctx);
 683
 684    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_GEOMETRY);
 685 }
 686
 687
 688 static void virgl_bind_fs_state(struct pipe_context *ctx,
 689                                         void *vss)
 690 {
 691    uint32_t handle = (unsigned long)vss;
 692    struct virgl_context *vctx = virgl_context(ctx);
 693
 694    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_FRAGMENT);
 695 }
 696
 697 static void virgl_clear(struct pipe_context *ctx,
 698                                 unsigned buffers,
 699                                 const union pipe_color_union *color,
 700                                 double depth, unsigned stencil)
 701 {
 702    struct virgl_context *vctx = virgl_context(ctx);
 703
 704    virgl_encode_clear(vctx, buffers, color, depth, stencil);
 705 }
 706
 707 static void virgl_draw_vbo(struct pipe_context *ctx,
 708                                    const struct pipe_draw_info *dinfo)
 709 {
 710    struct virgl_context *vctx = virgl_context(ctx);
 711    struct virgl_screen *rs = virgl_screen(ctx->screen);
 712    struct virgl_indexbuf ib = {};
 713    struct pipe_draw_info info = *dinfo;
 714
 715    if (!dinfo->count_from_stream_output && !dinfo->indirect &&
 716        !dinfo->primitive_restart &&
 717        !u_trim_pipe_prim(dinfo->mode, (unsigned*)&dinfo->count))
 718       return;
 719
 720    if (!(rs->caps.caps.v1.prim_mask & (1 << dinfo->mode))) {
 721       util_primconvert_save_rasterizer_state(vctx->primconvert, &vctx->rs_state.rs);
 722       util_primconvert_draw_vbo(vctx->primconvert, dinfo);
 723       return;
 724    }
 725    if (info.index_size) {
 726            pipe_resource_reference(&ib.buffer, info.has_user_indices ? NULL : info.index.resource);
 727            ib.user_buffer = info.has_user_indices ? info.index.user : NULL;
 728            ib.index_size = dinfo->index_size;
 729            ib.offset = info.start * ib.index_size;
 730
 731            if (ib.user_buffer) {
 732                    u_upload_data(vctx->uploader, 0, info.count * ib.index_size, 4,
 733                                  ib.user_buffer, &ib.offset, &ib.buffer);
 734                    ib.user_buffer = NULL;
 735            }
 736    }
 737
 738    vctx->num_draws++;
 739    virgl_hw_set_vertex_buffers(vctx);
 740    if (info.index_size)
 741       virgl_hw_set_index_buffer(vctx, &ib);
 742
 743    virgl_encoder_draw_vbo(vctx, &info);
 744
 745    pipe_resource_reference(&ib.buffer, NULL);
 746
 747 }
 748
 749 static void virgl_flush_eq(struct virgl_context *ctx, void *closure,
 750                            struct pipe_fence_handle **fence)
 751 {
 752    struct virgl_screen *rs = virgl_screen(ctx->base.screen);
 753
 754    if (ctx->num_draws)
 755       u_upload_unmap(ctx->uploader);
 756
 757    /* send the buffer to the remote side for decoding */
 758    ctx->num_draws = ctx->num_compute = 0;
 759
 760    virgl_transfer_queue_clear(&ctx->queue, ctx->cbuf);
 761    rs->vws->submit_cmd(rs->vws, ctx->cbuf, fence);
 762
 763    /* Reserve some space for transfers. */
 764    if (ctx->encoded_transfers)
 765       ctx->cbuf->cdw = VIRGL_MAX_TBUF_DWORDS;
 766
 767    virgl_encoder_set_sub_ctx(ctx, ctx->hw_sub_ctx_id);
 768
 769    /* add back current framebuffer resources to reference list? */
 770    virgl_reemit_res(ctx);
 771 }
 772
 773 static void virgl_flush_from_st(struct pipe_context *ctx,
 774                                struct pipe_fence_handle **fence,
 775                                enum pipe_flush_flags flags)
 776 {
 777    struct virgl_context *vctx = virgl_context(ctx);
 778
 779    virgl_flush_eq(vctx, vctx, fence);
 780 }
 781
 782 static struct pipe_sampler_view *virgl_create_sampler_view(struct pipe_context *ctx,
 783                                       struct pipe_resource *texture,
 784                                       const struct pipe_sampler_view *state)
 785 {
 786    struct virgl_context *vctx = virgl_context(ctx);
 787    struct virgl_sampler_view *grview;
 788    uint32_t handle;
 789    struct virgl_resource *res;
 790
 791    if (!state)
 792       return NULL;
 793
 794    grview = CALLOC_STRUCT(virgl_sampler_view);
 795    if (!grview)
 796       return NULL;
 797
 798    res = virgl_resource(texture);
 799    handle = virgl_object_assign_handle();
 800    virgl_encode_sampler_view(vctx, handle, res, state);
 801
 802    grview->base = *state;
 803    grview->base.reference.count = 1;
 804
 805    grview->base.texture = NULL;
 806    grview->base.context = ctx;
 807    pipe_resource_reference(&grview->base.texture, texture);
 808    grview->handle = handle;
 809    return &grview->base;
 810 }
 811
 812 static void virgl_set_sampler_views(struct pipe_context *ctx,
 813                                    enum pipe_shader_type shader_type,
 814                                    unsigned start_slot,
 815                                    unsigned num_views,
 816                                    struct pipe_sampler_view **views)
 817 {
 818    struct virgl_context *vctx = virgl_context(ctx);
 819    int i;
 820    uint32_t disable_mask = ~((1ull << num_views) - 1);
 821    struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
 822    uint32_t new_mask = 0;
 823    uint32_t remaining_mask;
 824
 825    remaining_mask = tinfo->enabled_mask & disable_mask;
 826
 827    while (remaining_mask) {
 828       i = u_bit_scan(&remaining_mask);
 829       assert(tinfo->views[i]);
 830
 831       pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
 832    }
 833
 834    for (i = 0; i < num_views; i++) {
 835       struct virgl_sampler_view *grview = virgl_sampler_view(views[i]);
 836
 837       if (views[i] == (struct pipe_sampler_view *)tinfo->views[i])
 838          continue;
 839
 840       if (grview) {
 841          new_mask |= 1 << i;
 842          pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], views[i]);
 843       } else {
 844          pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
 845          disable_mask |= 1 << i;
 846       }
 847    }
 848
 849    tinfo->enabled_mask &= ~disable_mask;
 850    tinfo->enabled_mask |= new_mask;
 851    virgl_encode_set_sampler_views(vctx, shader_type, start_slot, num_views, tinfo->views);
 852    virgl_attach_res_sampler_views(vctx, shader_type);
 853 }
 854
 855 static void
 856 virgl_texture_barrier(struct pipe_context *ctx, unsigned flags)
 857 {
 858    struct virgl_context *vctx = virgl_context(ctx);
 859    struct virgl_screen *rs = virgl_screen(ctx->screen);
 860
 861    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER))
 862       return;
 863    virgl_encode_texture_barrier(vctx, flags);
 864 }
 865
 866 static void virgl_destroy_sampler_view(struct pipe_context *ctx,
 867                                  struct pipe_sampler_view *view)
 868 {
 869    struct virgl_context *vctx = virgl_context(ctx);
 870    struct virgl_sampler_view *grview = virgl_sampler_view(view);
 871
 872    virgl_encode_delete_object(vctx, grview->handle, VIRGL_OBJECT_SAMPLER_VIEW);
 873    pipe_resource_reference(&view->texture, NULL);
 874    FREE(view);
 875 }
 876
 877 static void *virgl_create_sampler_state(struct pipe_context *ctx,
 878                                         const struct pipe_sampler_state *state)
 879 {
 880    struct virgl_context *vctx = virgl_context(ctx);
 881    uint32_t handle;
 882
 883    handle = virgl_object_assign_handle();
 884
 885    virgl_encode_sampler_state(vctx, handle, state);
 886    return (void *)(unsigned long)handle;
 887 }
 888
 889 static void virgl_delete_sampler_state(struct pipe_context *ctx,
 890                                       void *ss)
 891 {
 892    struct virgl_context *vctx = virgl_context(ctx);
 893    uint32_t handle = (unsigned long)ss;
 894
 895    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SAMPLER_STATE);
 896 }
 897
 898 static void virgl_bind_sampler_states(struct pipe_context *ctx,
 899                                      enum pipe_shader_type shader,
 900                                      unsigned start_slot,
 901                                      unsigned num_samplers,
 902                                      void **samplers)
 903 {
 904    struct virgl_context *vctx = virgl_context(ctx);
 905    uint32_t handles[32];
 906    int i;
 907    for (i = 0; i < num_samplers; i++) {
 908       handles[i] = (unsigned long)(samplers[i]);
 909    }
 910    virgl_encode_bind_sampler_states(vctx, shader, start_slot, num_samplers, handles);
 911 }
 912
 913 static void virgl_set_polygon_stipple(struct pipe_context *ctx,
 914                                      const struct pipe_poly_stipple *ps)
 915 {
 916    struct virgl_context *vctx = virgl_context(ctx);
 917    virgl_encoder_set_polygon_stipple(vctx, ps);
 918 }
 919
 920 static void virgl_set_scissor_states(struct pipe_context *ctx,
 921                                     unsigned start_slot,
 922                                     unsigned num_scissor,
 923                                    const struct pipe_scissor_state *ss)
 924 {
 925    struct virgl_context *vctx = virgl_context(ctx);
 926    virgl_encoder_set_scissor_state(vctx, start_slot, num_scissor, ss);
 927 }
 928
 929 static void virgl_set_sample_mask(struct pipe_context *ctx,
 930                                  unsigned sample_mask)
 931 {
 932    struct virgl_context *vctx = virgl_context(ctx);
 933    virgl_encoder_set_sample_mask(vctx, sample_mask);
 934 }
 935
 936 static void virgl_set_min_samples(struct pipe_context *ctx,
 937                                  unsigned min_samples)
 938 {
 939    struct virgl_context *vctx = virgl_context(ctx);
 940    struct virgl_screen *rs = virgl_screen(ctx->screen);
 941
 942    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_SET_MIN_SAMPLES))
 943       return;
 944    virgl_encoder_set_min_samples(vctx, min_samples);
 945 }
 946
 947 static void virgl_set_clip_state(struct pipe_context *ctx,
 948                                 const struct pipe_clip_state *clip)
 949 {
 950    struct virgl_context *vctx = virgl_context(ctx);
 951    virgl_encoder_set_clip_state(vctx, clip);
 952 }
 953
 954 static void virgl_set_tess_state(struct pipe_context *ctx,
 955                                  const float default_outer_level[4],
 956                                  const float default_inner_level[2])
 957 {
 958    struct virgl_context *vctx = virgl_context(ctx);
 959    struct virgl_screen *rs = virgl_screen(ctx->screen);
 960
 961    if (!rs->caps.caps.v1.bset.has_tessellation_shaders)
 962       return;
 963    virgl_encode_set_tess_state(vctx, default_outer_level, default_inner_level);
 964 }
 965
 966 static void virgl_resource_copy_region(struct pipe_context *ctx,
 967                                       struct pipe_resource *dst,
 968                                       unsigned dst_level,
 969                                       unsigned dstx, unsigned dsty, unsigned dstz,
 970                                       struct pipe_resource *src,
 971                                       unsigned src_level,
 972                                       const struct pipe_box *src_box)
 973 {
 974    struct virgl_context *vctx = virgl_context(ctx);
 975    struct virgl_resource *dres = virgl_resource(dst);
 976    struct virgl_resource *sres = virgl_resource(src);
 977
 978    virgl_resource_dirty(dres, dst_level);
 979    virgl_encode_resource_copy_region(vctx, dres,
 980                                     dst_level, dstx, dsty, dstz,
 981                                     sres, src_level,
 982                                     src_box);
 983 }
 984
 985 static void
 986 virgl_flush_resource(struct pipe_context *pipe,
 987                     struct pipe_resource *resource)
 988 {
 989 }
 990
 991 static void virgl_blit(struct pipe_context *ctx,
 992                       const struct pipe_blit_info *blit)
 993 {
 994    struct virgl_context *vctx = virgl_context(ctx);
 995    struct virgl_resource *dres = virgl_resource(blit->dst.resource);
 996    struct virgl_resource *sres = virgl_resource(blit->src.resource);
 997
 998    assert(ctx->screen->get_param(ctx->screen,
 999                                  PIPE_CAP_DEST_SURFACE_SRGB_CONTROL) ||
1000           (util_format_is_srgb(blit->dst.resource->format) ==
1001             util_format_is_srgb(blit->dst.format)));
1002
1003    virgl_resource_dirty(dres, blit->dst.level);
1004    virgl_encode_blit(vctx, dres, sres,
1005                     blit);
1006 }
1007
1008 static void virgl_set_hw_atomic_buffers(struct pipe_context *ctx,
1009                                         unsigned start_slot,
1010                                         unsigned count,
1011                                         const struct pipe_shader_buffer *buffers)
1012 {
1013    struct virgl_context *vctx = virgl_context(ctx);
1014
1015    for (unsigned i = 0; i < count; i++) {
1016       unsigned idx = start_slot + i;
1017
1018       if (buffers) {
1019          if (buffers[i].buffer) {
1020             pipe_resource_reference(&vctx->atomic_buffers[idx],
1021                                     buffers[i].buffer);
1022             continue;
1023          }
1024       }
1025       pipe_resource_reference(&vctx->atomic_buffers[idx], NULL);
1026    }
1027    virgl_encode_set_hw_atomic_buffers(vctx, start_slot, count, buffers);
1028 }
1029
1030 static void virgl_set_shader_buffers(struct pipe_context *ctx,
1031                                      enum pipe_shader_type shader,
1032                                      unsigned start_slot, unsigned count,
1033                                      const struct pipe_shader_buffer *buffers,
1034                                      unsigned writable_bitmask)
1035 {
1036    struct virgl_context *vctx = virgl_context(ctx);
1037    struct virgl_screen *rs = virgl_screen(ctx->screen);
1038
1039    for (unsigned i = 0; i < count; i++) {
1040       unsigned idx = start_slot + i;
1041
1042       if (buffers) {
1043          if (buffers[i].buffer) {
1044             pipe_resource_reference(&vctx->ssbos[shader][idx], buffers[i].buffer);
1045             continue;
1046          }
1047       }
1048       pipe_resource_reference(&vctx->ssbos[shader][idx], NULL);
1049    }
1050
1051    uint32_t max_shader_buffer = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1052       rs->caps.caps.v2.max_shader_buffer_frag_compute :
1053       rs->caps.caps.v2.max_shader_buffer_other_stages;
1054    if (!max_shader_buffer)
1055       return;
1056    virgl_encode_set_shader_buffers(vctx, shader, start_slot, count, buffers);
1057 }
1058
1059 static void virgl_create_fence_fd(struct pipe_context *ctx,
1060                                   struct pipe_fence_handle **fence,
1061                                   int fd,
1062                                   enum pipe_fd_type type)
1063 {
1064    assert(type == PIPE_FD_TYPE_NATIVE_SYNC);
1065    struct virgl_screen *rs = virgl_screen(ctx->screen);
1066
1067    if (rs->vws->cs_create_fence)
1068       *fence = rs->vws->cs_create_fence(rs->vws, fd);
1069 }
1070
1071 static void virgl_fence_server_sync(struct pipe_context *ctx,
1072                                     struct pipe_fence_handle *fence)
1073 {
1074    struct virgl_context *vctx = virgl_context(ctx);
1075    struct virgl_screen *rs = virgl_screen(ctx->screen);
1076
1077    if (rs->vws->fence_server_sync)
1078       rs->vws->fence_server_sync(rs->vws, vctx->cbuf, fence);
1079 }
1080
1081 static void virgl_set_shader_images(struct pipe_context *ctx,
1082                                     enum pipe_shader_type shader,
1083                                     unsigned start_slot, unsigned count,
1084                                     const struct pipe_image_view *images)
1085 {
1086    struct virgl_context *vctx = virgl_context(ctx);
1087    struct virgl_screen *rs = virgl_screen(ctx->screen);
1088
1089    for (unsigned i = 0; i < count; i++) {
1090       unsigned idx = start_slot + i;
1091
1092       if (images) {
1093          if (images[i].resource) {
1094             pipe_resource_reference(&vctx->images[shader][idx], images[i].resource);
1095             continue;
1096          }
1097       }
1098       pipe_resource_reference(&vctx->images[shader][idx], NULL);
1099    }
1100
1101    uint32_t max_shader_images = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1102      rs->caps.caps.v2.max_shader_image_frag_compute :
1103      rs->caps.caps.v2.max_shader_image_other_stages;
1104    if (!max_shader_images)
1105       return;
1106    virgl_encode_set_shader_images(vctx, shader, start_slot, count, images);
1107 }
1108
1109 static void virgl_memory_barrier(struct pipe_context *ctx,
1110                                  unsigned flags)
1111 {
1112    struct virgl_context *vctx = virgl_context(ctx);
1113    struct virgl_screen *rs = virgl_screen(ctx->screen);
1114
1115    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_MEMORY_BARRIER))
1116       return;
1117    virgl_encode_memory_barrier(vctx, flags);
1118 }
1119
1120 static void *virgl_create_compute_state(struct pipe_context *ctx,
1121                                         const struct pipe_compute_state *state)
1122 {
1123    struct virgl_context *vctx = virgl_context(ctx);
1124    uint32_t handle;
1125    const struct tgsi_token *new_tokens = state->prog;
1126    struct pipe_stream_output_info so_info = {};
1127    int ret;
1128
1129    handle = virgl_object_assign_handle();
1130    ret = virgl_encode_shader_state(vctx, handle, PIPE_SHADER_COMPUTE,
1131                                    &so_info,
1132                                    state->req_local_mem,
1133                                    new_tokens);
1134    if (ret) {
1135       return NULL;
1136    }
1137
1138    return (void *)(unsigned long)handle;
1139 }
1140
1141 static void virgl_bind_compute_state(struct pipe_context *ctx, void *state)
1142 {
1143    uint32_t handle = (unsigned long)state;
1144    struct virgl_context *vctx = virgl_context(ctx);
1145
1146    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_COMPUTE);
1147 }
1148
1149 static void virgl_delete_compute_state(struct pipe_context *ctx, void *state)
1150 {
1151    uint32_t handle = (unsigned long)state;
1152    struct virgl_context *vctx = virgl_context(ctx);
1153
1154    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
1155 }
1156
1157 static void virgl_launch_grid(struct pipe_context *ctx,
1158                               const struct pipe_grid_info *info)
1159 {
1160    struct virgl_context *vctx = virgl_context(ctx);
1161    virgl_encode_launch_grid(vctx, info);
1162    vctx->num_compute++;
1163 }
1164
1165 static void
1166 virgl_context_destroy( struct pipe_context *ctx )
1167 {
1168    struct virgl_context *vctx = virgl_context(ctx);
1169    struct virgl_screen *rs = virgl_screen(ctx->screen);
1170
1171    vctx->framebuffer.zsbuf = NULL;
1172    vctx->framebuffer.nr_cbufs = 0;
1173    virgl_encoder_destroy_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1174    virgl_flush_eq(vctx, vctx, NULL);
1175
1176    rs->vws->cmd_buf_destroy(vctx->cbuf);
1177    if (vctx->uploader)
1178       u_upload_destroy(vctx->uploader);
1179    util_primconvert_destroy(vctx->primconvert);
1180    virgl_transfer_queue_fini(&vctx->queue);
1181
1182    slab_destroy_child(&vctx->transfer_pool);
1183    FREE(vctx);
1184 }
1185
1186 static void virgl_get_sample_position(struct pipe_context *ctx,
1187                                       unsigned sample_count,
1188                                       unsigned index,
1189                                       float *out_value)
1190 {
1191    struct virgl_context *vctx = virgl_context(ctx);
1192    struct virgl_screen *vs = virgl_screen(vctx->base.screen);
1193
1194    if (sample_count > vs->caps.caps.v1.max_samples) {
1195       debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1196                    sample_count, vs->caps.caps.v1.max_samples);
1197       return;
1198    }
1199
1200    /* The following is basically copied from dri/i965gen6_get_sample_position
1201     * The only addition is that we hold the msaa positions for all sample
1202     * counts in a flat array. */
1203    uint32_t bits = 0;
1204    if (sample_count == 1) {
1205       out_value[0] = out_value[1] = 0.5f;
1206       return;
1207    } else if (sample_count == 2) {
1208       bits = vs->caps.caps.v2.sample_locations[0] >> (8 * index);
1209    } else if (sample_count <= 4) {
1210       bits = vs->caps.caps.v2.sample_locations[1] >> (8 * index);
1211    } else if (sample_count <= 8) {
1212       bits = vs->caps.caps.v2.sample_locations[2 + (index >> 2)] >> (8 * (index & 3));
1213    } else if (sample_count <= 16) {
1214       bits = vs->caps.caps.v2.sample_locations[4 + (index >> 2)] >> (8 * (index & 3));
1215    }
1216    out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
1217    out_value[1] = (bits & 0xf) / 16.0f;
1218
1219    if (virgl_debug & VIRGL_DEBUG_VERBOSE)
1220       debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1221                    index, sample_count, out_value[0], out_value[1]);
1222 }
1223
1224 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
1225                                           void *priv,
1226                                           unsigned flags)
1227 {
1228    struct virgl_context *vctx;
1229    struct virgl_screen *rs = virgl_screen(pscreen);
1230    vctx = CALLOC_STRUCT(virgl_context);
1231    const char *host_debug_flagstring;
1232
1233    vctx->cbuf = rs->vws->cmd_buf_create(rs->vws, VIRGL_MAX_CMDBUF_DWORDS);
1234    if (!vctx->cbuf) {
1235       FREE(vctx);
1236       return NULL;
1237    }
1238
1239    vctx->base.destroy = virgl_context_destroy;
1240    vctx->base.create_surface = virgl_create_surface;
1241    vctx->base.surface_destroy = virgl_surface_destroy;
1242    vctx->base.set_framebuffer_state = virgl_set_framebuffer_state;
1243    vctx->base.create_blend_state = virgl_create_blend_state;
1244    vctx->base.bind_blend_state = virgl_bind_blend_state;
1245    vctx->base.delete_blend_state = virgl_delete_blend_state;
1246    vctx->base.create_depth_stencil_alpha_state = virgl_create_depth_stencil_alpha_state;
1247    vctx->base.bind_depth_stencil_alpha_state = virgl_bind_depth_stencil_alpha_state;
1248    vctx->base.delete_depth_stencil_alpha_state = virgl_delete_depth_stencil_alpha_state;
1249    vctx->base.create_rasterizer_state = virgl_create_rasterizer_state;
1250    vctx->base.bind_rasterizer_state = virgl_bind_rasterizer_state;
1251    vctx->base.delete_rasterizer_state = virgl_delete_rasterizer_state;
1252
1253    vctx->base.set_viewport_states = virgl_set_viewport_states;
1254    vctx->base.create_vertex_elements_state = virgl_create_vertex_elements_state;
1255    vctx->base.bind_vertex_elements_state = virgl_bind_vertex_elements_state;
1256    vctx->base.delete_vertex_elements_state = virgl_delete_vertex_elements_state;
1257    vctx->base.set_vertex_buffers = virgl_set_vertex_buffers;
1258    vctx->base.set_constant_buffer = virgl_set_constant_buffer;
1259
1260    vctx->base.set_tess_state = virgl_set_tess_state;
1261    vctx->base.create_vs_state = virgl_create_vs_state;
1262    vctx->base.create_tcs_state = virgl_create_tcs_state;
1263    vctx->base.create_tes_state = virgl_create_tes_state;
1264    vctx->base.create_gs_state = virgl_create_gs_state;
1265    vctx->base.create_fs_state = virgl_create_fs_state;
1266
1267    vctx->base.bind_vs_state = virgl_bind_vs_state;
1268    vctx->base.bind_tcs_state = virgl_bind_tcs_state;
1269    vctx->base.bind_tes_state = virgl_bind_tes_state;
1270    vctx->base.bind_gs_state = virgl_bind_gs_state;
1271    vctx->base.bind_fs_state = virgl_bind_fs_state;
1272
1273    vctx->base.delete_vs_state = virgl_delete_vs_state;
1274    vctx->base.delete_tcs_state = virgl_delete_tcs_state;
1275    vctx->base.delete_tes_state = virgl_delete_tes_state;
1276    vctx->base.delete_gs_state = virgl_delete_gs_state;
1277    vctx->base.delete_fs_state = virgl_delete_fs_state;
1278
1279    vctx->base.create_compute_state = virgl_create_compute_state;
1280    vctx->base.bind_compute_state = virgl_bind_compute_state;
1281    vctx->base.delete_compute_state = virgl_delete_compute_state;
1282    vctx->base.launch_grid = virgl_launch_grid;
1283
1284    vctx->base.clear = virgl_clear;
1285    vctx->base.draw_vbo = virgl_draw_vbo;
1286    vctx->base.flush = virgl_flush_from_st;
1287    vctx->base.screen = pscreen;
1288    vctx->base.create_sampler_view = virgl_create_sampler_view;
1289    vctx->base.sampler_view_destroy = virgl_destroy_sampler_view;
1290    vctx->base.set_sampler_views = virgl_set_sampler_views;
1291    vctx->base.texture_barrier = virgl_texture_barrier;
1292
1293    vctx->base.create_sampler_state = virgl_create_sampler_state;
1294    vctx->base.delete_sampler_state = virgl_delete_sampler_state;
1295    vctx->base.bind_sampler_states = virgl_bind_sampler_states;
1296
1297    vctx->base.set_polygon_stipple = virgl_set_polygon_stipple;
1298    vctx->base.set_scissor_states = virgl_set_scissor_states;
1299    vctx->base.set_sample_mask = virgl_set_sample_mask;
1300    vctx->base.set_min_samples = virgl_set_min_samples;
1301    vctx->base.set_stencil_ref = virgl_set_stencil_ref;
1302    vctx->base.set_clip_state = virgl_set_clip_state;
1303
1304    vctx->base.set_blend_color = virgl_set_blend_color;
1305
1306    vctx->base.get_sample_position = virgl_get_sample_position;
1307
1308    vctx->base.resource_copy_region = virgl_resource_copy_region;
1309    vctx->base.flush_resource = virgl_flush_resource;
1310    vctx->base.blit =  virgl_blit;
1311    vctx->base.create_fence_fd = virgl_create_fence_fd;
1312    vctx->base.fence_server_sync = virgl_fence_server_sync;
1313
1314    vctx->base.set_shader_buffers = virgl_set_shader_buffers;
1315    vctx->base.set_hw_atomic_buffers = virgl_set_hw_atomic_buffers;
1316    vctx->base.set_shader_images = virgl_set_shader_images;
1317    vctx->base.memory_barrier = virgl_memory_barrier;
1318
1319    virgl_init_context_resource_functions(&vctx->base);
1320    virgl_init_query_functions(vctx);
1321    virgl_init_so_functions(vctx);
1322
1323    slab_create_child(&vctx->transfer_pool, &rs->transfer_pool);
1324    virgl_transfer_queue_init(&vctx->queue, rs, &vctx->transfer_pool);
1325    vctx->encoded_transfers = (rs->vws->supports_encoded_transfers &&
1326                        (rs->caps.caps.v2.capability_bits & VIRGL_CAP_TRANSFER));
1327
1328    /* Reserve some space for transfers. */
1329    if (vctx->encoded_transfers)
1330       vctx->cbuf->cdw = VIRGL_MAX_TBUF_DWORDS;
1331
1332    vctx->primconvert = util_primconvert_create(&vctx->base, rs->caps.caps.v1.prim_mask);
1333    vctx->uploader = u_upload_create(&vctx->base, 1024 * 1024,
1334                                      PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM, 0);
1335    if (!vctx->uploader)
1336            goto fail;
1337    vctx->base.stream_uploader = vctx->uploader;
1338    vctx->base.const_uploader = vctx->uploader;
1339
1340    vctx->hw_sub_ctx_id = rs->sub_ctx_id++;
1341    virgl_encoder_create_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1342
1343    virgl_encoder_set_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1344
1345    if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_GUEST_MAY_INIT_LOG) {
1346       host_debug_flagstring = getenv("VIRGL_HOST_DEBUG");
1347       if (host_debug_flagstring)
1348          virgl_encode_host_debug_flagstring(vctx, host_debug_flagstring);
1349    }
1350
1351    return &vctx->base;
1352 fail:
1353    return NULL;
1354 }