src/gallium/drivers/virgl/virgl_context.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "pipe/p_shader_tokens.h"
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_defines.h"
  28 #include "pipe/p_screen.h"
  29 #include "pipe/p_state.h"
  30 #include "util/u_inlines.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_format.h"
  33 #include "util/u_prim.h"
  34 #include "util/u_transfer.h"
  35 #include "util/u_helpers.h"
  36 #include "util/slab.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_blitter.h"
  39 #include "tgsi/tgsi_text.h"
  40 #include "indices/u_primconvert.h"
  41
  42 #include "pipebuffer/pb_buffer.h"
  43
  44 #include "virgl_encode.h"
  45 #include "virgl_context.h"
  46 #include "virgl_protocol.h"
  47 #include "virgl_resource.h"
  48 #include "virgl_screen.h"
  49
  50 static uint32_t next_handle;
  51 uint32_t virgl_object_assign_handle(void)
  52 {
  53    return ++next_handle;
  54 }
  55
  56 static void virgl_buffer_flush(struct virgl_context *vctx,
  57                               struct virgl_buffer *vbuf)
  58 {
  59    struct virgl_screen *rs = virgl_screen(vctx->base.screen);
  60    struct pipe_box box;
  61
  62    assert(vbuf->on_list);
  63
  64    box.height = 1;
  65    box.depth = 1;
  66    box.y = 0;
  67    box.z = 0;
  68
  69    box.x = vbuf->valid_buffer_range.start;
  70    box.width = MIN2(vbuf->valid_buffer_range.end - vbuf->valid_buffer_range.start, vbuf->base.u.b.width0);
  71
  72    vctx->num_transfers++;
  73    rs->vws->transfer_put(rs->vws, vbuf->base.hw_res,
  74                          &box, 0, 0, box.x, 0);
  75
  76    util_range_set_empty(&vbuf->valid_buffer_range);
  77 }
  78
  79 static void virgl_attach_res_framebuffer(struct virgl_context *vctx)
  80 {
  81    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
  82    struct pipe_surface *surf;
  83    struct virgl_resource *res;
  84    unsigned i;
  85
  86    surf = vctx->framebuffer.zsbuf;
  87    if (surf) {
  88       res = virgl_resource(surf->texture);
  89       if (res)
  90          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
  91    }
  92    for (i = 0; i < vctx->framebuffer.nr_cbufs; i++) {
  93       surf = vctx->framebuffer.cbufs[i];
  94       if (surf) {
  95          res = virgl_resource(surf->texture);
  96          if (res)
  97             vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
  98       }
  99    }
 100 }
 101
 102 static void virgl_attach_res_sampler_views(struct virgl_context *vctx,
 103                                            enum pipe_shader_type shader_type)
 104 {
 105    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 106    struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
 107    struct virgl_resource *res;
 108    uint32_t remaining_mask = tinfo->enabled_mask;
 109    unsigned i;
 110    while (remaining_mask) {
 111       i = u_bit_scan(&remaining_mask);
 112       assert(tinfo->views[i]);
 113
 114       res = virgl_resource(tinfo->views[i]->base.texture);
 115       if (res)
 116          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 117    }
 118 }
 119
 120 static void virgl_attach_res_vertex_buffers(struct virgl_context *vctx)
 121 {
 122    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 123    struct virgl_resource *res;
 124    unsigned i;
 125
 126    for (i = 0; i < vctx->num_vertex_buffers; i++) {
 127       res = virgl_resource(vctx->vertex_buffer[i].buffer.resource);
 128       if (res)
 129          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 130    }
 131 }
 132
 133 static void virgl_attach_res_index_buffer(struct virgl_context *vctx,
 134                                           struct virgl_indexbuf *ib)
 135 {
 136    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 137    struct virgl_resource *res;
 138
 139    res = virgl_resource(ib->buffer);
 140    if (res)
 141       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 142 }
 143
 144 static void virgl_attach_res_so_targets(struct virgl_context *vctx)
 145 {
 146    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 147    struct virgl_resource *res;
 148    unsigned i;
 149
 150    for (i = 0; i < vctx->num_so_targets; i++) {
 151       res = virgl_resource(vctx->so_targets[i].base.buffer);
 152       if (res)
 153          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 154    }
 155 }
 156
 157 static void virgl_attach_res_uniform_buffers(struct virgl_context *vctx,
 158                                              enum pipe_shader_type shader_type)
 159 {
 160    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 161    struct virgl_resource *res;
 162    unsigned i;
 163    for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
 164       res = virgl_resource(vctx->ubos[shader_type][i]);
 165       if (res) {
 166          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 167       }
 168    }
 169 }
 170
 171 /*
 172  * after flushing, the hw context still has a bunch of
 173  * resources bound, so we need to rebind those here.
 174  */
 175 static void virgl_reemit_res(struct virgl_context *vctx)
 176 {
 177    enum pipe_shader_type shader_type;
 178
 179    /* reattach any flushed resources */
 180    /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
 181    virgl_attach_res_framebuffer(vctx);
 182
 183    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
 184       virgl_attach_res_sampler_views(vctx, shader_type);
 185       virgl_attach_res_uniform_buffers(vctx, shader_type);
 186    }
 187    virgl_attach_res_vertex_buffers(vctx);
 188    virgl_attach_res_so_targets(vctx);
 189 }
 190
 191 static struct pipe_surface *virgl_create_surface(struct pipe_context *ctx,
 192                                                 struct pipe_resource *resource,
 193                                                 const struct pipe_surface *templ)
 194 {
 195    struct virgl_context *vctx = virgl_context(ctx);
 196    struct virgl_surface *surf;
 197    struct virgl_resource *res = virgl_resource(resource);
 198    uint32_t handle;
 199
 200    surf = CALLOC_STRUCT(virgl_surface);
 201    if (!surf)
 202       return NULL;
 203
 204    res->clean = FALSE;
 205    handle = virgl_object_assign_handle();
 206    pipe_reference_init(&surf->base.reference, 1);
 207    pipe_resource_reference(&surf->base.texture, resource);
 208    surf->base.context = ctx;
 209    surf->base.format = templ->format;
 210    if (resource->target != PIPE_BUFFER) {
 211       surf->base.width = u_minify(resource->width0, templ->u.tex.level);
 212       surf->base.height = u_minify(resource->height0, templ->u.tex.level);
 213       surf->base.u.tex.level = templ->u.tex.level;
 214       surf->base.u.tex.first_layer = templ->u.tex.first_layer;
 215       surf->base.u.tex.last_layer = templ->u.tex.last_layer;
 216    } else {
 217       surf->base.width = templ->u.buf.last_element - templ->u.buf.first_element + 1;
 218       surf->base.height = resource->height0;
 219       surf->base.u.buf.first_element = templ->u.buf.first_element;
 220       surf->base.u.buf.last_element = templ->u.buf.last_element;
 221    }
 222    virgl_encoder_create_surface(vctx, handle, res, &surf->base);
 223    surf->handle = handle;
 224    return &surf->base;
 225 }
 226
 227 static void virgl_surface_destroy(struct pipe_context *ctx,
 228                                  struct pipe_surface *psurf)
 229 {
 230    struct virgl_context *vctx = virgl_context(ctx);
 231    struct virgl_surface *surf = virgl_surface(psurf);
 232
 233    pipe_resource_reference(&surf->base.texture, NULL);
 234    virgl_encode_delete_object(vctx, surf->handle, VIRGL_OBJECT_SURFACE);
 235    FREE(surf);
 236 }
 237
 238 static void *virgl_create_blend_state(struct pipe_context *ctx,
 239                                               const struct pipe_blend_state *blend_state)
 240 {
 241    struct virgl_context *vctx = virgl_context(ctx);
 242    uint32_t handle;
 243    handle = virgl_object_assign_handle();
 244
 245    virgl_encode_blend_state(vctx, handle, blend_state);
 246    return (void *)(unsigned long)handle;
 247
 248 }
 249
 250 static void virgl_bind_blend_state(struct pipe_context *ctx,
 251                                            void *blend_state)
 252 {
 253    struct virgl_context *vctx = virgl_context(ctx);
 254    uint32_t handle = (unsigned long)blend_state;
 255    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_BLEND);
 256 }
 257
 258 static void virgl_delete_blend_state(struct pipe_context *ctx,
 259                                      void *blend_state)
 260 {
 261    struct virgl_context *vctx = virgl_context(ctx);
 262    uint32_t handle = (unsigned long)blend_state;
 263    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_BLEND);
 264 }
 265
 266 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context *ctx,
 267                                                    const struct pipe_depth_stencil_alpha_state *blend_state)
 268 {
 269    struct virgl_context *vctx = virgl_context(ctx);
 270    uint32_t handle;
 271    handle = virgl_object_assign_handle();
 272
 273    virgl_encode_dsa_state(vctx, handle, blend_state);
 274    return (void *)(unsigned long)handle;
 275 }
 276
 277 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context *ctx,
 278                                                 void *blend_state)
 279 {
 280    struct virgl_context *vctx = virgl_context(ctx);
 281    uint32_t handle = (unsigned long)blend_state;
 282    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_DSA);
 283 }
 284
 285 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context *ctx,
 286                                                   void *dsa_state)
 287 {
 288    struct virgl_context *vctx = virgl_context(ctx);
 289    uint32_t handle = (unsigned long)dsa_state;
 290    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_DSA);
 291 }
 292
 293 static void *virgl_create_rasterizer_state(struct pipe_context *ctx,
 294                                                    const struct pipe_rasterizer_state *rs_state)
 295 {
 296    struct virgl_context *vctx = virgl_context(ctx);
 297    uint32_t handle;
 298    handle = virgl_object_assign_handle();
 299
 300    virgl_encode_rasterizer_state(vctx, handle, rs_state);
 301    return (void *)(unsigned long)handle;
 302 }
 303
 304 static void virgl_bind_rasterizer_state(struct pipe_context *ctx,
 305                                                 void *rs_state)
 306 {
 307    struct virgl_context *vctx = virgl_context(ctx);
 308    uint32_t handle = (unsigned long)rs_state;
 309
 310    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
 311 }
 312
 313 static void virgl_delete_rasterizer_state(struct pipe_context *ctx,
 314                                          void *rs_state)
 315 {
 316    struct virgl_context *vctx = virgl_context(ctx);
 317    uint32_t handle = (unsigned long)rs_state;
 318    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
 319 }
 320
 321 static void virgl_set_framebuffer_state(struct pipe_context *ctx,
 322                                                 const struct pipe_framebuffer_state *state)
 323 {
 324    struct virgl_context *vctx = virgl_context(ctx);
 325
 326    vctx->framebuffer = *state;
 327    virgl_encoder_set_framebuffer_state(vctx, state);
 328    virgl_attach_res_framebuffer(vctx);
 329 }
 330
 331 static void virgl_set_viewport_states(struct pipe_context *ctx,
 332                                      unsigned start_slot,
 333                                      unsigned num_viewports,
 334                                      const struct pipe_viewport_state *state)
 335 {
 336    struct virgl_context *vctx = virgl_context(ctx);
 337    virgl_encoder_set_viewport_states(vctx, start_slot, num_viewports, state);
 338 }
 339
 340 static void *virgl_create_vertex_elements_state(struct pipe_context *ctx,
 341                                                         unsigned num_elements,
 342                                                         const struct pipe_vertex_element *elements)
 343 {
 344    struct virgl_context *vctx = virgl_context(ctx);
 345    uint32_t handle = virgl_object_assign_handle();
 346    virgl_encoder_create_vertex_elements(vctx, handle,
 347                                        num_elements, elements);
 348    return (void*)(unsigned long)handle;
 349
 350 }
 351
 352 static void virgl_delete_vertex_elements_state(struct pipe_context *ctx,
 353                                               void *ve)
 354 {
 355    struct virgl_context *vctx = virgl_context(ctx);
 356    uint32_t handle = (unsigned long)ve;
 357
 358    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
 359 }
 360
 361 static void virgl_bind_vertex_elements_state(struct pipe_context *ctx,
 362                                                      void *ve)
 363 {
 364    struct virgl_context *vctx = virgl_context(ctx);
 365    uint32_t handle = (unsigned long)ve;
 366    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
 367 }
 368
 369 static void virgl_set_vertex_buffers(struct pipe_context *ctx,
 370                                     unsigned start_slot,
 371                                     unsigned num_buffers,
 372                                     const struct pipe_vertex_buffer *buffers)
 373 {
 374    struct virgl_context *vctx = virgl_context(ctx);
 375
 376    util_set_vertex_buffers_count(vctx->vertex_buffer,
 377                                  &vctx->num_vertex_buffers,
 378                                  buffers, start_slot, num_buffers);
 379
 380    vctx->vertex_array_dirty = TRUE;
 381 }
 382
 383 static void virgl_hw_set_vertex_buffers(struct pipe_context *ctx)
 384 {
 385    struct virgl_context *vctx = virgl_context(ctx);
 386
 387    if (vctx->vertex_array_dirty) {
 388       virgl_encoder_set_vertex_buffers(vctx, vctx->num_vertex_buffers, vctx->vertex_buffer);
 389       virgl_attach_res_vertex_buffers(vctx);
 390    }
 391 }
 392
 393 static void virgl_set_stencil_ref(struct pipe_context *ctx,
 394                                  const struct pipe_stencil_ref *ref)
 395 {
 396    struct virgl_context *vctx = virgl_context(ctx);
 397    virgl_encoder_set_stencil_ref(vctx, ref);
 398 }
 399
 400 static void virgl_set_blend_color(struct pipe_context *ctx,
 401                                  const struct pipe_blend_color *color)
 402 {
 403    struct virgl_context *vctx = virgl_context(ctx);
 404    virgl_encoder_set_blend_color(vctx, color);
 405 }
 406
 407 static void virgl_hw_set_index_buffer(struct pipe_context *ctx,
 408                                      struct virgl_indexbuf *ib)
 409 {
 410    struct virgl_context *vctx = virgl_context(ctx);
 411    virgl_encoder_set_index_buffer(vctx, ib);
 412    virgl_attach_res_index_buffer(vctx, ib);
 413 }
 414
 415 static void virgl_set_constant_buffer(struct pipe_context *ctx,
 416                                      enum pipe_shader_type shader, uint index,
 417                                      const struct pipe_constant_buffer *buf)
 418 {
 419    struct virgl_context *vctx = virgl_context(ctx);
 420
 421    if (buf) {
 422       if (!buf->user_buffer){
 423          struct virgl_resource *res = virgl_resource(buf->buffer);
 424          virgl_encoder_set_uniform_buffer(vctx, shader, index, buf->buffer_offset,
 425                                           buf->buffer_size, res);
 426          pipe_resource_reference(&vctx->ubos[shader][index], buf->buffer);
 427          return;
 428       }
 429       pipe_resource_reference(&vctx->ubos[shader][index], NULL);
 430       virgl_encoder_write_constant_buffer(vctx, shader, index, buf->buffer_size / 4, buf->user_buffer);
 431    } else {
 432       virgl_encoder_write_constant_buffer(vctx, shader, index, 0, NULL);
 433       pipe_resource_reference(&vctx->ubos[shader][index], NULL);
 434    }
 435 }
 436
 437 void virgl_transfer_inline_write(struct pipe_context *ctx,
 438                                 struct pipe_resource *res,
 439                                 unsigned level,
 440                                 unsigned usage,
 441                                 const struct pipe_box *box,
 442                                 const void *data,
 443                                 unsigned stride,
 444                                 unsigned layer_stride)
 445 {
 446    struct virgl_context *vctx = virgl_context(ctx);
 447    struct virgl_screen *vs = virgl_screen(ctx->screen);
 448    struct virgl_resource *grres = virgl_resource(res);
 449    struct virgl_buffer *vbuf = virgl_buffer(res);
 450
 451    grres->clean = FALSE;
 452
 453    if (virgl_res_needs_flush_wait(vctx, &vbuf->base, usage)) {
 454       ctx->flush(ctx, NULL, 0);
 455
 456       vs->vws->resource_wait(vs->vws, vbuf->base.hw_res);
 457    }
 458
 459    virgl_encoder_inline_write(vctx, grres, level, usage,
 460                               box, data, stride, layer_stride);
 461 }
 462
 463 static void *virgl_shader_encoder(struct pipe_context *ctx,
 464                                   const struct pipe_shader_state *shader,
 465                                   unsigned type)
 466 {
 467    struct virgl_context *vctx = virgl_context(ctx);
 468    uint32_t handle;
 469    struct tgsi_token *new_tokens;
 470    int ret;
 471
 472    new_tokens = virgl_tgsi_transform(vctx, shader->tokens);
 473    if (!new_tokens)
 474       return NULL;
 475
 476    handle = virgl_object_assign_handle();
 477    /* encode VS state */
 478    ret = virgl_encode_shader_state(vctx, handle, type,
 479                                    &shader->stream_output,
 480                                    new_tokens);
 481    if (ret) {
 482       return NULL;
 483    }
 484
 485    FREE(new_tokens);
 486    return (void *)(unsigned long)handle;
 487
 488 }
 489 static void *virgl_create_vs_state(struct pipe_context *ctx,
 490                                    const struct pipe_shader_state *shader)
 491 {
 492    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_VERTEX);
 493 }
 494
 495 static void *virgl_create_tcs_state(struct pipe_context *ctx,
 496                                    const struct pipe_shader_state *shader)
 497 {
 498    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_CTRL);
 499 }
 500
 501 static void *virgl_create_tes_state(struct pipe_context *ctx,
 502                                    const struct pipe_shader_state *shader)
 503 {
 504    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_EVAL);
 505 }
 506
 507 static void *virgl_create_gs_state(struct pipe_context *ctx,
 508                                    const struct pipe_shader_state *shader)
 509 {
 510    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_GEOMETRY);
 511 }
 512
 513 static void *virgl_create_fs_state(struct pipe_context *ctx,
 514                                    const struct pipe_shader_state *shader)
 515 {
 516    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_FRAGMENT);
 517 }
 518
 519 static void
 520 virgl_delete_fs_state(struct pipe_context *ctx,
 521                      void *fs)
 522 {
 523    uint32_t handle = (unsigned long)fs;
 524    struct virgl_context *vctx = virgl_context(ctx);
 525
 526    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 527 }
 528
 529 static void
 530 virgl_delete_gs_state(struct pipe_context *ctx,
 531                      void *gs)
 532 {
 533    uint32_t handle = (unsigned long)gs;
 534    struct virgl_context *vctx = virgl_context(ctx);
 535
 536    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 537 }
 538
 539 static void
 540 virgl_delete_vs_state(struct pipe_context *ctx,
 541                      void *vs)
 542 {
 543    uint32_t handle = (unsigned long)vs;
 544    struct virgl_context *vctx = virgl_context(ctx);
 545
 546    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 547 }
 548
 549 static void
 550 virgl_delete_tcs_state(struct pipe_context *ctx,
 551                        void *tcs)
 552 {
 553    uint32_t handle = (unsigned long)tcs;
 554    struct virgl_context *vctx = virgl_context(ctx);
 555
 556    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 557 }
 558
 559 static void
 560 virgl_delete_tes_state(struct pipe_context *ctx,
 561                       void *tes)
 562 {
 563    uint32_t handle = (unsigned long)tes;
 564    struct virgl_context *vctx = virgl_context(ctx);
 565
 566    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 567 }
 568
 569 static void virgl_bind_vs_state(struct pipe_context *ctx,
 570                                         void *vss)
 571 {
 572    uint32_t handle = (unsigned long)vss;
 573    struct virgl_context *vctx = virgl_context(ctx);
 574
 575    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_VERTEX);
 576 }
 577
 578 static void virgl_bind_tcs_state(struct pipe_context *ctx,
 579                                void *vss)
 580 {
 581    uint32_t handle = (unsigned long)vss;
 582    struct virgl_context *vctx = virgl_context(ctx);
 583
 584    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_CTRL);
 585 }
 586
 587 static void virgl_bind_tes_state(struct pipe_context *ctx,
 588                                void *vss)
 589 {
 590    uint32_t handle = (unsigned long)vss;
 591    struct virgl_context *vctx = virgl_context(ctx);
 592
 593    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_EVAL);
 594 }
 595
 596 static void virgl_bind_gs_state(struct pipe_context *ctx,
 597                                void *vss)
 598 {
 599    uint32_t handle = (unsigned long)vss;
 600    struct virgl_context *vctx = virgl_context(ctx);
 601
 602    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_GEOMETRY);
 603 }
 604
 605
 606 static void virgl_bind_fs_state(struct pipe_context *ctx,
 607                                         void *vss)
 608 {
 609    uint32_t handle = (unsigned long)vss;
 610    struct virgl_context *vctx = virgl_context(ctx);
 611
 612    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_FRAGMENT);
 613 }
 614
 615 static void virgl_clear(struct pipe_context *ctx,
 616                                 unsigned buffers,
 617                                 const union pipe_color_union *color,
 618                                 double depth, unsigned stencil)
 619 {
 620    struct virgl_context *vctx = virgl_context(ctx);
 621
 622    virgl_encode_clear(vctx, buffers, color, depth, stencil);
 623 }
 624
 625 static void virgl_draw_vbo(struct pipe_context *ctx,
 626                                    const struct pipe_draw_info *dinfo)
 627 {
 628    struct virgl_context *vctx = virgl_context(ctx);
 629    struct virgl_screen *rs = virgl_screen(ctx->screen);
 630    struct virgl_indexbuf ib = {};
 631    struct pipe_draw_info info = *dinfo;
 632
 633    if (!dinfo->count_from_stream_output && !dinfo->indirect &&
 634        !dinfo->primitive_restart &&
 635        !u_trim_pipe_prim(dinfo->mode, (unsigned*)&dinfo->count))
 636       return;
 637
 638    if (!(rs->caps.caps.v1.prim_mask & (1 << dinfo->mode))) {
 639       util_primconvert_draw_vbo(vctx->primconvert, dinfo);
 640       return;
 641    }
 642    if (info.index_size) {
 643            pipe_resource_reference(&ib.buffer, info.has_user_indices ? NULL : info.index.resource);
 644            ib.user_buffer = info.has_user_indices ? info.index.user : NULL;
 645            ib.index_size = dinfo->index_size;
 646            ib.offset = info.start * ib.index_size;
 647
 648            if (ib.user_buffer) {
 649                    u_upload_data(vctx->uploader, 0, info.count * ib.index_size, 256,
 650                                  ib.user_buffer, &ib.offset, &ib.buffer);
 651                    ib.user_buffer = NULL;
 652            }
 653    }
 654
 655    u_upload_unmap(vctx->uploader);
 656
 657    vctx->num_draws++;
 658    virgl_hw_set_vertex_buffers(ctx);
 659    if (info.index_size)
 660       virgl_hw_set_index_buffer(ctx, &ib);
 661
 662    virgl_encoder_draw_vbo(vctx, &info);
 663
 664    pipe_resource_reference(&ib.buffer, NULL);
 665
 666 }
 667
 668 static void virgl_flush_eq(struct virgl_context *ctx, void *closure)
 669 {
 670    struct virgl_screen *rs = virgl_screen(ctx->base.screen);
 671
 672    /* send the buffer to the remote side for decoding */
 673    ctx->num_transfers = ctx->num_draws = 0;
 674    rs->vws->submit_cmd(rs->vws, ctx->cbuf);
 675
 676    virgl_encoder_set_sub_ctx(ctx, ctx->hw_sub_ctx_id);
 677
 678    /* add back current framebuffer resources to reference list? */
 679    virgl_reemit_res(ctx);
 680 }
 681
 682 static void virgl_flush_from_st(struct pipe_context *ctx,
 683                                struct pipe_fence_handle **fence,
 684                                enum pipe_flush_flags flags)
 685 {
 686    struct virgl_context *vctx = virgl_context(ctx);
 687    struct virgl_screen *rs = virgl_screen(ctx->screen);
 688    struct virgl_buffer *buf, *tmp;
 689
 690    if (fence)
 691       *fence = rs->vws->cs_create_fence(rs->vws);
 692
 693    LIST_FOR_EACH_ENTRY_SAFE(buf, tmp, &vctx->to_flush_bufs, flush_list) {
 694       struct pipe_resource *res = &buf->base.u.b;
 695       virgl_buffer_flush(vctx, buf);
 696       list_del(&buf->flush_list);
 697       buf->on_list = FALSE;
 698       pipe_resource_reference(&res, NULL);
 699
 700    }
 701    virgl_flush_eq(vctx, vctx);
 702 }
 703
 704 static struct pipe_sampler_view *virgl_create_sampler_view(struct pipe_context *ctx,
 705                                       struct pipe_resource *texture,
 706                                       const struct pipe_sampler_view *state)
 707 {
 708    struct virgl_context *vctx = virgl_context(ctx);
 709    struct virgl_sampler_view *grview;
 710    uint32_t handle;
 711    struct virgl_resource *res;
 712
 713    if (!state)
 714       return NULL;
 715
 716    grview = CALLOC_STRUCT(virgl_sampler_view);
 717    if (!grview)
 718       return NULL;
 719
 720    res = virgl_resource(texture);
 721    handle = virgl_object_assign_handle();
 722    virgl_encode_sampler_view(vctx, handle, res, state);
 723
 724    grview->base = *state;
 725    grview->base.reference.count = 1;
 726
 727    grview->base.texture = NULL;
 728    grview->base.context = ctx;
 729    pipe_resource_reference(&grview->base.texture, texture);
 730    grview->handle = handle;
 731    return &grview->base;
 732 }
 733
 734 static void virgl_set_sampler_views(struct pipe_context *ctx,
 735                                    enum pipe_shader_type shader_type,
 736                                    unsigned start_slot,
 737                                    unsigned num_views,
 738                                    struct pipe_sampler_view **views)
 739 {
 740    struct virgl_context *vctx = virgl_context(ctx);
 741    int i;
 742    uint32_t disable_mask = ~((1ull << num_views) - 1);
 743    struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
 744    uint32_t new_mask = 0;
 745    uint32_t remaining_mask;
 746
 747    remaining_mask = tinfo->enabled_mask & disable_mask;
 748
 749    while (remaining_mask) {
 750       i = u_bit_scan(&remaining_mask);
 751       assert(tinfo->views[i]);
 752
 753       pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
 754    }
 755
 756    for (i = 0; i < num_views; i++) {
 757       struct virgl_sampler_view *grview = virgl_sampler_view(views[i]);
 758
 759       if (views[i] == (struct pipe_sampler_view *)tinfo->views[i])
 760          continue;
 761
 762       if (grview) {
 763          new_mask |= 1 << i;
 764          pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], views[i]);
 765       } else {
 766          pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
 767          disable_mask |= 1 << i;
 768       }
 769    }
 770
 771    tinfo->enabled_mask &= ~disable_mask;
 772    tinfo->enabled_mask |= new_mask;
 773    virgl_encode_set_sampler_views(vctx, shader_type, start_slot, num_views, tinfo->views);
 774    virgl_attach_res_sampler_views(vctx, shader_type);
 775 }
 776
 777 static void virgl_destroy_sampler_view(struct pipe_context *ctx,
 778                                  struct pipe_sampler_view *view)
 779 {
 780    struct virgl_context *vctx = virgl_context(ctx);
 781    struct virgl_sampler_view *grview = virgl_sampler_view(view);
 782
 783    virgl_encode_delete_object(vctx, grview->handle, VIRGL_OBJECT_SAMPLER_VIEW);
 784    pipe_resource_reference(&view->texture, NULL);
 785    FREE(view);
 786 }
 787
 788 static void *virgl_create_sampler_state(struct pipe_context *ctx,
 789                                         const struct pipe_sampler_state *state)
 790 {
 791    struct virgl_context *vctx = virgl_context(ctx);
 792    uint32_t handle;
 793
 794    handle = virgl_object_assign_handle();
 795
 796    virgl_encode_sampler_state(vctx, handle, state);
 797    return (void *)(unsigned long)handle;
 798 }
 799
 800 static void virgl_delete_sampler_state(struct pipe_context *ctx,
 801                                       void *ss)
 802 {
 803    struct virgl_context *vctx = virgl_context(ctx);
 804    uint32_t handle = (unsigned long)ss;
 805
 806    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SAMPLER_STATE);
 807 }
 808
 809 static void virgl_bind_sampler_states(struct pipe_context *ctx,
 810                                      enum pipe_shader_type shader,
 811                                      unsigned start_slot,
 812                                      unsigned num_samplers,
 813                                      void **samplers)
 814 {
 815    struct virgl_context *vctx = virgl_context(ctx);
 816    uint32_t handles[32];
 817    int i;
 818    for (i = 0; i < num_samplers; i++) {
 819       handles[i] = (unsigned long)(samplers[i]);
 820    }
 821    virgl_encode_bind_sampler_states(vctx, shader, start_slot, num_samplers, handles);
 822 }
 823
 824 static void virgl_set_polygon_stipple(struct pipe_context *ctx,
 825                                      const struct pipe_poly_stipple *ps)
 826 {
 827    struct virgl_context *vctx = virgl_context(ctx);
 828    virgl_encoder_set_polygon_stipple(vctx, ps);
 829 }
 830
 831 static void virgl_set_scissor_states(struct pipe_context *ctx,
 832                                     unsigned start_slot,
 833                                     unsigned num_scissor,
 834                                    const struct pipe_scissor_state *ss)
 835 {
 836    struct virgl_context *vctx = virgl_context(ctx);
 837    virgl_encoder_set_scissor_state(vctx, start_slot, num_scissor, ss);
 838 }
 839
 840 static void virgl_set_sample_mask(struct pipe_context *ctx,
 841                                  unsigned sample_mask)
 842 {
 843    struct virgl_context *vctx = virgl_context(ctx);
 844    virgl_encoder_set_sample_mask(vctx, sample_mask);
 845 }
 846
 847 static void virgl_set_min_samples(struct pipe_context *ctx,
 848                                  unsigned min_samples)
 849 {
 850    struct virgl_context *vctx = virgl_context(ctx);
 851    struct virgl_screen *rs = virgl_screen(ctx->screen);
 852
 853    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_SET_MIN_SAMPLES))
 854       return;
 855    virgl_encoder_set_min_samples(vctx, min_samples);
 856 }
 857
 858 static void virgl_set_clip_state(struct pipe_context *ctx,
 859                                 const struct pipe_clip_state *clip)
 860 {
 861    struct virgl_context *vctx = virgl_context(ctx);
 862    virgl_encoder_set_clip_state(vctx, clip);
 863 }
 864
 865 static void virgl_set_tess_state(struct pipe_context *ctx,
 866                                  const float default_outer_level[4],
 867                                  const float default_inner_level[2])
 868 {
 869    struct virgl_context *vctx = virgl_context(ctx);
 870    struct virgl_screen *rs = virgl_screen(ctx->screen);
 871
 872    if (!rs->caps.caps.v1.bset.has_tessellation_shaders)
 873       return;
 874    virgl_encode_set_tess_state(vctx, default_outer_level, default_inner_level);
 875 }
 876
 877 static void virgl_resource_copy_region(struct pipe_context *ctx,
 878                                       struct pipe_resource *dst,
 879                                       unsigned dst_level,
 880                                       unsigned dstx, unsigned dsty, unsigned dstz,
 881                                       struct pipe_resource *src,
 882                                       unsigned src_level,
 883                                       const struct pipe_box *src_box)
 884 {
 885    struct virgl_context *vctx = virgl_context(ctx);
 886    struct virgl_resource *dres = virgl_resource(dst);
 887    struct virgl_resource *sres = virgl_resource(src);
 888
 889    dres->clean = FALSE;
 890    virgl_encode_resource_copy_region(vctx, dres,
 891                                     dst_level, dstx, dsty, dstz,
 892                                     sres, src_level,
 893                                     src_box);
 894 }
 895
 896 static void
 897 virgl_flush_resource(struct pipe_context *pipe,
 898                     struct pipe_resource *resource)
 899 {
 900 }
 901
 902 static void virgl_blit(struct pipe_context *ctx,
 903                       const struct pipe_blit_info *blit)
 904 {
 905    struct virgl_context *vctx = virgl_context(ctx);
 906    struct virgl_resource *dres = virgl_resource(blit->dst.resource);
 907    struct virgl_resource *sres = virgl_resource(blit->src.resource);
 908
 909    dres->clean = FALSE;
 910    virgl_encode_blit(vctx, dres, sres,
 911                     blit);
 912 }
 913
 914 static void
 915 virgl_context_destroy( struct pipe_context *ctx )
 916 {
 917    struct virgl_context *vctx = virgl_context(ctx);
 918    struct virgl_screen *rs = virgl_screen(ctx->screen);
 919
 920    vctx->framebuffer.zsbuf = NULL;
 921    vctx->framebuffer.nr_cbufs = 0;
 922    virgl_encoder_destroy_sub_ctx(vctx, vctx->hw_sub_ctx_id);
 923    virgl_flush_eq(vctx, vctx);
 924
 925    rs->vws->cmd_buf_destroy(vctx->cbuf);
 926    if (vctx->uploader)
 927       u_upload_destroy(vctx->uploader);
 928    util_primconvert_destroy(vctx->primconvert);
 929
 930    slab_destroy_child(&vctx->texture_transfer_pool);
 931    FREE(vctx);
 932 }
 933
 934 static void virgl_get_sample_position(struct pipe_context *ctx,
 935                                       unsigned sample_count,
 936                                       unsigned index,
 937                                       float *out_value)
 938 {
 939    struct virgl_context *vctx = virgl_context(ctx);
 940    struct virgl_screen *vs = virgl_screen(vctx->base.screen);
 941
 942    if (sample_count > vs->caps.caps.v1.max_samples) {
 943       debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
 944                    sample_count, vs->caps.caps.v1.max_samples);
 945       return;
 946    }
 947
 948    /* The following is basically copied from dri/i965gen6_get_sample_position
 949     * The only addition is that we hold the msaa positions for all sample
 950     * counts in a flat array. */
 951    uint32_t bits = 0;
 952    if (sample_count == 1) {
 953       out_value[0] = out_value[1] = 0.5f;
 954       return;
 955    } else if (sample_count == 2) {
 956       bits = vs->caps.caps.v2.msaa_sample_positions[0] >> (8 * index);
 957    } else if (sample_count <= 4) {
 958       bits = vs->caps.caps.v2.msaa_sample_positions[1] >> (8 * index);
 959    } else if (sample_count <= 8) {
 960       bits = vs->caps.caps.v2.msaa_sample_positions[2 + (index >> 2)] >> (8 * (index & 3));
 961    } else if (sample_count <= 16) {
 962       bits = vs->caps.caps.v2.msaa_sample_positions[4 + (index >> 2)] >> (8 * (index & 3));
 963    }
 964    out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
 965    out_value[1] = (bits & 0xf) / 16.0f;
 966    debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
 967                 index, sample_count, out_value[0], out_value[1]);
 968 }
 969
 970 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
 971                                           void *priv,
 972                                           unsigned flags)
 973 {
 974    struct virgl_context *vctx;
 975    struct virgl_screen *rs = virgl_screen(pscreen);
 976    vctx = CALLOC_STRUCT(virgl_context);
 977
 978    vctx->cbuf = rs->vws->cmd_buf_create(rs->vws);
 979    if (!vctx->cbuf) {
 980       FREE(vctx);
 981       return NULL;
 982    }
 983
 984    vctx->base.destroy = virgl_context_destroy;
 985    vctx->base.create_surface = virgl_create_surface;
 986    vctx->base.surface_destroy = virgl_surface_destroy;
 987    vctx->base.set_framebuffer_state = virgl_set_framebuffer_state;
 988    vctx->base.create_blend_state = virgl_create_blend_state;
 989    vctx->base.bind_blend_state = virgl_bind_blend_state;
 990    vctx->base.delete_blend_state = virgl_delete_blend_state;
 991    vctx->base.create_depth_stencil_alpha_state = virgl_create_depth_stencil_alpha_state;
 992    vctx->base.bind_depth_stencil_alpha_state = virgl_bind_depth_stencil_alpha_state;
 993    vctx->base.delete_depth_stencil_alpha_state = virgl_delete_depth_stencil_alpha_state;
 994    vctx->base.create_rasterizer_state = virgl_create_rasterizer_state;
 995    vctx->base.bind_rasterizer_state = virgl_bind_rasterizer_state;
 996    vctx->base.delete_rasterizer_state = virgl_delete_rasterizer_state;
 997
 998    vctx->base.set_viewport_states = virgl_set_viewport_states;
 999    vctx->base.create_vertex_elements_state = virgl_create_vertex_elements_state;
1000    vctx->base.bind_vertex_elements_state = virgl_bind_vertex_elements_state;
1001    vctx->base.delete_vertex_elements_state = virgl_delete_vertex_elements_state;
1002    vctx->base.set_vertex_buffers = virgl_set_vertex_buffers;
1003    vctx->base.set_constant_buffer = virgl_set_constant_buffer;
1004
1005    vctx->base.set_tess_state = virgl_set_tess_state;
1006    vctx->base.create_vs_state = virgl_create_vs_state;
1007    vctx->base.create_tcs_state = virgl_create_tcs_state;
1008    vctx->base.create_tes_state = virgl_create_tes_state;
1009    vctx->base.create_gs_state = virgl_create_gs_state;
1010    vctx->base.create_fs_state = virgl_create_fs_state;
1011
1012    vctx->base.bind_vs_state = virgl_bind_vs_state;
1013    vctx->base.bind_tcs_state = virgl_bind_tcs_state;
1014    vctx->base.bind_tes_state = virgl_bind_tes_state;
1015    vctx->base.bind_gs_state = virgl_bind_gs_state;
1016    vctx->base.bind_fs_state = virgl_bind_fs_state;
1017
1018    vctx->base.delete_vs_state = virgl_delete_vs_state;
1019    vctx->base.delete_tcs_state = virgl_delete_tcs_state;
1020    vctx->base.delete_tes_state = virgl_delete_tes_state;
1021    vctx->base.delete_gs_state = virgl_delete_gs_state;
1022    vctx->base.delete_fs_state = virgl_delete_fs_state;
1023
1024    vctx->base.clear = virgl_clear;
1025    vctx->base.draw_vbo = virgl_draw_vbo;
1026    vctx->base.flush = virgl_flush_from_st;
1027    vctx->base.screen = pscreen;
1028    vctx->base.create_sampler_view = virgl_create_sampler_view;
1029    vctx->base.sampler_view_destroy = virgl_destroy_sampler_view;
1030    vctx->base.set_sampler_views = virgl_set_sampler_views;
1031
1032    vctx->base.create_sampler_state = virgl_create_sampler_state;
1033    vctx->base.delete_sampler_state = virgl_delete_sampler_state;
1034    vctx->base.bind_sampler_states = virgl_bind_sampler_states;
1035
1036    vctx->base.set_polygon_stipple = virgl_set_polygon_stipple;
1037    vctx->base.set_scissor_states = virgl_set_scissor_states;
1038    vctx->base.set_sample_mask = virgl_set_sample_mask;
1039    vctx->base.set_min_samples = virgl_set_min_samples;
1040    vctx->base.set_stencil_ref = virgl_set_stencil_ref;
1041    vctx->base.set_clip_state = virgl_set_clip_state;
1042
1043    vctx->base.set_blend_color = virgl_set_blend_color;
1044
1045    vctx->base.get_sample_position = virgl_get_sample_position;
1046
1047    vctx->base.resource_copy_region = virgl_resource_copy_region;
1048    vctx->base.flush_resource = virgl_flush_resource;
1049    vctx->base.blit =  virgl_blit;
1050
1051    virgl_init_context_resource_functions(&vctx->base);
1052    virgl_init_query_functions(vctx);
1053    virgl_init_so_functions(vctx);
1054
1055    list_inithead(&vctx->to_flush_bufs);
1056    slab_create_child(&vctx->texture_transfer_pool, &rs->texture_transfer_pool);
1057
1058    vctx->primconvert = util_primconvert_create(&vctx->base, rs->caps.caps.v1.prim_mask);
1059    vctx->uploader = u_upload_create(&vctx->base, 1024 * 1024,
1060                                      PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM, 0);
1061    if (!vctx->uploader)
1062            goto fail;
1063    vctx->base.stream_uploader = vctx->uploader;
1064    vctx->base.const_uploader = vctx->uploader;
1065
1066    vctx->hw_sub_ctx_id = rs->sub_ctx_id++;
1067    virgl_encoder_create_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1068
1069    virgl_encoder_set_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1070    return &vctx->base;
1071 fail:
1072    return NULL;
1073 }