virgl: simplify virgl_hw_set_index_buffer
[mesa.git] / src / gallium / drivers / virgl / virgl_context.c
1 /*
2 * Copyright 2014, 2015 Red Hat.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <libsync.h>
25 #include "pipe/p_shader_tokens.h"
26
27 #include "pipe/p_context.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31 #include "util/u_inlines.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_prim.h"
35 #include "util/u_transfer.h"
36 #include "util/u_helpers.h"
37 #include "util/slab.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_blitter.h"
40 #include "tgsi/tgsi_text.h"
41 #include "indices/u_primconvert.h"
42
43 #include "pipebuffer/pb_buffer.h"
44
45 #include "virgl_encode.h"
46 #include "virgl_context.h"
47 #include "virgl_protocol.h"
48 #include "virgl_resource.h"
49 #include "virgl_screen.h"
50
51 static uint32_t next_handle;
52 uint32_t virgl_object_assign_handle(void)
53 {
54 return ++next_handle;
55 }
56
57 static void virgl_buffer_flush(struct virgl_context *vctx,
58 struct virgl_buffer *vbuf)
59 {
60 struct virgl_screen *rs = virgl_screen(vctx->base.screen);
61 struct pipe_box box;
62
63 assert(vbuf->on_list);
64
65 box.height = 1;
66 box.depth = 1;
67 box.y = 0;
68 box.z = 0;
69
70 box.x = vbuf->valid_buffer_range.start;
71 box.width = MIN2(vbuf->valid_buffer_range.end - vbuf->valid_buffer_range.start, vbuf->base.u.b.width0);
72
73 vctx->num_transfers++;
74 rs->vws->transfer_put(rs->vws, vbuf->base.hw_res,
75 &box, 0, 0, box.x, 0);
76
77 util_range_set_empty(&vbuf->valid_buffer_range);
78 }
79
80 static void virgl_attach_res_framebuffer(struct virgl_context *vctx)
81 {
82 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
83 struct pipe_surface *surf;
84 struct virgl_resource *res;
85 unsigned i;
86
87 surf = vctx->framebuffer.zsbuf;
88 if (surf) {
89 res = virgl_resource(surf->texture);
90 if (res)
91 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
92 }
93 for (i = 0; i < vctx->framebuffer.nr_cbufs; i++) {
94 surf = vctx->framebuffer.cbufs[i];
95 if (surf) {
96 res = virgl_resource(surf->texture);
97 if (res)
98 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
99 }
100 }
101 }
102
103 static void virgl_attach_res_sampler_views(struct virgl_context *vctx,
104 enum pipe_shader_type shader_type)
105 {
106 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
107 struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
108 struct virgl_resource *res;
109 uint32_t remaining_mask = tinfo->enabled_mask;
110 unsigned i;
111 while (remaining_mask) {
112 i = u_bit_scan(&remaining_mask);
113 assert(tinfo->views[i]);
114
115 res = virgl_resource(tinfo->views[i]->base.texture);
116 if (res)
117 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
118 }
119 }
120
121 static void virgl_attach_res_vertex_buffers(struct virgl_context *vctx)
122 {
123 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
124 struct virgl_resource *res;
125 unsigned i;
126
127 for (i = 0; i < vctx->num_vertex_buffers; i++) {
128 res = virgl_resource(vctx->vertex_buffer[i].buffer.resource);
129 if (res)
130 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
131 }
132 }
133
134 static void virgl_attach_res_index_buffer(struct virgl_context *vctx,
135 struct virgl_indexbuf *ib)
136 {
137 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
138 struct virgl_resource *res;
139
140 res = virgl_resource(ib->buffer);
141 if (res)
142 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
143 }
144
145 static void virgl_attach_res_so_targets(struct virgl_context *vctx)
146 {
147 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
148 struct virgl_resource *res;
149 unsigned i;
150
151 for (i = 0; i < vctx->num_so_targets; i++) {
152 res = virgl_resource(vctx->so_targets[i].base.buffer);
153 if (res)
154 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
155 }
156 }
157
158 static void virgl_attach_res_uniform_buffers(struct virgl_context *vctx,
159 enum pipe_shader_type shader_type)
160 {
161 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
162 struct virgl_resource *res;
163 unsigned i;
164 for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
165 res = virgl_resource(vctx->ubos[shader_type][i]);
166 if (res) {
167 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
168 }
169 }
170 }
171
172 static void virgl_attach_res_shader_buffers(struct virgl_context *vctx,
173 enum pipe_shader_type shader_type)
174 {
175 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
176 struct virgl_resource *res;
177 unsigned i;
178 for (i = 0; i < PIPE_MAX_SHADER_BUFFERS; i++) {
179 res = virgl_resource(vctx->ssbos[shader_type][i]);
180 if (res) {
181 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
182 }
183 }
184 }
185
186 static void virgl_attach_res_shader_images(struct virgl_context *vctx,
187 enum pipe_shader_type shader_type)
188 {
189 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
190 struct virgl_resource *res;
191 unsigned i;
192 for (i = 0; i < PIPE_MAX_SHADER_IMAGES; i++) {
193 res = virgl_resource(vctx->images[shader_type][i]);
194 if (res) {
195 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
196 }
197 }
198 }
199
200 static void virgl_attach_res_atomic_buffers(struct virgl_context *vctx)
201 {
202 struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
203 struct virgl_resource *res;
204 unsigned i;
205 for (i = 0; i < PIPE_MAX_HW_ATOMIC_BUFFERS; i++) {
206 res = virgl_resource(vctx->atomic_buffers[i]);
207 if (res) {
208 vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
209 }
210 }
211 }
212
213 /*
214 * after flushing, the hw context still has a bunch of
215 * resources bound, so we need to rebind those here.
216 */
217 static void virgl_reemit_res(struct virgl_context *vctx)
218 {
219 enum pipe_shader_type shader_type;
220
221 /* reattach any flushed resources */
222 /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
223 virgl_attach_res_framebuffer(vctx);
224
225 for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
226 virgl_attach_res_sampler_views(vctx, shader_type);
227 virgl_attach_res_uniform_buffers(vctx, shader_type);
228 virgl_attach_res_shader_buffers(vctx, shader_type);
229 virgl_attach_res_shader_images(vctx, shader_type);
230 }
231 virgl_attach_res_atomic_buffers(vctx);
232 virgl_attach_res_vertex_buffers(vctx);
233 virgl_attach_res_so_targets(vctx);
234 }
235
236 static struct pipe_surface *virgl_create_surface(struct pipe_context *ctx,
237 struct pipe_resource *resource,
238 const struct pipe_surface *templ)
239 {
240 struct virgl_context *vctx = virgl_context(ctx);
241 struct virgl_surface *surf;
242 struct virgl_resource *res = virgl_resource(resource);
243 uint32_t handle;
244
245 surf = CALLOC_STRUCT(virgl_surface);
246 if (!surf)
247 return NULL;
248
249 res->clean = FALSE;
250 handle = virgl_object_assign_handle();
251 pipe_reference_init(&surf->base.reference, 1);
252 pipe_resource_reference(&surf->base.texture, resource);
253 surf->base.context = ctx;
254 surf->base.format = templ->format;
255 if (resource->target != PIPE_BUFFER) {
256 surf->base.width = u_minify(resource->width0, templ->u.tex.level);
257 surf->base.height = u_minify(resource->height0, templ->u.tex.level);
258 surf->base.u.tex.level = templ->u.tex.level;
259 surf->base.u.tex.first_layer = templ->u.tex.first_layer;
260 surf->base.u.tex.last_layer = templ->u.tex.last_layer;
261 } else {
262 surf->base.width = templ->u.buf.last_element - templ->u.buf.first_element + 1;
263 surf->base.height = resource->height0;
264 surf->base.u.buf.first_element = templ->u.buf.first_element;
265 surf->base.u.buf.last_element = templ->u.buf.last_element;
266 }
267 virgl_encoder_create_surface(vctx, handle, res, &surf->base);
268 surf->handle = handle;
269 return &surf->base;
270 }
271
272 static void virgl_surface_destroy(struct pipe_context *ctx,
273 struct pipe_surface *psurf)
274 {
275 struct virgl_context *vctx = virgl_context(ctx);
276 struct virgl_surface *surf = virgl_surface(psurf);
277
278 pipe_resource_reference(&surf->base.texture, NULL);
279 virgl_encode_delete_object(vctx, surf->handle, VIRGL_OBJECT_SURFACE);
280 FREE(surf);
281 }
282
283 static void *virgl_create_blend_state(struct pipe_context *ctx,
284 const struct pipe_blend_state *blend_state)
285 {
286 struct virgl_context *vctx = virgl_context(ctx);
287 uint32_t handle;
288 handle = virgl_object_assign_handle();
289
290 virgl_encode_blend_state(vctx, handle, blend_state);
291 return (void *)(unsigned long)handle;
292
293 }
294
295 static void virgl_bind_blend_state(struct pipe_context *ctx,
296 void *blend_state)
297 {
298 struct virgl_context *vctx = virgl_context(ctx);
299 uint32_t handle = (unsigned long)blend_state;
300 virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_BLEND);
301 }
302
303 static void virgl_delete_blend_state(struct pipe_context *ctx,
304 void *blend_state)
305 {
306 struct virgl_context *vctx = virgl_context(ctx);
307 uint32_t handle = (unsigned long)blend_state;
308 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_BLEND);
309 }
310
311 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context *ctx,
312 const struct pipe_depth_stencil_alpha_state *blend_state)
313 {
314 struct virgl_context *vctx = virgl_context(ctx);
315 uint32_t handle;
316 handle = virgl_object_assign_handle();
317
318 virgl_encode_dsa_state(vctx, handle, blend_state);
319 return (void *)(unsigned long)handle;
320 }
321
322 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context *ctx,
323 void *blend_state)
324 {
325 struct virgl_context *vctx = virgl_context(ctx);
326 uint32_t handle = (unsigned long)blend_state;
327 virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_DSA);
328 }
329
330 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context *ctx,
331 void *dsa_state)
332 {
333 struct virgl_context *vctx = virgl_context(ctx);
334 uint32_t handle = (unsigned long)dsa_state;
335 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_DSA);
336 }
337
338 static void *virgl_create_rasterizer_state(struct pipe_context *ctx,
339 const struct pipe_rasterizer_state *rs_state)
340 {
341 struct virgl_context *vctx = virgl_context(ctx);
342 uint32_t handle;
343 handle = virgl_object_assign_handle();
344
345 virgl_encode_rasterizer_state(vctx, handle, rs_state);
346 return (void *)(unsigned long)handle;
347 }
348
349 static void virgl_bind_rasterizer_state(struct pipe_context *ctx,
350 void *rs_state)
351 {
352 struct virgl_context *vctx = virgl_context(ctx);
353 uint32_t handle = (unsigned long)rs_state;
354
355 virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
356 }
357
358 static void virgl_delete_rasterizer_state(struct pipe_context *ctx,
359 void *rs_state)
360 {
361 struct virgl_context *vctx = virgl_context(ctx);
362 uint32_t handle = (unsigned long)rs_state;
363 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
364 }
365
366 static void virgl_set_framebuffer_state(struct pipe_context *ctx,
367 const struct pipe_framebuffer_state *state)
368 {
369 struct virgl_context *vctx = virgl_context(ctx);
370
371 vctx->framebuffer = *state;
372 virgl_encoder_set_framebuffer_state(vctx, state);
373 virgl_attach_res_framebuffer(vctx);
374 }
375
376 static void virgl_set_viewport_states(struct pipe_context *ctx,
377 unsigned start_slot,
378 unsigned num_viewports,
379 const struct pipe_viewport_state *state)
380 {
381 struct virgl_context *vctx = virgl_context(ctx);
382 virgl_encoder_set_viewport_states(vctx, start_slot, num_viewports, state);
383 }
384
385 static void *virgl_create_vertex_elements_state(struct pipe_context *ctx,
386 unsigned num_elements,
387 const struct pipe_vertex_element *elements)
388 {
389 struct virgl_context *vctx = virgl_context(ctx);
390 uint32_t handle = virgl_object_assign_handle();
391 virgl_encoder_create_vertex_elements(vctx, handle,
392 num_elements, elements);
393 return (void*)(unsigned long)handle;
394
395 }
396
397 static void virgl_delete_vertex_elements_state(struct pipe_context *ctx,
398 void *ve)
399 {
400 struct virgl_context *vctx = virgl_context(ctx);
401 uint32_t handle = (unsigned long)ve;
402
403 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
404 }
405
406 static void virgl_bind_vertex_elements_state(struct pipe_context *ctx,
407 void *ve)
408 {
409 struct virgl_context *vctx = virgl_context(ctx);
410 uint32_t handle = (unsigned long)ve;
411 virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
412 }
413
414 static void virgl_set_vertex_buffers(struct pipe_context *ctx,
415 unsigned start_slot,
416 unsigned num_buffers,
417 const struct pipe_vertex_buffer *buffers)
418 {
419 struct virgl_context *vctx = virgl_context(ctx);
420
421 util_set_vertex_buffers_count(vctx->vertex_buffer,
422 &vctx->num_vertex_buffers,
423 buffers, start_slot, num_buffers);
424
425 vctx->vertex_array_dirty = TRUE;
426 }
427
428 static void virgl_hw_set_vertex_buffers(struct virgl_context *vctx)
429 {
430 if (vctx->vertex_array_dirty) {
431 virgl_encoder_set_vertex_buffers(vctx, vctx->num_vertex_buffers, vctx->vertex_buffer);
432 virgl_attach_res_vertex_buffers(vctx);
433 }
434 }
435
436 static void virgl_set_stencil_ref(struct pipe_context *ctx,
437 const struct pipe_stencil_ref *ref)
438 {
439 struct virgl_context *vctx = virgl_context(ctx);
440 virgl_encoder_set_stencil_ref(vctx, ref);
441 }
442
443 static void virgl_set_blend_color(struct pipe_context *ctx,
444 const struct pipe_blend_color *color)
445 {
446 struct virgl_context *vctx = virgl_context(ctx);
447 virgl_encoder_set_blend_color(vctx, color);
448 }
449
450 static void virgl_hw_set_index_buffer(struct virgl_context *vctx,
451 struct virgl_indexbuf *ib)
452 {
453 virgl_encoder_set_index_buffer(vctx, ib);
454 virgl_attach_res_index_buffer(vctx, ib);
455 }
456
457 static void virgl_set_constant_buffer(struct pipe_context *ctx,
458 enum pipe_shader_type shader, uint index,
459 const struct pipe_constant_buffer *buf)
460 {
461 struct virgl_context *vctx = virgl_context(ctx);
462
463 if (buf) {
464 if (!buf->user_buffer){
465 struct virgl_resource *res = virgl_resource(buf->buffer);
466 virgl_encoder_set_uniform_buffer(vctx, shader, index, buf->buffer_offset,
467 buf->buffer_size, res);
468 pipe_resource_reference(&vctx->ubos[shader][index], buf->buffer);
469 return;
470 }
471 pipe_resource_reference(&vctx->ubos[shader][index], NULL);
472 virgl_encoder_write_constant_buffer(vctx, shader, index, buf->buffer_size / 4, buf->user_buffer);
473 } else {
474 virgl_encoder_write_constant_buffer(vctx, shader, index, 0, NULL);
475 pipe_resource_reference(&vctx->ubos[shader][index], NULL);
476 }
477 }
478
479 void virgl_transfer_inline_write(struct pipe_context *ctx,
480 struct pipe_resource *res,
481 unsigned level,
482 unsigned usage,
483 const struct pipe_box *box,
484 const void *data,
485 unsigned stride,
486 unsigned layer_stride)
487 {
488 struct virgl_context *vctx = virgl_context(ctx);
489 struct virgl_screen *vs = virgl_screen(ctx->screen);
490 struct virgl_resource *grres = virgl_resource(res);
491 struct virgl_buffer *vbuf = virgl_buffer(res);
492
493 grres->clean = FALSE;
494
495 if (virgl_res_needs_flush_wait(vctx, &vbuf->base, usage)) {
496 ctx->flush(ctx, NULL, 0);
497
498 vs->vws->resource_wait(vs->vws, vbuf->base.hw_res);
499 }
500
501 virgl_encoder_inline_write(vctx, grres, level, usage,
502 box, data, stride, layer_stride);
503 }
504
505 static void *virgl_shader_encoder(struct pipe_context *ctx,
506 const struct pipe_shader_state *shader,
507 unsigned type)
508 {
509 struct virgl_context *vctx = virgl_context(ctx);
510 uint32_t handle;
511 struct tgsi_token *new_tokens;
512 int ret;
513
514 new_tokens = virgl_tgsi_transform(vctx, shader->tokens);
515 if (!new_tokens)
516 return NULL;
517
518 handle = virgl_object_assign_handle();
519 /* encode VS state */
520 ret = virgl_encode_shader_state(vctx, handle, type,
521 &shader->stream_output, 0,
522 new_tokens);
523 if (ret) {
524 return NULL;
525 }
526
527 FREE(new_tokens);
528 return (void *)(unsigned long)handle;
529
530 }
531 static void *virgl_create_vs_state(struct pipe_context *ctx,
532 const struct pipe_shader_state *shader)
533 {
534 return virgl_shader_encoder(ctx, shader, PIPE_SHADER_VERTEX);
535 }
536
537 static void *virgl_create_tcs_state(struct pipe_context *ctx,
538 const struct pipe_shader_state *shader)
539 {
540 return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_CTRL);
541 }
542
543 static void *virgl_create_tes_state(struct pipe_context *ctx,
544 const struct pipe_shader_state *shader)
545 {
546 return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_EVAL);
547 }
548
549 static void *virgl_create_gs_state(struct pipe_context *ctx,
550 const struct pipe_shader_state *shader)
551 {
552 return virgl_shader_encoder(ctx, shader, PIPE_SHADER_GEOMETRY);
553 }
554
555 static void *virgl_create_fs_state(struct pipe_context *ctx,
556 const struct pipe_shader_state *shader)
557 {
558 return virgl_shader_encoder(ctx, shader, PIPE_SHADER_FRAGMENT);
559 }
560
561 static void
562 virgl_delete_fs_state(struct pipe_context *ctx,
563 void *fs)
564 {
565 uint32_t handle = (unsigned long)fs;
566 struct virgl_context *vctx = virgl_context(ctx);
567
568 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
569 }
570
571 static void
572 virgl_delete_gs_state(struct pipe_context *ctx,
573 void *gs)
574 {
575 uint32_t handle = (unsigned long)gs;
576 struct virgl_context *vctx = virgl_context(ctx);
577
578 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
579 }
580
581 static void
582 virgl_delete_vs_state(struct pipe_context *ctx,
583 void *vs)
584 {
585 uint32_t handle = (unsigned long)vs;
586 struct virgl_context *vctx = virgl_context(ctx);
587
588 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
589 }
590
591 static void
592 virgl_delete_tcs_state(struct pipe_context *ctx,
593 void *tcs)
594 {
595 uint32_t handle = (unsigned long)tcs;
596 struct virgl_context *vctx = virgl_context(ctx);
597
598 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
599 }
600
601 static void
602 virgl_delete_tes_state(struct pipe_context *ctx,
603 void *tes)
604 {
605 uint32_t handle = (unsigned long)tes;
606 struct virgl_context *vctx = virgl_context(ctx);
607
608 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
609 }
610
611 static void virgl_bind_vs_state(struct pipe_context *ctx,
612 void *vss)
613 {
614 uint32_t handle = (unsigned long)vss;
615 struct virgl_context *vctx = virgl_context(ctx);
616
617 virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_VERTEX);
618 }
619
620 static void virgl_bind_tcs_state(struct pipe_context *ctx,
621 void *vss)
622 {
623 uint32_t handle = (unsigned long)vss;
624 struct virgl_context *vctx = virgl_context(ctx);
625
626 virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_CTRL);
627 }
628
629 static void virgl_bind_tes_state(struct pipe_context *ctx,
630 void *vss)
631 {
632 uint32_t handle = (unsigned long)vss;
633 struct virgl_context *vctx = virgl_context(ctx);
634
635 virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_EVAL);
636 }
637
638 static void virgl_bind_gs_state(struct pipe_context *ctx,
639 void *vss)
640 {
641 uint32_t handle = (unsigned long)vss;
642 struct virgl_context *vctx = virgl_context(ctx);
643
644 virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_GEOMETRY);
645 }
646
647
648 static void virgl_bind_fs_state(struct pipe_context *ctx,
649 void *vss)
650 {
651 uint32_t handle = (unsigned long)vss;
652 struct virgl_context *vctx = virgl_context(ctx);
653
654 virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_FRAGMENT);
655 }
656
657 static void virgl_clear(struct pipe_context *ctx,
658 unsigned buffers,
659 const union pipe_color_union *color,
660 double depth, unsigned stencil)
661 {
662 struct virgl_context *vctx = virgl_context(ctx);
663
664 virgl_encode_clear(vctx, buffers, color, depth, stencil);
665 }
666
667 static void virgl_draw_vbo(struct pipe_context *ctx,
668 const struct pipe_draw_info *dinfo)
669 {
670 struct virgl_context *vctx = virgl_context(ctx);
671 struct virgl_screen *rs = virgl_screen(ctx->screen);
672 struct virgl_indexbuf ib = {};
673 struct pipe_draw_info info = *dinfo;
674
675 if (!dinfo->count_from_stream_output && !dinfo->indirect &&
676 !dinfo->primitive_restart &&
677 !u_trim_pipe_prim(dinfo->mode, (unsigned*)&dinfo->count))
678 return;
679
680 if (!(rs->caps.caps.v1.prim_mask & (1 << dinfo->mode))) {
681 util_primconvert_draw_vbo(vctx->primconvert, dinfo);
682 return;
683 }
684 if (info.index_size) {
685 pipe_resource_reference(&ib.buffer, info.has_user_indices ? NULL : info.index.resource);
686 ib.user_buffer = info.has_user_indices ? info.index.user : NULL;
687 ib.index_size = dinfo->index_size;
688 ib.offset = info.start * ib.index_size;
689
690 if (ib.user_buffer) {
691 u_upload_data(vctx->uploader, 0, info.count * ib.index_size, 256,
692 ib.user_buffer, &ib.offset, &ib.buffer);
693 ib.user_buffer = NULL;
694 }
695 }
696
697 u_upload_unmap(vctx->uploader);
698
699 vctx->num_draws++;
700 virgl_hw_set_vertex_buffers(vctx);
701 if (info.index_size)
702 virgl_hw_set_index_buffer(vctx, &ib);
703
704 virgl_encoder_draw_vbo(vctx, &info);
705
706 pipe_resource_reference(&ib.buffer, NULL);
707
708 }
709
710 static void virgl_flush_eq(struct virgl_context *ctx, void *closure,
711 struct pipe_fence_handle **fence)
712 {
713 struct virgl_screen *rs = virgl_screen(ctx->base.screen);
714 int out_fence_fd = -1;
715
716 /* send the buffer to the remote side for decoding */
717 ctx->num_transfers = ctx->num_draws = 0;
718
719 rs->vws->submit_cmd(rs->vws, ctx->cbuf, ctx->cbuf->in_fence_fd,
720 ctx->cbuf->needs_out_fence_fd ? &out_fence_fd : NULL);
721
722 if (fence)
723 *fence = rs->vws->cs_create_fence(rs->vws, out_fence_fd);
724
725 virgl_encoder_set_sub_ctx(ctx, ctx->hw_sub_ctx_id);
726
727 /* add back current framebuffer resources to reference list? */
728 virgl_reemit_res(ctx);
729 }
730
731 static void virgl_flush_from_st(struct pipe_context *ctx,
732 struct pipe_fence_handle **fence,
733 enum pipe_flush_flags flags)
734 {
735 struct virgl_context *vctx = virgl_context(ctx);
736 struct virgl_buffer *buf, *tmp;
737
738 if (flags & PIPE_FLUSH_FENCE_FD)
739 vctx->cbuf->needs_out_fence_fd = true;
740
741 LIST_FOR_EACH_ENTRY_SAFE(buf, tmp, &vctx->to_flush_bufs, flush_list) {
742 struct pipe_resource *res = &buf->base.u.b;
743 virgl_buffer_flush(vctx, buf);
744 list_del(&buf->flush_list);
745 buf->on_list = FALSE;
746 pipe_resource_reference(&res, NULL);
747
748 }
749 virgl_flush_eq(vctx, vctx, fence);
750
751 if (vctx->cbuf->in_fence_fd != -1) {
752 close(vctx->cbuf->in_fence_fd);
753 vctx->cbuf->in_fence_fd = -1;
754 }
755 vctx->cbuf->needs_out_fence_fd = false;
756 }
757
758 static struct pipe_sampler_view *virgl_create_sampler_view(struct pipe_context *ctx,
759 struct pipe_resource *texture,
760 const struct pipe_sampler_view *state)
761 {
762 struct virgl_context *vctx = virgl_context(ctx);
763 struct virgl_sampler_view *grview;
764 uint32_t handle;
765 struct virgl_resource *res;
766
767 if (!state)
768 return NULL;
769
770 grview = CALLOC_STRUCT(virgl_sampler_view);
771 if (!grview)
772 return NULL;
773
774 res = virgl_resource(texture);
775 handle = virgl_object_assign_handle();
776 virgl_encode_sampler_view(vctx, handle, res, state);
777
778 grview->base = *state;
779 grview->base.reference.count = 1;
780
781 grview->base.texture = NULL;
782 grview->base.context = ctx;
783 pipe_resource_reference(&grview->base.texture, texture);
784 grview->handle = handle;
785 return &grview->base;
786 }
787
788 static void virgl_set_sampler_views(struct pipe_context *ctx,
789 enum pipe_shader_type shader_type,
790 unsigned start_slot,
791 unsigned num_views,
792 struct pipe_sampler_view **views)
793 {
794 struct virgl_context *vctx = virgl_context(ctx);
795 int i;
796 uint32_t disable_mask = ~((1ull << num_views) - 1);
797 struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
798 uint32_t new_mask = 0;
799 uint32_t remaining_mask;
800
801 remaining_mask = tinfo->enabled_mask & disable_mask;
802
803 while (remaining_mask) {
804 i = u_bit_scan(&remaining_mask);
805 assert(tinfo->views[i]);
806
807 pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
808 }
809
810 for (i = 0; i < num_views; i++) {
811 struct virgl_sampler_view *grview = virgl_sampler_view(views[i]);
812
813 if (views[i] == (struct pipe_sampler_view *)tinfo->views[i])
814 continue;
815
816 if (grview) {
817 new_mask |= 1 << i;
818 pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], views[i]);
819 } else {
820 pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
821 disable_mask |= 1 << i;
822 }
823 }
824
825 tinfo->enabled_mask &= ~disable_mask;
826 tinfo->enabled_mask |= new_mask;
827 virgl_encode_set_sampler_views(vctx, shader_type, start_slot, num_views, tinfo->views);
828 virgl_attach_res_sampler_views(vctx, shader_type);
829 }
830
831 static void
832 virgl_texture_barrier(struct pipe_context *ctx, unsigned flags)
833 {
834 struct virgl_context *vctx = virgl_context(ctx);
835 struct virgl_screen *rs = virgl_screen(ctx->screen);
836
837 if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER))
838 return;
839 virgl_encode_texture_barrier(vctx, flags);
840 }
841
842 static void virgl_destroy_sampler_view(struct pipe_context *ctx,
843 struct pipe_sampler_view *view)
844 {
845 struct virgl_context *vctx = virgl_context(ctx);
846 struct virgl_sampler_view *grview = virgl_sampler_view(view);
847
848 virgl_encode_delete_object(vctx, grview->handle, VIRGL_OBJECT_SAMPLER_VIEW);
849 pipe_resource_reference(&view->texture, NULL);
850 FREE(view);
851 }
852
853 static void *virgl_create_sampler_state(struct pipe_context *ctx,
854 const struct pipe_sampler_state *state)
855 {
856 struct virgl_context *vctx = virgl_context(ctx);
857 uint32_t handle;
858
859 handle = virgl_object_assign_handle();
860
861 virgl_encode_sampler_state(vctx, handle, state);
862 return (void *)(unsigned long)handle;
863 }
864
865 static void virgl_delete_sampler_state(struct pipe_context *ctx,
866 void *ss)
867 {
868 struct virgl_context *vctx = virgl_context(ctx);
869 uint32_t handle = (unsigned long)ss;
870
871 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SAMPLER_STATE);
872 }
873
874 static void virgl_bind_sampler_states(struct pipe_context *ctx,
875 enum pipe_shader_type shader,
876 unsigned start_slot,
877 unsigned num_samplers,
878 void **samplers)
879 {
880 struct virgl_context *vctx = virgl_context(ctx);
881 uint32_t handles[32];
882 int i;
883 for (i = 0; i < num_samplers; i++) {
884 handles[i] = (unsigned long)(samplers[i]);
885 }
886 virgl_encode_bind_sampler_states(vctx, shader, start_slot, num_samplers, handles);
887 }
888
889 static void virgl_set_polygon_stipple(struct pipe_context *ctx,
890 const struct pipe_poly_stipple *ps)
891 {
892 struct virgl_context *vctx = virgl_context(ctx);
893 virgl_encoder_set_polygon_stipple(vctx, ps);
894 }
895
896 static void virgl_set_scissor_states(struct pipe_context *ctx,
897 unsigned start_slot,
898 unsigned num_scissor,
899 const struct pipe_scissor_state *ss)
900 {
901 struct virgl_context *vctx = virgl_context(ctx);
902 virgl_encoder_set_scissor_state(vctx, start_slot, num_scissor, ss);
903 }
904
905 static void virgl_set_sample_mask(struct pipe_context *ctx,
906 unsigned sample_mask)
907 {
908 struct virgl_context *vctx = virgl_context(ctx);
909 virgl_encoder_set_sample_mask(vctx, sample_mask);
910 }
911
912 static void virgl_set_min_samples(struct pipe_context *ctx,
913 unsigned min_samples)
914 {
915 struct virgl_context *vctx = virgl_context(ctx);
916 struct virgl_screen *rs = virgl_screen(ctx->screen);
917
918 if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_SET_MIN_SAMPLES))
919 return;
920 virgl_encoder_set_min_samples(vctx, min_samples);
921 }
922
923 static void virgl_set_clip_state(struct pipe_context *ctx,
924 const struct pipe_clip_state *clip)
925 {
926 struct virgl_context *vctx = virgl_context(ctx);
927 virgl_encoder_set_clip_state(vctx, clip);
928 }
929
930 static void virgl_set_tess_state(struct pipe_context *ctx,
931 const float default_outer_level[4],
932 const float default_inner_level[2])
933 {
934 struct virgl_context *vctx = virgl_context(ctx);
935 struct virgl_screen *rs = virgl_screen(ctx->screen);
936
937 if (!rs->caps.caps.v1.bset.has_tessellation_shaders)
938 return;
939 virgl_encode_set_tess_state(vctx, default_outer_level, default_inner_level);
940 }
941
942 static void virgl_resource_copy_region(struct pipe_context *ctx,
943 struct pipe_resource *dst,
944 unsigned dst_level,
945 unsigned dstx, unsigned dsty, unsigned dstz,
946 struct pipe_resource *src,
947 unsigned src_level,
948 const struct pipe_box *src_box)
949 {
950 struct virgl_context *vctx = virgl_context(ctx);
951 struct virgl_resource *dres = virgl_resource(dst);
952 struct virgl_resource *sres = virgl_resource(src);
953
954 dres->clean = FALSE;
955 virgl_encode_resource_copy_region(vctx, dres,
956 dst_level, dstx, dsty, dstz,
957 sres, src_level,
958 src_box);
959 }
960
961 static void
962 virgl_flush_resource(struct pipe_context *pipe,
963 struct pipe_resource *resource)
964 {
965 }
966
967 static void virgl_blit(struct pipe_context *ctx,
968 const struct pipe_blit_info *blit)
969 {
970 struct virgl_context *vctx = virgl_context(ctx);
971 struct virgl_resource *dres = virgl_resource(blit->dst.resource);
972 struct virgl_resource *sres = virgl_resource(blit->src.resource);
973
974 dres->clean = FALSE;
975 virgl_encode_blit(vctx, dres, sres,
976 blit);
977 }
978
979 static void virgl_set_hw_atomic_buffers(struct pipe_context *ctx,
980 unsigned start_slot,
981 unsigned count,
982 const struct pipe_shader_buffer *buffers)
983 {
984 struct virgl_context *vctx = virgl_context(ctx);
985
986 for (unsigned i = 0; i < count; i++) {
987 unsigned idx = start_slot + i;
988
989 if (buffers) {
990 if (buffers[i].buffer) {
991 pipe_resource_reference(&vctx->atomic_buffers[idx],
992 buffers[i].buffer);
993 continue;
994 }
995 }
996 pipe_resource_reference(&vctx->atomic_buffers[idx], NULL);
997 }
998 virgl_encode_set_hw_atomic_buffers(vctx, start_slot, count, buffers);
999 }
1000
1001 static void virgl_set_shader_buffers(struct pipe_context *ctx,
1002 enum pipe_shader_type shader,
1003 unsigned start_slot, unsigned count,
1004 const struct pipe_shader_buffer *buffers)
1005 {
1006 struct virgl_context *vctx = virgl_context(ctx);
1007 struct virgl_screen *rs = virgl_screen(ctx->screen);
1008
1009 for (unsigned i = 0; i < count; i++) {
1010 unsigned idx = start_slot + i;
1011
1012 if (buffers) {
1013 if (buffers[i].buffer) {
1014 pipe_resource_reference(&vctx->ssbos[shader][idx], buffers[i].buffer);
1015 continue;
1016 }
1017 }
1018 pipe_resource_reference(&vctx->ssbos[shader][idx], NULL);
1019 }
1020
1021 uint32_t max_shader_buffer = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1022 rs->caps.caps.v2.max_shader_buffer_frag_compute :
1023 rs->caps.caps.v2.max_shader_buffer_other_stages;
1024 if (!max_shader_buffer)
1025 return;
1026 virgl_encode_set_shader_buffers(vctx, shader, start_slot, count, buffers);
1027 }
1028
1029 static void virgl_create_fence_fd(struct pipe_context *ctx,
1030 struct pipe_fence_handle **fence,
1031 int fd,
1032 enum pipe_fd_type type)
1033 {
1034 assert(type == PIPE_FD_TYPE_NATIVE_SYNC);
1035 struct virgl_screen *rs = virgl_screen(ctx->screen);
1036
1037 if (rs->vws->cs_create_fence)
1038 *fence = rs->vws->cs_create_fence(rs->vws, fd);
1039 }
1040
1041 static void virgl_fence_server_sync(struct pipe_context *ctx,
1042 struct pipe_fence_handle *fence)
1043 {
1044 struct virgl_context *vctx = virgl_context(ctx);
1045 struct virgl_screen *rs = virgl_screen(ctx->screen);
1046
1047 if (rs->vws->fence_server_sync)
1048 rs->vws->fence_server_sync(rs->vws, vctx->cbuf, fence);
1049 }
1050
1051 static void virgl_set_shader_images(struct pipe_context *ctx,
1052 enum pipe_shader_type shader,
1053 unsigned start_slot, unsigned count,
1054 const struct pipe_image_view *images)
1055 {
1056 struct virgl_context *vctx = virgl_context(ctx);
1057 struct virgl_screen *rs = virgl_screen(ctx->screen);
1058
1059 for (unsigned i = 0; i < count; i++) {
1060 unsigned idx = start_slot + i;
1061
1062 if (images) {
1063 if (images[i].resource) {
1064 pipe_resource_reference(&vctx->images[shader][idx], images[i].resource);
1065 continue;
1066 }
1067 }
1068 pipe_resource_reference(&vctx->images[shader][idx], NULL);
1069 }
1070
1071 uint32_t max_shader_images = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1072 rs->caps.caps.v2.max_shader_image_frag_compute :
1073 rs->caps.caps.v2.max_shader_image_other_stages;
1074 if (!max_shader_images)
1075 return;
1076 virgl_encode_set_shader_images(vctx, shader, start_slot, count, images);
1077 }
1078
1079 static void virgl_memory_barrier(struct pipe_context *ctx,
1080 unsigned flags)
1081 {
1082 struct virgl_context *vctx = virgl_context(ctx);
1083 struct virgl_screen *rs = virgl_screen(ctx->screen);
1084
1085 if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_MEMORY_BARRIER))
1086 return;
1087 virgl_encode_memory_barrier(vctx, flags);
1088 }
1089
1090 static void *virgl_create_compute_state(struct pipe_context *ctx,
1091 const struct pipe_compute_state *state)
1092 {
1093 struct virgl_context *vctx = virgl_context(ctx);
1094 uint32_t handle;
1095 const struct tgsi_token *new_tokens = state->prog;
1096 struct pipe_stream_output_info so_info = {};
1097 int ret;
1098
1099 handle = virgl_object_assign_handle();
1100 ret = virgl_encode_shader_state(vctx, handle, PIPE_SHADER_COMPUTE,
1101 &so_info,
1102 state->req_local_mem,
1103 new_tokens);
1104 if (ret) {
1105 return NULL;
1106 }
1107
1108 return (void *)(unsigned long)handle;
1109 }
1110
1111 static void virgl_bind_compute_state(struct pipe_context *ctx, void *state)
1112 {
1113 uint32_t handle = (unsigned long)state;
1114 struct virgl_context *vctx = virgl_context(ctx);
1115
1116 virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_COMPUTE);
1117 }
1118
1119 static void virgl_delete_compute_state(struct pipe_context *ctx, void *state)
1120 {
1121 uint32_t handle = (unsigned long)state;
1122 struct virgl_context *vctx = virgl_context(ctx);
1123
1124 virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
1125 }
1126
1127 static void virgl_launch_grid(struct pipe_context *ctx,
1128 const struct pipe_grid_info *info)
1129 {
1130 struct virgl_context *vctx = virgl_context(ctx);
1131 virgl_encode_launch_grid(vctx, info);
1132 }
1133
1134 static void
1135 virgl_context_destroy( struct pipe_context *ctx )
1136 {
1137 struct virgl_context *vctx = virgl_context(ctx);
1138 struct virgl_screen *rs = virgl_screen(ctx->screen);
1139
1140 vctx->framebuffer.zsbuf = NULL;
1141 vctx->framebuffer.nr_cbufs = 0;
1142 virgl_encoder_destroy_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1143 virgl_flush_eq(vctx, vctx, NULL);
1144
1145 rs->vws->cmd_buf_destroy(vctx->cbuf);
1146 if (vctx->uploader)
1147 u_upload_destroy(vctx->uploader);
1148 util_primconvert_destroy(vctx->primconvert);
1149
1150 slab_destroy_child(&vctx->texture_transfer_pool);
1151 FREE(vctx);
1152 }
1153
1154 static void virgl_get_sample_position(struct pipe_context *ctx,
1155 unsigned sample_count,
1156 unsigned index,
1157 float *out_value)
1158 {
1159 struct virgl_context *vctx = virgl_context(ctx);
1160 struct virgl_screen *vs = virgl_screen(vctx->base.screen);
1161
1162 if (sample_count > vs->caps.caps.v1.max_samples) {
1163 debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1164 sample_count, vs->caps.caps.v1.max_samples);
1165 return;
1166 }
1167
1168 /* The following is basically copied from dri/i965gen6_get_sample_position
1169 * The only addition is that we hold the msaa positions for all sample
1170 * counts in a flat array. */
1171 uint32_t bits = 0;
1172 if (sample_count == 1) {
1173 out_value[0] = out_value[1] = 0.5f;
1174 return;
1175 } else if (sample_count == 2) {
1176 bits = vs->caps.caps.v2.sample_locations[0] >> (8 * index);
1177 } else if (sample_count <= 4) {
1178 bits = vs->caps.caps.v2.sample_locations[1] >> (8 * index);
1179 } else if (sample_count <= 8) {
1180 bits = vs->caps.caps.v2.sample_locations[2 + (index >> 2)] >> (8 * (index & 3));
1181 } else if (sample_count <= 16) {
1182 bits = vs->caps.caps.v2.sample_locations[4 + (index >> 2)] >> (8 * (index & 3));
1183 }
1184 out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
1185 out_value[1] = (bits & 0xf) / 16.0f;
1186
1187 if (virgl_debug & VIRGL_DEBUG_VERBOSE)
1188 debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1189 index, sample_count, out_value[0], out_value[1]);
1190 }
1191
1192 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
1193 void *priv,
1194 unsigned flags)
1195 {
1196 struct virgl_context *vctx;
1197 struct virgl_screen *rs = virgl_screen(pscreen);
1198 vctx = CALLOC_STRUCT(virgl_context);
1199 const char *host_debug_flagstring;
1200
1201 vctx->cbuf = rs->vws->cmd_buf_create(rs->vws);
1202 if (!vctx->cbuf) {
1203 FREE(vctx);
1204 return NULL;
1205 }
1206
1207 vctx->base.destroy = virgl_context_destroy;
1208 vctx->base.create_surface = virgl_create_surface;
1209 vctx->base.surface_destroy = virgl_surface_destroy;
1210 vctx->base.set_framebuffer_state = virgl_set_framebuffer_state;
1211 vctx->base.create_blend_state = virgl_create_blend_state;
1212 vctx->base.bind_blend_state = virgl_bind_blend_state;
1213 vctx->base.delete_blend_state = virgl_delete_blend_state;
1214 vctx->base.create_depth_stencil_alpha_state = virgl_create_depth_stencil_alpha_state;
1215 vctx->base.bind_depth_stencil_alpha_state = virgl_bind_depth_stencil_alpha_state;
1216 vctx->base.delete_depth_stencil_alpha_state = virgl_delete_depth_stencil_alpha_state;
1217 vctx->base.create_rasterizer_state = virgl_create_rasterizer_state;
1218 vctx->base.bind_rasterizer_state = virgl_bind_rasterizer_state;
1219 vctx->base.delete_rasterizer_state = virgl_delete_rasterizer_state;
1220
1221 vctx->base.set_viewport_states = virgl_set_viewport_states;
1222 vctx->base.create_vertex_elements_state = virgl_create_vertex_elements_state;
1223 vctx->base.bind_vertex_elements_state = virgl_bind_vertex_elements_state;
1224 vctx->base.delete_vertex_elements_state = virgl_delete_vertex_elements_state;
1225 vctx->base.set_vertex_buffers = virgl_set_vertex_buffers;
1226 vctx->base.set_constant_buffer = virgl_set_constant_buffer;
1227
1228 vctx->base.set_tess_state = virgl_set_tess_state;
1229 vctx->base.create_vs_state = virgl_create_vs_state;
1230 vctx->base.create_tcs_state = virgl_create_tcs_state;
1231 vctx->base.create_tes_state = virgl_create_tes_state;
1232 vctx->base.create_gs_state = virgl_create_gs_state;
1233 vctx->base.create_fs_state = virgl_create_fs_state;
1234
1235 vctx->base.bind_vs_state = virgl_bind_vs_state;
1236 vctx->base.bind_tcs_state = virgl_bind_tcs_state;
1237 vctx->base.bind_tes_state = virgl_bind_tes_state;
1238 vctx->base.bind_gs_state = virgl_bind_gs_state;
1239 vctx->base.bind_fs_state = virgl_bind_fs_state;
1240
1241 vctx->base.delete_vs_state = virgl_delete_vs_state;
1242 vctx->base.delete_tcs_state = virgl_delete_tcs_state;
1243 vctx->base.delete_tes_state = virgl_delete_tes_state;
1244 vctx->base.delete_gs_state = virgl_delete_gs_state;
1245 vctx->base.delete_fs_state = virgl_delete_fs_state;
1246
1247 vctx->base.create_compute_state = virgl_create_compute_state;
1248 vctx->base.bind_compute_state = virgl_bind_compute_state;
1249 vctx->base.delete_compute_state = virgl_delete_compute_state;
1250 vctx->base.launch_grid = virgl_launch_grid;
1251
1252 vctx->base.clear = virgl_clear;
1253 vctx->base.draw_vbo = virgl_draw_vbo;
1254 vctx->base.flush = virgl_flush_from_st;
1255 vctx->base.screen = pscreen;
1256 vctx->base.create_sampler_view = virgl_create_sampler_view;
1257 vctx->base.sampler_view_destroy = virgl_destroy_sampler_view;
1258 vctx->base.set_sampler_views = virgl_set_sampler_views;
1259 vctx->base.texture_barrier = virgl_texture_barrier;
1260
1261 vctx->base.create_sampler_state = virgl_create_sampler_state;
1262 vctx->base.delete_sampler_state = virgl_delete_sampler_state;
1263 vctx->base.bind_sampler_states = virgl_bind_sampler_states;
1264
1265 vctx->base.set_polygon_stipple = virgl_set_polygon_stipple;
1266 vctx->base.set_scissor_states = virgl_set_scissor_states;
1267 vctx->base.set_sample_mask = virgl_set_sample_mask;
1268 vctx->base.set_min_samples = virgl_set_min_samples;
1269 vctx->base.set_stencil_ref = virgl_set_stencil_ref;
1270 vctx->base.set_clip_state = virgl_set_clip_state;
1271
1272 vctx->base.set_blend_color = virgl_set_blend_color;
1273
1274 vctx->base.get_sample_position = virgl_get_sample_position;
1275
1276 vctx->base.resource_copy_region = virgl_resource_copy_region;
1277 vctx->base.flush_resource = virgl_flush_resource;
1278 vctx->base.blit = virgl_blit;
1279 vctx->base.create_fence_fd = virgl_create_fence_fd;
1280 vctx->base.fence_server_sync = virgl_fence_server_sync;
1281
1282 vctx->base.set_shader_buffers = virgl_set_shader_buffers;
1283 vctx->base.set_hw_atomic_buffers = virgl_set_hw_atomic_buffers;
1284 vctx->base.set_shader_images = virgl_set_shader_images;
1285 vctx->base.memory_barrier = virgl_memory_barrier;
1286
1287 virgl_init_context_resource_functions(&vctx->base);
1288 virgl_init_query_functions(vctx);
1289 virgl_init_so_functions(vctx);
1290
1291 list_inithead(&vctx->to_flush_bufs);
1292 slab_create_child(&vctx->texture_transfer_pool, &rs->texture_transfer_pool);
1293
1294 vctx->primconvert = util_primconvert_create(&vctx->base, rs->caps.caps.v1.prim_mask);
1295 vctx->uploader = u_upload_create(&vctx->base, 1024 * 1024,
1296 PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM, 0);
1297 if (!vctx->uploader)
1298 goto fail;
1299 vctx->base.stream_uploader = vctx->uploader;
1300 vctx->base.const_uploader = vctx->uploader;
1301
1302 vctx->hw_sub_ctx_id = rs->sub_ctx_id++;
1303 virgl_encoder_create_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1304
1305 virgl_encoder_set_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1306
1307 if (rs->caps.caps.v2.capability_bits & VIRGL_CAP_GUEST_MAY_INIT_LOG) {
1308 host_debug_flagstring = getenv("VIRGL_HOST_DEBUG");
1309 if (host_debug_flagstring)
1310 virgl_encode_host_debug_flagstring(vctx, host_debug_flagstring);
1311 }
1312
1313 return &vctx->base;
1314 fail:
1315 return NULL;
1316 }