2 * Copyright 2014, 2015 Red Hat.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_shader_tokens.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31 #include "util/u_inlines.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_prim.h"
35 #include "util/u_transfer.h"
36 #include "util/u_helpers.h"
37 #include "util/slab.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_blitter.h"
40 #include "tgsi/tgsi_text.h"
41 #include "indices/u_primconvert.h"
43 #include "pipebuffer/pb_buffer.h"
45 #include "virgl_encode.h"
46 #include "virgl_context.h"
47 #include "virgl_protocol.h"
48 #include "virgl_resource.h"
49 #include "virgl_screen.h"
51 static uint32_t next_handle
;
52 uint32_t virgl_object_assign_handle(void)
57 static void virgl_buffer_flush(struct virgl_context
*vctx
,
58 struct virgl_buffer
*vbuf
)
60 struct virgl_screen
*rs
= virgl_screen(vctx
->base
.screen
);
63 assert(vbuf
->on_list
);
70 box
.x
= vbuf
->valid_buffer_range
.start
;
71 box
.width
= MIN2(vbuf
->valid_buffer_range
.end
- vbuf
->valid_buffer_range
.start
, vbuf
->base
.u
.b
.width0
);
73 vctx
->num_transfers
++;
74 rs
->vws
->transfer_put(rs
->vws
, vbuf
->base
.hw_res
,
75 &box
, 0, 0, box
.x
, 0);
77 util_range_set_empty(&vbuf
->valid_buffer_range
);
80 static void virgl_attach_res_framebuffer(struct virgl_context
*vctx
)
82 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
83 struct pipe_surface
*surf
;
84 struct virgl_resource
*res
;
87 surf
= vctx
->framebuffer
.zsbuf
;
89 res
= virgl_resource(surf
->texture
);
91 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
93 for (i
= 0; i
< vctx
->framebuffer
.nr_cbufs
; i
++) {
94 surf
= vctx
->framebuffer
.cbufs
[i
];
96 res
= virgl_resource(surf
->texture
);
98 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
103 static void virgl_attach_res_sampler_views(struct virgl_context
*vctx
,
104 enum pipe_shader_type shader_type
)
106 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
107 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
108 struct virgl_resource
*res
;
109 uint32_t remaining_mask
= tinfo
->enabled_mask
;
111 while (remaining_mask
) {
112 i
= u_bit_scan(&remaining_mask
);
113 assert(tinfo
->views
[i
]);
115 res
= virgl_resource(tinfo
->views
[i
]->base
.texture
);
117 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
121 static void virgl_attach_res_vertex_buffers(struct virgl_context
*vctx
)
123 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
124 struct virgl_resource
*res
;
127 for (i
= 0; i
< vctx
->num_vertex_buffers
; i
++) {
128 res
= virgl_resource(vctx
->vertex_buffer
[i
].buffer
.resource
);
130 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
134 static void virgl_attach_res_index_buffer(struct virgl_context
*vctx
,
135 struct virgl_indexbuf
*ib
)
137 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
138 struct virgl_resource
*res
;
140 res
= virgl_resource(ib
->buffer
);
142 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
145 static void virgl_attach_res_so_targets(struct virgl_context
*vctx
)
147 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
148 struct virgl_resource
*res
;
151 for (i
= 0; i
< vctx
->num_so_targets
; i
++) {
152 res
= virgl_resource(vctx
->so_targets
[i
].base
.buffer
);
154 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
158 static void virgl_attach_res_uniform_buffers(struct virgl_context
*vctx
,
159 enum pipe_shader_type shader_type
)
161 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
162 struct virgl_resource
*res
;
164 for (i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
165 res
= virgl_resource(vctx
->ubos
[shader_type
][i
]);
167 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
172 static void virgl_attach_res_shader_buffers(struct virgl_context
*vctx
,
173 enum pipe_shader_type shader_type
)
175 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
176 struct virgl_resource
*res
;
178 for (i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
179 res
= virgl_resource(vctx
->ssbos
[shader_type
][i
]);
181 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
186 static void virgl_attach_res_shader_images(struct virgl_context
*vctx
,
187 enum pipe_shader_type shader_type
)
189 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
190 struct virgl_resource
*res
;
192 for (i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
193 res
= virgl_resource(vctx
->images
[shader_type
][i
]);
195 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
200 static void virgl_attach_res_atomic_buffers(struct virgl_context
*vctx
)
202 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
203 struct virgl_resource
*res
;
205 for (i
= 0; i
< PIPE_MAX_HW_ATOMIC_BUFFERS
; i
++) {
206 res
= virgl_resource(vctx
->atomic_buffers
[i
]);
208 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
214 * after flushing, the hw context still has a bunch of
215 * resources bound, so we need to rebind those here.
217 static void virgl_reemit_res(struct virgl_context
*vctx
)
219 enum pipe_shader_type shader_type
;
221 /* reattach any flushed resources */
222 /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
223 virgl_attach_res_framebuffer(vctx
);
225 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
226 virgl_attach_res_sampler_views(vctx
, shader_type
);
227 virgl_attach_res_uniform_buffers(vctx
, shader_type
);
228 virgl_attach_res_shader_buffers(vctx
, shader_type
);
229 virgl_attach_res_shader_images(vctx
, shader_type
);
231 virgl_attach_res_atomic_buffers(vctx
);
232 virgl_attach_res_vertex_buffers(vctx
);
233 virgl_attach_res_so_targets(vctx
);
236 static struct pipe_surface
*virgl_create_surface(struct pipe_context
*ctx
,
237 struct pipe_resource
*resource
,
238 const struct pipe_surface
*templ
)
240 struct virgl_context
*vctx
= virgl_context(ctx
);
241 struct virgl_surface
*surf
;
242 struct virgl_resource
*res
= virgl_resource(resource
);
245 surf
= CALLOC_STRUCT(virgl_surface
);
250 handle
= virgl_object_assign_handle();
251 pipe_reference_init(&surf
->base
.reference
, 1);
252 pipe_resource_reference(&surf
->base
.texture
, resource
);
253 surf
->base
.context
= ctx
;
254 surf
->base
.format
= templ
->format
;
255 if (resource
->target
!= PIPE_BUFFER
) {
256 surf
->base
.width
= u_minify(resource
->width0
, templ
->u
.tex
.level
);
257 surf
->base
.height
= u_minify(resource
->height0
, templ
->u
.tex
.level
);
258 surf
->base
.u
.tex
.level
= templ
->u
.tex
.level
;
259 surf
->base
.u
.tex
.first_layer
= templ
->u
.tex
.first_layer
;
260 surf
->base
.u
.tex
.last_layer
= templ
->u
.tex
.last_layer
;
262 surf
->base
.width
= templ
->u
.buf
.last_element
- templ
->u
.buf
.first_element
+ 1;
263 surf
->base
.height
= resource
->height0
;
264 surf
->base
.u
.buf
.first_element
= templ
->u
.buf
.first_element
;
265 surf
->base
.u
.buf
.last_element
= templ
->u
.buf
.last_element
;
267 virgl_encoder_create_surface(vctx
, handle
, res
, &surf
->base
);
268 surf
->handle
= handle
;
272 static void virgl_surface_destroy(struct pipe_context
*ctx
,
273 struct pipe_surface
*psurf
)
275 struct virgl_context
*vctx
= virgl_context(ctx
);
276 struct virgl_surface
*surf
= virgl_surface(psurf
);
278 pipe_resource_reference(&surf
->base
.texture
, NULL
);
279 virgl_encode_delete_object(vctx
, surf
->handle
, VIRGL_OBJECT_SURFACE
);
283 static void *virgl_create_blend_state(struct pipe_context
*ctx
,
284 const struct pipe_blend_state
*blend_state
)
286 struct virgl_context
*vctx
= virgl_context(ctx
);
288 handle
= virgl_object_assign_handle();
290 virgl_encode_blend_state(vctx
, handle
, blend_state
);
291 return (void *)(unsigned long)handle
;
295 static void virgl_bind_blend_state(struct pipe_context
*ctx
,
298 struct virgl_context
*vctx
= virgl_context(ctx
);
299 uint32_t handle
= (unsigned long)blend_state
;
300 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
303 static void virgl_delete_blend_state(struct pipe_context
*ctx
,
306 struct virgl_context
*vctx
= virgl_context(ctx
);
307 uint32_t handle
= (unsigned long)blend_state
;
308 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
311 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context
*ctx
,
312 const struct pipe_depth_stencil_alpha_state
*blend_state
)
314 struct virgl_context
*vctx
= virgl_context(ctx
);
316 handle
= virgl_object_assign_handle();
318 virgl_encode_dsa_state(vctx
, handle
, blend_state
);
319 return (void *)(unsigned long)handle
;
322 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context
*ctx
,
325 struct virgl_context
*vctx
= virgl_context(ctx
);
326 uint32_t handle
= (unsigned long)blend_state
;
327 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
330 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context
*ctx
,
333 struct virgl_context
*vctx
= virgl_context(ctx
);
334 uint32_t handle
= (unsigned long)dsa_state
;
335 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
338 static void *virgl_create_rasterizer_state(struct pipe_context
*ctx
,
339 const struct pipe_rasterizer_state
*rs_state
)
341 struct virgl_context
*vctx
= virgl_context(ctx
);
343 handle
= virgl_object_assign_handle();
345 virgl_encode_rasterizer_state(vctx
, handle
, rs_state
);
346 return (void *)(unsigned long)handle
;
349 static void virgl_bind_rasterizer_state(struct pipe_context
*ctx
,
352 struct virgl_context
*vctx
= virgl_context(ctx
);
353 uint32_t handle
= (unsigned long)rs_state
;
355 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
358 static void virgl_delete_rasterizer_state(struct pipe_context
*ctx
,
361 struct virgl_context
*vctx
= virgl_context(ctx
);
362 uint32_t handle
= (unsigned long)rs_state
;
363 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
366 static void virgl_set_framebuffer_state(struct pipe_context
*ctx
,
367 const struct pipe_framebuffer_state
*state
)
369 struct virgl_context
*vctx
= virgl_context(ctx
);
371 vctx
->framebuffer
= *state
;
372 virgl_encoder_set_framebuffer_state(vctx
, state
);
373 virgl_attach_res_framebuffer(vctx
);
376 static void virgl_set_viewport_states(struct pipe_context
*ctx
,
378 unsigned num_viewports
,
379 const struct pipe_viewport_state
*state
)
381 struct virgl_context
*vctx
= virgl_context(ctx
);
382 virgl_encoder_set_viewport_states(vctx
, start_slot
, num_viewports
, state
);
385 static void *virgl_create_vertex_elements_state(struct pipe_context
*ctx
,
386 unsigned num_elements
,
387 const struct pipe_vertex_element
*elements
)
389 struct virgl_context
*vctx
= virgl_context(ctx
);
390 uint32_t handle
= virgl_object_assign_handle();
391 virgl_encoder_create_vertex_elements(vctx
, handle
,
392 num_elements
, elements
);
393 return (void*)(unsigned long)handle
;
397 static void virgl_delete_vertex_elements_state(struct pipe_context
*ctx
,
400 struct virgl_context
*vctx
= virgl_context(ctx
);
401 uint32_t handle
= (unsigned long)ve
;
403 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_VERTEX_ELEMENTS
);
406 static void virgl_bind_vertex_elements_state(struct pipe_context
*ctx
,
409 struct virgl_context
*vctx
= virgl_context(ctx
);
410 uint32_t handle
= (unsigned long)ve
;
411 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_VERTEX_ELEMENTS
);
414 static void virgl_set_vertex_buffers(struct pipe_context
*ctx
,
416 unsigned num_buffers
,
417 const struct pipe_vertex_buffer
*buffers
)
419 struct virgl_context
*vctx
= virgl_context(ctx
);
421 util_set_vertex_buffers_count(vctx
->vertex_buffer
,
422 &vctx
->num_vertex_buffers
,
423 buffers
, start_slot
, num_buffers
);
425 vctx
->vertex_array_dirty
= TRUE
;
428 static void virgl_hw_set_vertex_buffers(struct virgl_context
*vctx
)
430 if (vctx
->vertex_array_dirty
) {
431 virgl_encoder_set_vertex_buffers(vctx
, vctx
->num_vertex_buffers
, vctx
->vertex_buffer
);
432 virgl_attach_res_vertex_buffers(vctx
);
436 static void virgl_set_stencil_ref(struct pipe_context
*ctx
,
437 const struct pipe_stencil_ref
*ref
)
439 struct virgl_context
*vctx
= virgl_context(ctx
);
440 virgl_encoder_set_stencil_ref(vctx
, ref
);
443 static void virgl_set_blend_color(struct pipe_context
*ctx
,
444 const struct pipe_blend_color
*color
)
446 struct virgl_context
*vctx
= virgl_context(ctx
);
447 virgl_encoder_set_blend_color(vctx
, color
);
450 static void virgl_hw_set_index_buffer(struct virgl_context
*vctx
,
451 struct virgl_indexbuf
*ib
)
453 virgl_encoder_set_index_buffer(vctx
, ib
);
454 virgl_attach_res_index_buffer(vctx
, ib
);
457 static void virgl_set_constant_buffer(struct pipe_context
*ctx
,
458 enum pipe_shader_type shader
, uint index
,
459 const struct pipe_constant_buffer
*buf
)
461 struct virgl_context
*vctx
= virgl_context(ctx
);
464 if (!buf
->user_buffer
){
465 struct virgl_resource
*res
= virgl_resource(buf
->buffer
);
466 virgl_encoder_set_uniform_buffer(vctx
, shader
, index
, buf
->buffer_offset
,
467 buf
->buffer_size
, res
);
468 pipe_resource_reference(&vctx
->ubos
[shader
][index
], buf
->buffer
);
471 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
472 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, buf
->buffer_size
/ 4, buf
->user_buffer
);
474 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, 0, NULL
);
475 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
479 void virgl_transfer_inline_write(struct pipe_context
*ctx
,
480 struct pipe_resource
*res
,
483 const struct pipe_box
*box
,
486 unsigned layer_stride
)
488 struct virgl_context
*vctx
= virgl_context(ctx
);
489 struct virgl_screen
*vs
= virgl_screen(ctx
->screen
);
490 struct virgl_resource
*grres
= virgl_resource(res
);
491 struct virgl_buffer
*vbuf
= virgl_buffer(res
);
493 grres
->clean
= FALSE
;
495 if (virgl_res_needs_flush_wait(vctx
, &vbuf
->base
, usage
)) {
496 ctx
->flush(ctx
, NULL
, 0);
498 vs
->vws
->resource_wait(vs
->vws
, vbuf
->base
.hw_res
);
501 virgl_encoder_inline_write(vctx
, grres
, level
, usage
,
502 box
, data
, stride
, layer_stride
);
505 static void *virgl_shader_encoder(struct pipe_context
*ctx
,
506 const struct pipe_shader_state
*shader
,
509 struct virgl_context
*vctx
= virgl_context(ctx
);
511 struct tgsi_token
*new_tokens
;
514 new_tokens
= virgl_tgsi_transform(vctx
, shader
->tokens
);
518 handle
= virgl_object_assign_handle();
519 /* encode VS state */
520 ret
= virgl_encode_shader_state(vctx
, handle
, type
,
521 &shader
->stream_output
, 0,
528 return (void *)(unsigned long)handle
;
531 static void *virgl_create_vs_state(struct pipe_context
*ctx
,
532 const struct pipe_shader_state
*shader
)
534 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_VERTEX
);
537 static void *virgl_create_tcs_state(struct pipe_context
*ctx
,
538 const struct pipe_shader_state
*shader
)
540 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_CTRL
);
543 static void *virgl_create_tes_state(struct pipe_context
*ctx
,
544 const struct pipe_shader_state
*shader
)
546 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_EVAL
);
549 static void *virgl_create_gs_state(struct pipe_context
*ctx
,
550 const struct pipe_shader_state
*shader
)
552 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_GEOMETRY
);
555 static void *virgl_create_fs_state(struct pipe_context
*ctx
,
556 const struct pipe_shader_state
*shader
)
558 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_FRAGMENT
);
562 virgl_delete_fs_state(struct pipe_context
*ctx
,
565 uint32_t handle
= (unsigned long)fs
;
566 struct virgl_context
*vctx
= virgl_context(ctx
);
568 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
572 virgl_delete_gs_state(struct pipe_context
*ctx
,
575 uint32_t handle
= (unsigned long)gs
;
576 struct virgl_context
*vctx
= virgl_context(ctx
);
578 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
582 virgl_delete_vs_state(struct pipe_context
*ctx
,
585 uint32_t handle
= (unsigned long)vs
;
586 struct virgl_context
*vctx
= virgl_context(ctx
);
588 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
592 virgl_delete_tcs_state(struct pipe_context
*ctx
,
595 uint32_t handle
= (unsigned long)tcs
;
596 struct virgl_context
*vctx
= virgl_context(ctx
);
598 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
602 virgl_delete_tes_state(struct pipe_context
*ctx
,
605 uint32_t handle
= (unsigned long)tes
;
606 struct virgl_context
*vctx
= virgl_context(ctx
);
608 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
611 static void virgl_bind_vs_state(struct pipe_context
*ctx
,
614 uint32_t handle
= (unsigned long)vss
;
615 struct virgl_context
*vctx
= virgl_context(ctx
);
617 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_VERTEX
);
620 static void virgl_bind_tcs_state(struct pipe_context
*ctx
,
623 uint32_t handle
= (unsigned long)vss
;
624 struct virgl_context
*vctx
= virgl_context(ctx
);
626 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_CTRL
);
629 static void virgl_bind_tes_state(struct pipe_context
*ctx
,
632 uint32_t handle
= (unsigned long)vss
;
633 struct virgl_context
*vctx
= virgl_context(ctx
);
635 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_EVAL
);
638 static void virgl_bind_gs_state(struct pipe_context
*ctx
,
641 uint32_t handle
= (unsigned long)vss
;
642 struct virgl_context
*vctx
= virgl_context(ctx
);
644 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_GEOMETRY
);
648 static void virgl_bind_fs_state(struct pipe_context
*ctx
,
651 uint32_t handle
= (unsigned long)vss
;
652 struct virgl_context
*vctx
= virgl_context(ctx
);
654 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_FRAGMENT
);
657 static void virgl_clear(struct pipe_context
*ctx
,
659 const union pipe_color_union
*color
,
660 double depth
, unsigned stencil
)
662 struct virgl_context
*vctx
= virgl_context(ctx
);
664 virgl_encode_clear(vctx
, buffers
, color
, depth
, stencil
);
667 static void virgl_draw_vbo(struct pipe_context
*ctx
,
668 const struct pipe_draw_info
*dinfo
)
670 struct virgl_context
*vctx
= virgl_context(ctx
);
671 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
672 struct virgl_indexbuf ib
= {};
673 struct pipe_draw_info info
= *dinfo
;
675 if (!dinfo
->count_from_stream_output
&& !dinfo
->indirect
&&
676 !dinfo
->primitive_restart
&&
677 !u_trim_pipe_prim(dinfo
->mode
, (unsigned*)&dinfo
->count
))
680 if (!(rs
->caps
.caps
.v1
.prim_mask
& (1 << dinfo
->mode
))) {
681 util_primconvert_draw_vbo(vctx
->primconvert
, dinfo
);
684 if (info
.index_size
) {
685 pipe_resource_reference(&ib
.buffer
, info
.has_user_indices
? NULL
: info
.index
.resource
);
686 ib
.user_buffer
= info
.has_user_indices
? info
.index
.user
: NULL
;
687 ib
.index_size
= dinfo
->index_size
;
688 ib
.offset
= info
.start
* ib
.index_size
;
690 if (ib
.user_buffer
) {
691 u_upload_data(vctx
->uploader
, 0, info
.count
* ib
.index_size
, 256,
692 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
693 ib
.user_buffer
= NULL
;
697 u_upload_unmap(vctx
->uploader
);
700 virgl_hw_set_vertex_buffers(vctx
);
702 virgl_hw_set_index_buffer(vctx
, &ib
);
704 virgl_encoder_draw_vbo(vctx
, &info
);
706 pipe_resource_reference(&ib
.buffer
, NULL
);
710 static void virgl_flush_eq(struct virgl_context
*ctx
, void *closure
,
711 struct pipe_fence_handle
**fence
)
713 struct virgl_screen
*rs
= virgl_screen(ctx
->base
.screen
);
714 int out_fence_fd
= -1;
716 /* send the buffer to the remote side for decoding */
717 ctx
->num_transfers
= ctx
->num_draws
= 0;
719 rs
->vws
->submit_cmd(rs
->vws
, ctx
->cbuf
, ctx
->cbuf
->in_fence_fd
,
720 ctx
->cbuf
->needs_out_fence_fd
? &out_fence_fd
: NULL
);
723 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, out_fence_fd
);
725 virgl_encoder_set_sub_ctx(ctx
, ctx
->hw_sub_ctx_id
);
727 /* add back current framebuffer resources to reference list? */
728 virgl_reemit_res(ctx
);
731 static void virgl_flush_from_st(struct pipe_context
*ctx
,
732 struct pipe_fence_handle
**fence
,
733 enum pipe_flush_flags flags
)
735 struct virgl_context
*vctx
= virgl_context(ctx
);
736 struct virgl_buffer
*buf
, *tmp
;
738 if (flags
& PIPE_FLUSH_FENCE_FD
)
739 vctx
->cbuf
->needs_out_fence_fd
= true;
741 LIST_FOR_EACH_ENTRY_SAFE(buf
, tmp
, &vctx
->to_flush_bufs
, flush_list
) {
742 struct pipe_resource
*res
= &buf
->base
.u
.b
;
743 virgl_buffer_flush(vctx
, buf
);
744 list_del(&buf
->flush_list
);
745 buf
->on_list
= FALSE
;
746 pipe_resource_reference(&res
, NULL
);
749 virgl_flush_eq(vctx
, vctx
, fence
);
751 if (vctx
->cbuf
->in_fence_fd
!= -1) {
752 close(vctx
->cbuf
->in_fence_fd
);
753 vctx
->cbuf
->in_fence_fd
= -1;
755 vctx
->cbuf
->needs_out_fence_fd
= false;
758 static struct pipe_sampler_view
*virgl_create_sampler_view(struct pipe_context
*ctx
,
759 struct pipe_resource
*texture
,
760 const struct pipe_sampler_view
*state
)
762 struct virgl_context
*vctx
= virgl_context(ctx
);
763 struct virgl_sampler_view
*grview
;
765 struct virgl_resource
*res
;
770 grview
= CALLOC_STRUCT(virgl_sampler_view
);
774 res
= virgl_resource(texture
);
775 handle
= virgl_object_assign_handle();
776 virgl_encode_sampler_view(vctx
, handle
, res
, state
);
778 grview
->base
= *state
;
779 grview
->base
.reference
.count
= 1;
781 grview
->base
.texture
= NULL
;
782 grview
->base
.context
= ctx
;
783 pipe_resource_reference(&grview
->base
.texture
, texture
);
784 grview
->handle
= handle
;
785 return &grview
->base
;
788 static void virgl_set_sampler_views(struct pipe_context
*ctx
,
789 enum pipe_shader_type shader_type
,
792 struct pipe_sampler_view
**views
)
794 struct virgl_context
*vctx
= virgl_context(ctx
);
796 uint32_t disable_mask
= ~((1ull << num_views
) - 1);
797 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
798 uint32_t new_mask
= 0;
799 uint32_t remaining_mask
;
801 remaining_mask
= tinfo
->enabled_mask
& disable_mask
;
803 while (remaining_mask
) {
804 i
= u_bit_scan(&remaining_mask
);
805 assert(tinfo
->views
[i
]);
807 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
810 for (i
= 0; i
< num_views
; i
++) {
811 struct virgl_sampler_view
*grview
= virgl_sampler_view(views
[i
]);
813 if (views
[i
] == (struct pipe_sampler_view
*)tinfo
->views
[i
])
818 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], views
[i
]);
820 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
821 disable_mask
|= 1 << i
;
825 tinfo
->enabled_mask
&= ~disable_mask
;
826 tinfo
->enabled_mask
|= new_mask
;
827 virgl_encode_set_sampler_views(vctx
, shader_type
, start_slot
, num_views
, tinfo
->views
);
828 virgl_attach_res_sampler_views(vctx
, shader_type
);
832 virgl_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
834 struct virgl_context
*vctx
= virgl_context(ctx
);
835 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
837 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_BARRIER
))
839 virgl_encode_texture_barrier(vctx
, flags
);
842 static void virgl_destroy_sampler_view(struct pipe_context
*ctx
,
843 struct pipe_sampler_view
*view
)
845 struct virgl_context
*vctx
= virgl_context(ctx
);
846 struct virgl_sampler_view
*grview
= virgl_sampler_view(view
);
848 virgl_encode_delete_object(vctx
, grview
->handle
, VIRGL_OBJECT_SAMPLER_VIEW
);
849 pipe_resource_reference(&view
->texture
, NULL
);
853 static void *virgl_create_sampler_state(struct pipe_context
*ctx
,
854 const struct pipe_sampler_state
*state
)
856 struct virgl_context
*vctx
= virgl_context(ctx
);
859 handle
= virgl_object_assign_handle();
861 virgl_encode_sampler_state(vctx
, handle
, state
);
862 return (void *)(unsigned long)handle
;
865 static void virgl_delete_sampler_state(struct pipe_context
*ctx
,
868 struct virgl_context
*vctx
= virgl_context(ctx
);
869 uint32_t handle
= (unsigned long)ss
;
871 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SAMPLER_STATE
);
874 static void virgl_bind_sampler_states(struct pipe_context
*ctx
,
875 enum pipe_shader_type shader
,
877 unsigned num_samplers
,
880 struct virgl_context
*vctx
= virgl_context(ctx
);
881 uint32_t handles
[32];
883 for (i
= 0; i
< num_samplers
; i
++) {
884 handles
[i
] = (unsigned long)(samplers
[i
]);
886 virgl_encode_bind_sampler_states(vctx
, shader
, start_slot
, num_samplers
, handles
);
889 static void virgl_set_polygon_stipple(struct pipe_context
*ctx
,
890 const struct pipe_poly_stipple
*ps
)
892 struct virgl_context
*vctx
= virgl_context(ctx
);
893 virgl_encoder_set_polygon_stipple(vctx
, ps
);
896 static void virgl_set_scissor_states(struct pipe_context
*ctx
,
898 unsigned num_scissor
,
899 const struct pipe_scissor_state
*ss
)
901 struct virgl_context
*vctx
= virgl_context(ctx
);
902 virgl_encoder_set_scissor_state(vctx
, start_slot
, num_scissor
, ss
);
905 static void virgl_set_sample_mask(struct pipe_context
*ctx
,
906 unsigned sample_mask
)
908 struct virgl_context
*vctx
= virgl_context(ctx
);
909 virgl_encoder_set_sample_mask(vctx
, sample_mask
);
912 static void virgl_set_min_samples(struct pipe_context
*ctx
,
913 unsigned min_samples
)
915 struct virgl_context
*vctx
= virgl_context(ctx
);
916 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
918 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SET_MIN_SAMPLES
))
920 virgl_encoder_set_min_samples(vctx
, min_samples
);
923 static void virgl_set_clip_state(struct pipe_context
*ctx
,
924 const struct pipe_clip_state
*clip
)
926 struct virgl_context
*vctx
= virgl_context(ctx
);
927 virgl_encoder_set_clip_state(vctx
, clip
);
930 static void virgl_set_tess_state(struct pipe_context
*ctx
,
931 const float default_outer_level
[4],
932 const float default_inner_level
[2])
934 struct virgl_context
*vctx
= virgl_context(ctx
);
935 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
937 if (!rs
->caps
.caps
.v1
.bset
.has_tessellation_shaders
)
939 virgl_encode_set_tess_state(vctx
, default_outer_level
, default_inner_level
);
942 static void virgl_resource_copy_region(struct pipe_context
*ctx
,
943 struct pipe_resource
*dst
,
945 unsigned dstx
, unsigned dsty
, unsigned dstz
,
946 struct pipe_resource
*src
,
948 const struct pipe_box
*src_box
)
950 struct virgl_context
*vctx
= virgl_context(ctx
);
951 struct virgl_resource
*dres
= virgl_resource(dst
);
952 struct virgl_resource
*sres
= virgl_resource(src
);
955 virgl_encode_resource_copy_region(vctx
, dres
,
956 dst_level
, dstx
, dsty
, dstz
,
962 virgl_flush_resource(struct pipe_context
*pipe
,
963 struct pipe_resource
*resource
)
967 static void virgl_blit(struct pipe_context
*ctx
,
968 const struct pipe_blit_info
*blit
)
970 struct virgl_context
*vctx
= virgl_context(ctx
);
971 struct virgl_resource
*dres
= virgl_resource(blit
->dst
.resource
);
972 struct virgl_resource
*sres
= virgl_resource(blit
->src
.resource
);
975 virgl_encode_blit(vctx
, dres
, sres
,
979 static void virgl_set_hw_atomic_buffers(struct pipe_context
*ctx
,
982 const struct pipe_shader_buffer
*buffers
)
984 struct virgl_context
*vctx
= virgl_context(ctx
);
986 for (unsigned i
= 0; i
< count
; i
++) {
987 unsigned idx
= start_slot
+ i
;
990 if (buffers
[i
].buffer
) {
991 pipe_resource_reference(&vctx
->atomic_buffers
[idx
],
996 pipe_resource_reference(&vctx
->atomic_buffers
[idx
], NULL
);
998 virgl_encode_set_hw_atomic_buffers(vctx
, start_slot
, count
, buffers
);
1001 static void virgl_set_shader_buffers(struct pipe_context
*ctx
,
1002 enum pipe_shader_type shader
,
1003 unsigned start_slot
, unsigned count
,
1004 const struct pipe_shader_buffer
*buffers
)
1006 struct virgl_context
*vctx
= virgl_context(ctx
);
1007 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1009 for (unsigned i
= 0; i
< count
; i
++) {
1010 unsigned idx
= start_slot
+ i
;
1013 if (buffers
[i
].buffer
) {
1014 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], buffers
[i
].buffer
);
1018 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], NULL
);
1021 uint32_t max_shader_buffer
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1022 rs
->caps
.caps
.v2
.max_shader_buffer_frag_compute
:
1023 rs
->caps
.caps
.v2
.max_shader_buffer_other_stages
;
1024 if (!max_shader_buffer
)
1026 virgl_encode_set_shader_buffers(vctx
, shader
, start_slot
, count
, buffers
);
1029 static void virgl_create_fence_fd(struct pipe_context
*ctx
,
1030 struct pipe_fence_handle
**fence
,
1032 enum pipe_fd_type type
)
1034 assert(type
== PIPE_FD_TYPE_NATIVE_SYNC
);
1035 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1037 if (rs
->vws
->cs_create_fence
)
1038 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, fd
);
1041 static void virgl_fence_server_sync(struct pipe_context
*ctx
,
1042 struct pipe_fence_handle
*fence
)
1044 struct virgl_context
*vctx
= virgl_context(ctx
);
1045 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1047 if (rs
->vws
->fence_server_sync
)
1048 rs
->vws
->fence_server_sync(rs
->vws
, vctx
->cbuf
, fence
);
1051 static void virgl_set_shader_images(struct pipe_context
*ctx
,
1052 enum pipe_shader_type shader
,
1053 unsigned start_slot
, unsigned count
,
1054 const struct pipe_image_view
*images
)
1056 struct virgl_context
*vctx
= virgl_context(ctx
);
1057 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1059 for (unsigned i
= 0; i
< count
; i
++) {
1060 unsigned idx
= start_slot
+ i
;
1063 if (images
[i
].resource
) {
1064 pipe_resource_reference(&vctx
->images
[shader
][idx
], images
[i
].resource
);
1068 pipe_resource_reference(&vctx
->images
[shader
][idx
], NULL
);
1071 uint32_t max_shader_images
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1072 rs
->caps
.caps
.v2
.max_shader_image_frag_compute
:
1073 rs
->caps
.caps
.v2
.max_shader_image_other_stages
;
1074 if (!max_shader_images
)
1076 virgl_encode_set_shader_images(vctx
, shader
, start_slot
, count
, images
);
1079 static void virgl_memory_barrier(struct pipe_context
*ctx
,
1082 struct virgl_context
*vctx
= virgl_context(ctx
);
1083 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1085 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_MEMORY_BARRIER
))
1087 virgl_encode_memory_barrier(vctx
, flags
);
1090 static void *virgl_create_compute_state(struct pipe_context
*ctx
,
1091 const struct pipe_compute_state
*state
)
1093 struct virgl_context
*vctx
= virgl_context(ctx
);
1095 const struct tgsi_token
*new_tokens
= state
->prog
;
1096 struct pipe_stream_output_info so_info
= {};
1099 handle
= virgl_object_assign_handle();
1100 ret
= virgl_encode_shader_state(vctx
, handle
, PIPE_SHADER_COMPUTE
,
1102 state
->req_local_mem
,
1108 return (void *)(unsigned long)handle
;
1111 static void virgl_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1113 uint32_t handle
= (unsigned long)state
;
1114 struct virgl_context
*vctx
= virgl_context(ctx
);
1116 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_COMPUTE
);
1119 static void virgl_delete_compute_state(struct pipe_context
*ctx
, void *state
)
1121 uint32_t handle
= (unsigned long)state
;
1122 struct virgl_context
*vctx
= virgl_context(ctx
);
1124 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
1127 static void virgl_launch_grid(struct pipe_context
*ctx
,
1128 const struct pipe_grid_info
*info
)
1130 struct virgl_context
*vctx
= virgl_context(ctx
);
1131 virgl_encode_launch_grid(vctx
, info
);
1135 virgl_context_destroy( struct pipe_context
*ctx
)
1137 struct virgl_context
*vctx
= virgl_context(ctx
);
1138 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1140 vctx
->framebuffer
.zsbuf
= NULL
;
1141 vctx
->framebuffer
.nr_cbufs
= 0;
1142 virgl_encoder_destroy_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1143 virgl_flush_eq(vctx
, vctx
, NULL
);
1145 rs
->vws
->cmd_buf_destroy(vctx
->cbuf
);
1147 u_upload_destroy(vctx
->uploader
);
1148 util_primconvert_destroy(vctx
->primconvert
);
1150 slab_destroy_child(&vctx
->texture_transfer_pool
);
1154 static void virgl_get_sample_position(struct pipe_context
*ctx
,
1155 unsigned sample_count
,
1159 struct virgl_context
*vctx
= virgl_context(ctx
);
1160 struct virgl_screen
*vs
= virgl_screen(vctx
->base
.screen
);
1162 if (sample_count
> vs
->caps
.caps
.v1
.max_samples
) {
1163 debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1164 sample_count
, vs
->caps
.caps
.v1
.max_samples
);
1168 /* The following is basically copied from dri/i965gen6_get_sample_position
1169 * The only addition is that we hold the msaa positions for all sample
1170 * counts in a flat array. */
1172 if (sample_count
== 1) {
1173 out_value
[0] = out_value
[1] = 0.5f
;
1175 } else if (sample_count
== 2) {
1176 bits
= vs
->caps
.caps
.v2
.sample_locations
[0] >> (8 * index
);
1177 } else if (sample_count
<= 4) {
1178 bits
= vs
->caps
.caps
.v2
.sample_locations
[1] >> (8 * index
);
1179 } else if (sample_count
<= 8) {
1180 bits
= vs
->caps
.caps
.v2
.sample_locations
[2 + (index
>> 2)] >> (8 * (index
& 3));
1181 } else if (sample_count
<= 16) {
1182 bits
= vs
->caps
.caps
.v2
.sample_locations
[4 + (index
>> 2)] >> (8 * (index
& 3));
1184 out_value
[0] = ((bits
>> 4) & 0xf) / 16.0f
;
1185 out_value
[1] = (bits
& 0xf) / 16.0f
;
1187 if (virgl_debug
& VIRGL_DEBUG_VERBOSE
)
1188 debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1189 index
, sample_count
, out_value
[0], out_value
[1]);
1192 struct pipe_context
*virgl_context_create(struct pipe_screen
*pscreen
,
1196 struct virgl_context
*vctx
;
1197 struct virgl_screen
*rs
= virgl_screen(pscreen
);
1198 vctx
= CALLOC_STRUCT(virgl_context
);
1199 const char *host_debug_flagstring
;
1201 vctx
->cbuf
= rs
->vws
->cmd_buf_create(rs
->vws
);
1207 vctx
->base
.destroy
= virgl_context_destroy
;
1208 vctx
->base
.create_surface
= virgl_create_surface
;
1209 vctx
->base
.surface_destroy
= virgl_surface_destroy
;
1210 vctx
->base
.set_framebuffer_state
= virgl_set_framebuffer_state
;
1211 vctx
->base
.create_blend_state
= virgl_create_blend_state
;
1212 vctx
->base
.bind_blend_state
= virgl_bind_blend_state
;
1213 vctx
->base
.delete_blend_state
= virgl_delete_blend_state
;
1214 vctx
->base
.create_depth_stencil_alpha_state
= virgl_create_depth_stencil_alpha_state
;
1215 vctx
->base
.bind_depth_stencil_alpha_state
= virgl_bind_depth_stencil_alpha_state
;
1216 vctx
->base
.delete_depth_stencil_alpha_state
= virgl_delete_depth_stencil_alpha_state
;
1217 vctx
->base
.create_rasterizer_state
= virgl_create_rasterizer_state
;
1218 vctx
->base
.bind_rasterizer_state
= virgl_bind_rasterizer_state
;
1219 vctx
->base
.delete_rasterizer_state
= virgl_delete_rasterizer_state
;
1221 vctx
->base
.set_viewport_states
= virgl_set_viewport_states
;
1222 vctx
->base
.create_vertex_elements_state
= virgl_create_vertex_elements_state
;
1223 vctx
->base
.bind_vertex_elements_state
= virgl_bind_vertex_elements_state
;
1224 vctx
->base
.delete_vertex_elements_state
= virgl_delete_vertex_elements_state
;
1225 vctx
->base
.set_vertex_buffers
= virgl_set_vertex_buffers
;
1226 vctx
->base
.set_constant_buffer
= virgl_set_constant_buffer
;
1228 vctx
->base
.set_tess_state
= virgl_set_tess_state
;
1229 vctx
->base
.create_vs_state
= virgl_create_vs_state
;
1230 vctx
->base
.create_tcs_state
= virgl_create_tcs_state
;
1231 vctx
->base
.create_tes_state
= virgl_create_tes_state
;
1232 vctx
->base
.create_gs_state
= virgl_create_gs_state
;
1233 vctx
->base
.create_fs_state
= virgl_create_fs_state
;
1235 vctx
->base
.bind_vs_state
= virgl_bind_vs_state
;
1236 vctx
->base
.bind_tcs_state
= virgl_bind_tcs_state
;
1237 vctx
->base
.bind_tes_state
= virgl_bind_tes_state
;
1238 vctx
->base
.bind_gs_state
= virgl_bind_gs_state
;
1239 vctx
->base
.bind_fs_state
= virgl_bind_fs_state
;
1241 vctx
->base
.delete_vs_state
= virgl_delete_vs_state
;
1242 vctx
->base
.delete_tcs_state
= virgl_delete_tcs_state
;
1243 vctx
->base
.delete_tes_state
= virgl_delete_tes_state
;
1244 vctx
->base
.delete_gs_state
= virgl_delete_gs_state
;
1245 vctx
->base
.delete_fs_state
= virgl_delete_fs_state
;
1247 vctx
->base
.create_compute_state
= virgl_create_compute_state
;
1248 vctx
->base
.bind_compute_state
= virgl_bind_compute_state
;
1249 vctx
->base
.delete_compute_state
= virgl_delete_compute_state
;
1250 vctx
->base
.launch_grid
= virgl_launch_grid
;
1252 vctx
->base
.clear
= virgl_clear
;
1253 vctx
->base
.draw_vbo
= virgl_draw_vbo
;
1254 vctx
->base
.flush
= virgl_flush_from_st
;
1255 vctx
->base
.screen
= pscreen
;
1256 vctx
->base
.create_sampler_view
= virgl_create_sampler_view
;
1257 vctx
->base
.sampler_view_destroy
= virgl_destroy_sampler_view
;
1258 vctx
->base
.set_sampler_views
= virgl_set_sampler_views
;
1259 vctx
->base
.texture_barrier
= virgl_texture_barrier
;
1261 vctx
->base
.create_sampler_state
= virgl_create_sampler_state
;
1262 vctx
->base
.delete_sampler_state
= virgl_delete_sampler_state
;
1263 vctx
->base
.bind_sampler_states
= virgl_bind_sampler_states
;
1265 vctx
->base
.set_polygon_stipple
= virgl_set_polygon_stipple
;
1266 vctx
->base
.set_scissor_states
= virgl_set_scissor_states
;
1267 vctx
->base
.set_sample_mask
= virgl_set_sample_mask
;
1268 vctx
->base
.set_min_samples
= virgl_set_min_samples
;
1269 vctx
->base
.set_stencil_ref
= virgl_set_stencil_ref
;
1270 vctx
->base
.set_clip_state
= virgl_set_clip_state
;
1272 vctx
->base
.set_blend_color
= virgl_set_blend_color
;
1274 vctx
->base
.get_sample_position
= virgl_get_sample_position
;
1276 vctx
->base
.resource_copy_region
= virgl_resource_copy_region
;
1277 vctx
->base
.flush_resource
= virgl_flush_resource
;
1278 vctx
->base
.blit
= virgl_blit
;
1279 vctx
->base
.create_fence_fd
= virgl_create_fence_fd
;
1280 vctx
->base
.fence_server_sync
= virgl_fence_server_sync
;
1282 vctx
->base
.set_shader_buffers
= virgl_set_shader_buffers
;
1283 vctx
->base
.set_hw_atomic_buffers
= virgl_set_hw_atomic_buffers
;
1284 vctx
->base
.set_shader_images
= virgl_set_shader_images
;
1285 vctx
->base
.memory_barrier
= virgl_memory_barrier
;
1287 virgl_init_context_resource_functions(&vctx
->base
);
1288 virgl_init_query_functions(vctx
);
1289 virgl_init_so_functions(vctx
);
1291 list_inithead(&vctx
->to_flush_bufs
);
1292 slab_create_child(&vctx
->texture_transfer_pool
, &rs
->texture_transfer_pool
);
1294 vctx
->primconvert
= util_primconvert_create(&vctx
->base
, rs
->caps
.caps
.v1
.prim_mask
);
1295 vctx
->uploader
= u_upload_create(&vctx
->base
, 1024 * 1024,
1296 PIPE_BIND_INDEX_BUFFER
, PIPE_USAGE_STREAM
, 0);
1297 if (!vctx
->uploader
)
1299 vctx
->base
.stream_uploader
= vctx
->uploader
;
1300 vctx
->base
.const_uploader
= vctx
->uploader
;
1302 vctx
->hw_sub_ctx_id
= rs
->sub_ctx_id
++;
1303 virgl_encoder_create_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1305 virgl_encoder_set_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1307 if (rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_GUEST_MAY_INIT_LOG
) {
1308 host_debug_flagstring
= getenv("VIRGL_HOST_DEBUG");
1309 if (host_debug_flagstring
)
1310 virgl_encode_host_debug_flagstring(vctx
, host_debug_flagstring
);