2 * Copyright 2014, 2015 Red Hat.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "pipe/p_shader_tokens.h"
27 #include "pipe/p_context.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
31 #include "util/u_inlines.h"
32 #include "util/u_memory.h"
33 #include "util/u_format.h"
34 #include "util/u_prim.h"
35 #include "util/u_transfer.h"
36 #include "util/u_helpers.h"
37 #include "util/slab.h"
38 #include "util/u_upload_mgr.h"
39 #include "util/u_blitter.h"
40 #include "tgsi/tgsi_text.h"
41 #include "indices/u_primconvert.h"
43 #include "pipebuffer/pb_buffer.h"
45 #include "virgl_encode.h"
46 #include "virgl_context.h"
47 #include "virgl_protocol.h"
48 #include "virgl_resource.h"
49 #include "virgl_screen.h"
51 struct virgl_vertex_elements_state
{
53 uint8_t binding_map
[PIPE_MAX_ATTRIBS
];
57 static uint32_t next_handle
;
58 uint32_t virgl_object_assign_handle(void)
63 static void virgl_buffer_flush(struct virgl_context
*vctx
,
64 struct virgl_buffer
*vbuf
)
66 struct virgl_screen
*rs
= virgl_screen(vctx
->base
.screen
);
69 assert(vbuf
->on_list
);
76 box
.x
= vbuf
->valid_buffer_range
.start
;
77 box
.width
= MIN2(vbuf
->valid_buffer_range
.end
- vbuf
->valid_buffer_range
.start
, vbuf
->base
.u
.b
.width0
);
79 vctx
->num_transfers
++;
80 rs
->vws
->transfer_put(rs
->vws
, vbuf
->base
.hw_res
,
81 &box
, 0, 0, box
.x
, 0);
83 util_range_set_empty(&vbuf
->valid_buffer_range
);
86 static void virgl_attach_res_framebuffer(struct virgl_context
*vctx
)
88 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
89 struct pipe_surface
*surf
;
90 struct virgl_resource
*res
;
93 surf
= vctx
->framebuffer
.zsbuf
;
95 res
= virgl_resource(surf
->texture
);
97 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
99 for (i
= 0; i
< vctx
->framebuffer
.nr_cbufs
; i
++) {
100 surf
= vctx
->framebuffer
.cbufs
[i
];
102 res
= virgl_resource(surf
->texture
);
104 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
109 static void virgl_attach_res_sampler_views(struct virgl_context
*vctx
,
110 enum pipe_shader_type shader_type
)
112 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
113 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
114 struct virgl_resource
*res
;
115 uint32_t remaining_mask
= tinfo
->enabled_mask
;
117 while (remaining_mask
) {
118 i
= u_bit_scan(&remaining_mask
);
119 assert(tinfo
->views
[i
]);
121 res
= virgl_resource(tinfo
->views
[i
]->base
.texture
);
123 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
127 static void virgl_attach_res_vertex_buffers(struct virgl_context
*vctx
)
129 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
130 struct virgl_resource
*res
;
133 for (i
= 0; i
< vctx
->num_vertex_buffers
; i
++) {
134 res
= virgl_resource(vctx
->vertex_buffer
[i
].buffer
.resource
);
136 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
140 static void virgl_attach_res_index_buffer(struct virgl_context
*vctx
,
141 struct virgl_indexbuf
*ib
)
143 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
144 struct virgl_resource
*res
;
146 res
= virgl_resource(ib
->buffer
);
148 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
151 static void virgl_attach_res_so_targets(struct virgl_context
*vctx
)
153 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
154 struct virgl_resource
*res
;
157 for (i
= 0; i
< vctx
->num_so_targets
; i
++) {
158 res
= virgl_resource(vctx
->so_targets
[i
].base
.buffer
);
160 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
164 static void virgl_attach_res_uniform_buffers(struct virgl_context
*vctx
,
165 enum pipe_shader_type shader_type
)
167 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
168 struct virgl_resource
*res
;
170 for (i
= 0; i
< PIPE_MAX_CONSTANT_BUFFERS
; i
++) {
171 res
= virgl_resource(vctx
->ubos
[shader_type
][i
]);
173 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
178 static void virgl_attach_res_shader_buffers(struct virgl_context
*vctx
,
179 enum pipe_shader_type shader_type
)
181 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
182 struct virgl_resource
*res
;
184 for (i
= 0; i
< PIPE_MAX_SHADER_BUFFERS
; i
++) {
185 res
= virgl_resource(vctx
->ssbos
[shader_type
][i
]);
187 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
192 static void virgl_attach_res_shader_images(struct virgl_context
*vctx
,
193 enum pipe_shader_type shader_type
)
195 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
196 struct virgl_resource
*res
;
198 for (i
= 0; i
< PIPE_MAX_SHADER_IMAGES
; i
++) {
199 res
= virgl_resource(vctx
->images
[shader_type
][i
]);
201 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
206 static void virgl_attach_res_atomic_buffers(struct virgl_context
*vctx
)
208 struct virgl_winsys
*vws
= virgl_screen(vctx
->base
.screen
)->vws
;
209 struct virgl_resource
*res
;
211 for (i
= 0; i
< PIPE_MAX_HW_ATOMIC_BUFFERS
; i
++) {
212 res
= virgl_resource(vctx
->atomic_buffers
[i
]);
214 vws
->emit_res(vws
, vctx
->cbuf
, res
->hw_res
, FALSE
);
220 * after flushing, the hw context still has a bunch of
221 * resources bound, so we need to rebind those here.
223 static void virgl_reemit_res(struct virgl_context
*vctx
)
225 enum pipe_shader_type shader_type
;
227 /* reattach any flushed resources */
228 /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
229 virgl_attach_res_framebuffer(vctx
);
231 for (shader_type
= 0; shader_type
< PIPE_SHADER_TYPES
; shader_type
++) {
232 virgl_attach_res_sampler_views(vctx
, shader_type
);
233 virgl_attach_res_uniform_buffers(vctx
, shader_type
);
234 virgl_attach_res_shader_buffers(vctx
, shader_type
);
235 virgl_attach_res_shader_images(vctx
, shader_type
);
237 virgl_attach_res_atomic_buffers(vctx
);
238 virgl_attach_res_vertex_buffers(vctx
);
239 virgl_attach_res_so_targets(vctx
);
242 static struct pipe_surface
*virgl_create_surface(struct pipe_context
*ctx
,
243 struct pipe_resource
*resource
,
244 const struct pipe_surface
*templ
)
246 struct virgl_context
*vctx
= virgl_context(ctx
);
247 struct virgl_surface
*surf
;
248 struct virgl_resource
*res
= virgl_resource(resource
);
251 surf
= CALLOC_STRUCT(virgl_surface
);
256 handle
= virgl_object_assign_handle();
257 pipe_reference_init(&surf
->base
.reference
, 1);
258 pipe_resource_reference(&surf
->base
.texture
, resource
);
259 surf
->base
.context
= ctx
;
260 surf
->base
.format
= templ
->format
;
261 if (resource
->target
!= PIPE_BUFFER
) {
262 surf
->base
.width
= u_minify(resource
->width0
, templ
->u
.tex
.level
);
263 surf
->base
.height
= u_minify(resource
->height0
, templ
->u
.tex
.level
);
264 surf
->base
.u
.tex
.level
= templ
->u
.tex
.level
;
265 surf
->base
.u
.tex
.first_layer
= templ
->u
.tex
.first_layer
;
266 surf
->base
.u
.tex
.last_layer
= templ
->u
.tex
.last_layer
;
268 surf
->base
.width
= templ
->u
.buf
.last_element
- templ
->u
.buf
.first_element
+ 1;
269 surf
->base
.height
= resource
->height0
;
270 surf
->base
.u
.buf
.first_element
= templ
->u
.buf
.first_element
;
271 surf
->base
.u
.buf
.last_element
= templ
->u
.buf
.last_element
;
273 virgl_encoder_create_surface(vctx
, handle
, res
, &surf
->base
);
274 surf
->handle
= handle
;
278 static void virgl_surface_destroy(struct pipe_context
*ctx
,
279 struct pipe_surface
*psurf
)
281 struct virgl_context
*vctx
= virgl_context(ctx
);
282 struct virgl_surface
*surf
= virgl_surface(psurf
);
284 pipe_resource_reference(&surf
->base
.texture
, NULL
);
285 virgl_encode_delete_object(vctx
, surf
->handle
, VIRGL_OBJECT_SURFACE
);
289 static void *virgl_create_blend_state(struct pipe_context
*ctx
,
290 const struct pipe_blend_state
*blend_state
)
292 struct virgl_context
*vctx
= virgl_context(ctx
);
294 handle
= virgl_object_assign_handle();
296 virgl_encode_blend_state(vctx
, handle
, blend_state
);
297 return (void *)(unsigned long)handle
;
301 static void virgl_bind_blend_state(struct pipe_context
*ctx
,
304 struct virgl_context
*vctx
= virgl_context(ctx
);
305 uint32_t handle
= (unsigned long)blend_state
;
306 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
309 static void virgl_delete_blend_state(struct pipe_context
*ctx
,
312 struct virgl_context
*vctx
= virgl_context(ctx
);
313 uint32_t handle
= (unsigned long)blend_state
;
314 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_BLEND
);
317 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context
*ctx
,
318 const struct pipe_depth_stencil_alpha_state
*blend_state
)
320 struct virgl_context
*vctx
= virgl_context(ctx
);
322 handle
= virgl_object_assign_handle();
324 virgl_encode_dsa_state(vctx
, handle
, blend_state
);
325 return (void *)(unsigned long)handle
;
328 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context
*ctx
,
331 struct virgl_context
*vctx
= virgl_context(ctx
);
332 uint32_t handle
= (unsigned long)blend_state
;
333 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
336 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context
*ctx
,
339 struct virgl_context
*vctx
= virgl_context(ctx
);
340 uint32_t handle
= (unsigned long)dsa_state
;
341 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_DSA
);
344 static void *virgl_create_rasterizer_state(struct pipe_context
*ctx
,
345 const struct pipe_rasterizer_state
*rs_state
)
347 struct virgl_context
*vctx
= virgl_context(ctx
);
349 handle
= virgl_object_assign_handle();
351 virgl_encode_rasterizer_state(vctx
, handle
, rs_state
);
352 return (void *)(unsigned long)handle
;
355 static void virgl_bind_rasterizer_state(struct pipe_context
*ctx
,
358 struct virgl_context
*vctx
= virgl_context(ctx
);
359 uint32_t handle
= (unsigned long)rs_state
;
361 virgl_encode_bind_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
364 static void virgl_delete_rasterizer_state(struct pipe_context
*ctx
,
367 struct virgl_context
*vctx
= virgl_context(ctx
);
368 uint32_t handle
= (unsigned long)rs_state
;
369 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_RASTERIZER
);
372 static void virgl_set_framebuffer_state(struct pipe_context
*ctx
,
373 const struct pipe_framebuffer_state
*state
)
375 struct virgl_context
*vctx
= virgl_context(ctx
);
377 vctx
->framebuffer
= *state
;
378 virgl_encoder_set_framebuffer_state(vctx
, state
);
379 virgl_attach_res_framebuffer(vctx
);
382 static void virgl_set_viewport_states(struct pipe_context
*ctx
,
384 unsigned num_viewports
,
385 const struct pipe_viewport_state
*state
)
387 struct virgl_context
*vctx
= virgl_context(ctx
);
388 virgl_encoder_set_viewport_states(vctx
, start_slot
, num_viewports
, state
);
391 static void *virgl_create_vertex_elements_state(struct pipe_context
*ctx
,
392 unsigned num_elements
,
393 const struct pipe_vertex_element
*elements
)
395 struct pipe_vertex_element new_elements
[PIPE_MAX_ATTRIBS
];
396 struct virgl_context
*vctx
= virgl_context(ctx
);
397 struct virgl_vertex_elements_state
*state
=
398 CALLOC_STRUCT(virgl_vertex_elements_state
);
400 for (int i
= 0; i
< num_elements
; ++i
) {
401 if (elements
[i
].instance_divisor
) {
402 /* Virglrenderer doesn't deal with instance_divisor correctly if
403 * there isn't a 1:1 relationship between elements and bindings.
404 * So let's make sure there is, by duplicating bindings.
406 for (int j
= 0; j
< num_elements
; ++j
) {
407 new_elements
[j
] = elements
[j
];
408 new_elements
[j
].vertex_buffer_index
= j
;
409 state
->binding_map
[j
] = elements
[j
].vertex_buffer_index
;
411 elements
= new_elements
;
412 state
->num_bindings
= num_elements
;
417 state
->handle
= virgl_object_assign_handle();
418 virgl_encoder_create_vertex_elements(vctx
, state
->handle
,
419 num_elements
, elements
);
423 static void virgl_delete_vertex_elements_state(struct pipe_context
*ctx
,
426 struct virgl_context
*vctx
= virgl_context(ctx
);
427 struct virgl_vertex_elements_state
*state
=
428 (struct virgl_vertex_elements_state
*)ve
;
429 virgl_encode_delete_object(vctx
, state
->handle
, VIRGL_OBJECT_VERTEX_ELEMENTS
);
433 static void virgl_bind_vertex_elements_state(struct pipe_context
*ctx
,
436 struct virgl_context
*vctx
= virgl_context(ctx
);
437 struct virgl_vertex_elements_state
*state
=
438 (struct virgl_vertex_elements_state
*)ve
;
439 vctx
->vertex_elements
= state
;
440 virgl_encode_bind_object(vctx
, state
? state
->handle
: 0,
441 VIRGL_OBJECT_VERTEX_ELEMENTS
);
442 vctx
->vertex_array_dirty
= TRUE
;
445 static void virgl_set_vertex_buffers(struct pipe_context
*ctx
,
447 unsigned num_buffers
,
448 const struct pipe_vertex_buffer
*buffers
)
450 struct virgl_context
*vctx
= virgl_context(ctx
);
452 util_set_vertex_buffers_count(vctx
->vertex_buffer
,
453 &vctx
->num_vertex_buffers
,
454 buffers
, start_slot
, num_buffers
);
456 vctx
->vertex_array_dirty
= TRUE
;
459 static void virgl_hw_set_vertex_buffers(struct virgl_context
*vctx
)
461 if (vctx
->vertex_array_dirty
) {
462 struct virgl_vertex_elements_state
*ve
= vctx
->vertex_elements
;
464 if (ve
->num_bindings
) {
465 struct pipe_vertex_buffer vertex_buffers
[PIPE_MAX_ATTRIBS
];
466 for (int i
= 0; i
< ve
->num_bindings
; ++i
)
467 vertex_buffers
[i
] = vctx
->vertex_buffer
[ve
->binding_map
[i
]];
469 virgl_encoder_set_vertex_buffers(vctx
, ve
->num_bindings
, vertex_buffers
);
471 virgl_encoder_set_vertex_buffers(vctx
, vctx
->num_vertex_buffers
, vctx
->vertex_buffer
);
473 virgl_attach_res_vertex_buffers(vctx
);
477 static void virgl_set_stencil_ref(struct pipe_context
*ctx
,
478 const struct pipe_stencil_ref
*ref
)
480 struct virgl_context
*vctx
= virgl_context(ctx
);
481 virgl_encoder_set_stencil_ref(vctx
, ref
);
484 static void virgl_set_blend_color(struct pipe_context
*ctx
,
485 const struct pipe_blend_color
*color
)
487 struct virgl_context
*vctx
= virgl_context(ctx
);
488 virgl_encoder_set_blend_color(vctx
, color
);
491 static void virgl_hw_set_index_buffer(struct virgl_context
*vctx
,
492 struct virgl_indexbuf
*ib
)
494 virgl_encoder_set_index_buffer(vctx
, ib
);
495 virgl_attach_res_index_buffer(vctx
, ib
);
498 static void virgl_set_constant_buffer(struct pipe_context
*ctx
,
499 enum pipe_shader_type shader
, uint index
,
500 const struct pipe_constant_buffer
*buf
)
502 struct virgl_context
*vctx
= virgl_context(ctx
);
505 if (!buf
->user_buffer
){
506 struct virgl_resource
*res
= virgl_resource(buf
->buffer
);
507 virgl_encoder_set_uniform_buffer(vctx
, shader
, index
, buf
->buffer_offset
,
508 buf
->buffer_size
, res
);
509 pipe_resource_reference(&vctx
->ubos
[shader
][index
], buf
->buffer
);
512 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
513 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, buf
->buffer_size
/ 4, buf
->user_buffer
);
515 virgl_encoder_write_constant_buffer(vctx
, shader
, index
, 0, NULL
);
516 pipe_resource_reference(&vctx
->ubos
[shader
][index
], NULL
);
520 void virgl_transfer_inline_write(struct pipe_context
*ctx
,
521 struct pipe_resource
*res
,
524 const struct pipe_box
*box
,
527 unsigned layer_stride
)
529 struct virgl_context
*vctx
= virgl_context(ctx
);
530 struct virgl_screen
*vs
= virgl_screen(ctx
->screen
);
531 struct virgl_resource
*grres
= virgl_resource(res
);
532 struct virgl_buffer
*vbuf
= virgl_buffer(res
);
534 grres
->clean
= FALSE
;
536 if (virgl_res_needs_flush_wait(vctx
, &vbuf
->base
, usage
)) {
537 ctx
->flush(ctx
, NULL
, 0);
539 vs
->vws
->resource_wait(vs
->vws
, vbuf
->base
.hw_res
);
542 virgl_encoder_inline_write(vctx
, grres
, level
, usage
,
543 box
, data
, stride
, layer_stride
);
546 static void *virgl_shader_encoder(struct pipe_context
*ctx
,
547 const struct pipe_shader_state
*shader
,
550 struct virgl_context
*vctx
= virgl_context(ctx
);
552 struct tgsi_token
*new_tokens
;
555 new_tokens
= virgl_tgsi_transform(vctx
, shader
->tokens
);
559 handle
= virgl_object_assign_handle();
560 /* encode VS state */
561 ret
= virgl_encode_shader_state(vctx
, handle
, type
,
562 &shader
->stream_output
, 0,
569 return (void *)(unsigned long)handle
;
572 static void *virgl_create_vs_state(struct pipe_context
*ctx
,
573 const struct pipe_shader_state
*shader
)
575 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_VERTEX
);
578 static void *virgl_create_tcs_state(struct pipe_context
*ctx
,
579 const struct pipe_shader_state
*shader
)
581 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_CTRL
);
584 static void *virgl_create_tes_state(struct pipe_context
*ctx
,
585 const struct pipe_shader_state
*shader
)
587 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_TESS_EVAL
);
590 static void *virgl_create_gs_state(struct pipe_context
*ctx
,
591 const struct pipe_shader_state
*shader
)
593 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_GEOMETRY
);
596 static void *virgl_create_fs_state(struct pipe_context
*ctx
,
597 const struct pipe_shader_state
*shader
)
599 return virgl_shader_encoder(ctx
, shader
, PIPE_SHADER_FRAGMENT
);
603 virgl_delete_fs_state(struct pipe_context
*ctx
,
606 uint32_t handle
= (unsigned long)fs
;
607 struct virgl_context
*vctx
= virgl_context(ctx
);
609 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
613 virgl_delete_gs_state(struct pipe_context
*ctx
,
616 uint32_t handle
= (unsigned long)gs
;
617 struct virgl_context
*vctx
= virgl_context(ctx
);
619 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
623 virgl_delete_vs_state(struct pipe_context
*ctx
,
626 uint32_t handle
= (unsigned long)vs
;
627 struct virgl_context
*vctx
= virgl_context(ctx
);
629 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
633 virgl_delete_tcs_state(struct pipe_context
*ctx
,
636 uint32_t handle
= (unsigned long)tcs
;
637 struct virgl_context
*vctx
= virgl_context(ctx
);
639 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
643 virgl_delete_tes_state(struct pipe_context
*ctx
,
646 uint32_t handle
= (unsigned long)tes
;
647 struct virgl_context
*vctx
= virgl_context(ctx
);
649 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
652 static void virgl_bind_vs_state(struct pipe_context
*ctx
,
655 uint32_t handle
= (unsigned long)vss
;
656 struct virgl_context
*vctx
= virgl_context(ctx
);
658 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_VERTEX
);
661 static void virgl_bind_tcs_state(struct pipe_context
*ctx
,
664 uint32_t handle
= (unsigned long)vss
;
665 struct virgl_context
*vctx
= virgl_context(ctx
);
667 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_CTRL
);
670 static void virgl_bind_tes_state(struct pipe_context
*ctx
,
673 uint32_t handle
= (unsigned long)vss
;
674 struct virgl_context
*vctx
= virgl_context(ctx
);
676 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_TESS_EVAL
);
679 static void virgl_bind_gs_state(struct pipe_context
*ctx
,
682 uint32_t handle
= (unsigned long)vss
;
683 struct virgl_context
*vctx
= virgl_context(ctx
);
685 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_GEOMETRY
);
689 static void virgl_bind_fs_state(struct pipe_context
*ctx
,
692 uint32_t handle
= (unsigned long)vss
;
693 struct virgl_context
*vctx
= virgl_context(ctx
);
695 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_FRAGMENT
);
698 static void virgl_clear(struct pipe_context
*ctx
,
700 const union pipe_color_union
*color
,
701 double depth
, unsigned stencil
)
703 struct virgl_context
*vctx
= virgl_context(ctx
);
705 virgl_encode_clear(vctx
, buffers
, color
, depth
, stencil
);
708 static void virgl_draw_vbo(struct pipe_context
*ctx
,
709 const struct pipe_draw_info
*dinfo
)
711 struct virgl_context
*vctx
= virgl_context(ctx
);
712 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
713 struct virgl_indexbuf ib
= {};
714 struct pipe_draw_info info
= *dinfo
;
716 if (!dinfo
->count_from_stream_output
&& !dinfo
->indirect
&&
717 !dinfo
->primitive_restart
&&
718 !u_trim_pipe_prim(dinfo
->mode
, (unsigned*)&dinfo
->count
))
721 if (!(rs
->caps
.caps
.v1
.prim_mask
& (1 << dinfo
->mode
))) {
722 util_primconvert_draw_vbo(vctx
->primconvert
, dinfo
);
725 if (info
.index_size
) {
726 pipe_resource_reference(&ib
.buffer
, info
.has_user_indices
? NULL
: info
.index
.resource
);
727 ib
.user_buffer
= info
.has_user_indices
? info
.index
.user
: NULL
;
728 ib
.index_size
= dinfo
->index_size
;
729 ib
.offset
= info
.start
* ib
.index_size
;
731 if (ib
.user_buffer
) {
732 u_upload_data(vctx
->uploader
, 0, info
.count
* ib
.index_size
, 256,
733 ib
.user_buffer
, &ib
.offset
, &ib
.buffer
);
734 ib
.user_buffer
= NULL
;
738 u_upload_unmap(vctx
->uploader
);
741 virgl_hw_set_vertex_buffers(vctx
);
743 virgl_hw_set_index_buffer(vctx
, &ib
);
745 virgl_encoder_draw_vbo(vctx
, &info
);
747 pipe_resource_reference(&ib
.buffer
, NULL
);
751 static void virgl_flush_eq(struct virgl_context
*ctx
, void *closure
,
752 struct pipe_fence_handle
**fence
)
754 struct virgl_screen
*rs
= virgl_screen(ctx
->base
.screen
);
755 int out_fence_fd
= -1;
757 /* send the buffer to the remote side for decoding */
758 ctx
->num_transfers
= ctx
->num_draws
= 0;
760 rs
->vws
->submit_cmd(rs
->vws
, ctx
->cbuf
, ctx
->cbuf
->in_fence_fd
,
761 ctx
->cbuf
->needs_out_fence_fd
? &out_fence_fd
: NULL
);
764 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, out_fence_fd
);
766 virgl_encoder_set_sub_ctx(ctx
, ctx
->hw_sub_ctx_id
);
768 /* add back current framebuffer resources to reference list? */
769 virgl_reemit_res(ctx
);
772 static void virgl_flush_from_st(struct pipe_context
*ctx
,
773 struct pipe_fence_handle
**fence
,
774 enum pipe_flush_flags flags
)
776 struct virgl_context
*vctx
= virgl_context(ctx
);
777 struct virgl_buffer
*buf
, *tmp
;
779 if (flags
& PIPE_FLUSH_FENCE_FD
)
780 vctx
->cbuf
->needs_out_fence_fd
= true;
782 LIST_FOR_EACH_ENTRY_SAFE(buf
, tmp
, &vctx
->to_flush_bufs
, flush_list
) {
783 struct pipe_resource
*res
= &buf
->base
.u
.b
;
784 virgl_buffer_flush(vctx
, buf
);
785 list_del(&buf
->flush_list
);
786 buf
->on_list
= FALSE
;
787 pipe_resource_reference(&res
, NULL
);
790 virgl_flush_eq(vctx
, vctx
, fence
);
792 if (vctx
->cbuf
->in_fence_fd
!= -1) {
793 close(vctx
->cbuf
->in_fence_fd
);
794 vctx
->cbuf
->in_fence_fd
= -1;
796 vctx
->cbuf
->needs_out_fence_fd
= false;
799 static struct pipe_sampler_view
*virgl_create_sampler_view(struct pipe_context
*ctx
,
800 struct pipe_resource
*texture
,
801 const struct pipe_sampler_view
*state
)
803 struct virgl_context
*vctx
= virgl_context(ctx
);
804 struct virgl_sampler_view
*grview
;
806 struct virgl_resource
*res
;
811 grview
= CALLOC_STRUCT(virgl_sampler_view
);
815 res
= virgl_resource(texture
);
816 handle
= virgl_object_assign_handle();
817 virgl_encode_sampler_view(vctx
, handle
, res
, state
);
819 grview
->base
= *state
;
820 grview
->base
.reference
.count
= 1;
822 grview
->base
.texture
= NULL
;
823 grview
->base
.context
= ctx
;
824 pipe_resource_reference(&grview
->base
.texture
, texture
);
825 grview
->handle
= handle
;
826 return &grview
->base
;
829 static void virgl_set_sampler_views(struct pipe_context
*ctx
,
830 enum pipe_shader_type shader_type
,
833 struct pipe_sampler_view
**views
)
835 struct virgl_context
*vctx
= virgl_context(ctx
);
837 uint32_t disable_mask
= ~((1ull << num_views
) - 1);
838 struct virgl_textures_info
*tinfo
= &vctx
->samplers
[shader_type
];
839 uint32_t new_mask
= 0;
840 uint32_t remaining_mask
;
842 remaining_mask
= tinfo
->enabled_mask
& disable_mask
;
844 while (remaining_mask
) {
845 i
= u_bit_scan(&remaining_mask
);
846 assert(tinfo
->views
[i
]);
848 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
851 for (i
= 0; i
< num_views
; i
++) {
852 struct virgl_sampler_view
*grview
= virgl_sampler_view(views
[i
]);
854 if (views
[i
] == (struct pipe_sampler_view
*)tinfo
->views
[i
])
859 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], views
[i
]);
861 pipe_sampler_view_reference((struct pipe_sampler_view
**)&tinfo
->views
[i
], NULL
);
862 disable_mask
|= 1 << i
;
866 tinfo
->enabled_mask
&= ~disable_mask
;
867 tinfo
->enabled_mask
|= new_mask
;
868 virgl_encode_set_sampler_views(vctx
, shader_type
, start_slot
, num_views
, tinfo
->views
);
869 virgl_attach_res_sampler_views(vctx
, shader_type
);
873 virgl_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
875 struct virgl_context
*vctx
= virgl_context(ctx
);
876 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
878 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_TEXTURE_BARRIER
))
880 virgl_encode_texture_barrier(vctx
, flags
);
883 static void virgl_destroy_sampler_view(struct pipe_context
*ctx
,
884 struct pipe_sampler_view
*view
)
886 struct virgl_context
*vctx
= virgl_context(ctx
);
887 struct virgl_sampler_view
*grview
= virgl_sampler_view(view
);
889 virgl_encode_delete_object(vctx
, grview
->handle
, VIRGL_OBJECT_SAMPLER_VIEW
);
890 pipe_resource_reference(&view
->texture
, NULL
);
894 static void *virgl_create_sampler_state(struct pipe_context
*ctx
,
895 const struct pipe_sampler_state
*state
)
897 struct virgl_context
*vctx
= virgl_context(ctx
);
900 handle
= virgl_object_assign_handle();
902 virgl_encode_sampler_state(vctx
, handle
, state
);
903 return (void *)(unsigned long)handle
;
906 static void virgl_delete_sampler_state(struct pipe_context
*ctx
,
909 struct virgl_context
*vctx
= virgl_context(ctx
);
910 uint32_t handle
= (unsigned long)ss
;
912 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SAMPLER_STATE
);
915 static void virgl_bind_sampler_states(struct pipe_context
*ctx
,
916 enum pipe_shader_type shader
,
918 unsigned num_samplers
,
921 struct virgl_context
*vctx
= virgl_context(ctx
);
922 uint32_t handles
[32];
924 for (i
= 0; i
< num_samplers
; i
++) {
925 handles
[i
] = (unsigned long)(samplers
[i
]);
927 virgl_encode_bind_sampler_states(vctx
, shader
, start_slot
, num_samplers
, handles
);
930 static void virgl_set_polygon_stipple(struct pipe_context
*ctx
,
931 const struct pipe_poly_stipple
*ps
)
933 struct virgl_context
*vctx
= virgl_context(ctx
);
934 virgl_encoder_set_polygon_stipple(vctx
, ps
);
937 static void virgl_set_scissor_states(struct pipe_context
*ctx
,
939 unsigned num_scissor
,
940 const struct pipe_scissor_state
*ss
)
942 struct virgl_context
*vctx
= virgl_context(ctx
);
943 virgl_encoder_set_scissor_state(vctx
, start_slot
, num_scissor
, ss
);
946 static void virgl_set_sample_mask(struct pipe_context
*ctx
,
947 unsigned sample_mask
)
949 struct virgl_context
*vctx
= virgl_context(ctx
);
950 virgl_encoder_set_sample_mask(vctx
, sample_mask
);
953 static void virgl_set_min_samples(struct pipe_context
*ctx
,
954 unsigned min_samples
)
956 struct virgl_context
*vctx
= virgl_context(ctx
);
957 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
959 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_SET_MIN_SAMPLES
))
961 virgl_encoder_set_min_samples(vctx
, min_samples
);
964 static void virgl_set_clip_state(struct pipe_context
*ctx
,
965 const struct pipe_clip_state
*clip
)
967 struct virgl_context
*vctx
= virgl_context(ctx
);
968 virgl_encoder_set_clip_state(vctx
, clip
);
971 static void virgl_set_tess_state(struct pipe_context
*ctx
,
972 const float default_outer_level
[4],
973 const float default_inner_level
[2])
975 struct virgl_context
*vctx
= virgl_context(ctx
);
976 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
978 if (!rs
->caps
.caps
.v1
.bset
.has_tessellation_shaders
)
980 virgl_encode_set_tess_state(vctx
, default_outer_level
, default_inner_level
);
983 static void virgl_resource_copy_region(struct pipe_context
*ctx
,
984 struct pipe_resource
*dst
,
986 unsigned dstx
, unsigned dsty
, unsigned dstz
,
987 struct pipe_resource
*src
,
989 const struct pipe_box
*src_box
)
991 struct virgl_context
*vctx
= virgl_context(ctx
);
992 struct virgl_resource
*dres
= virgl_resource(dst
);
993 struct virgl_resource
*sres
= virgl_resource(src
);
996 virgl_encode_resource_copy_region(vctx
, dres
,
997 dst_level
, dstx
, dsty
, dstz
,
1003 virgl_flush_resource(struct pipe_context
*pipe
,
1004 struct pipe_resource
*resource
)
1008 static void virgl_blit(struct pipe_context
*ctx
,
1009 const struct pipe_blit_info
*blit
)
1011 struct virgl_context
*vctx
= virgl_context(ctx
);
1012 struct virgl_resource
*dres
= virgl_resource(blit
->dst
.resource
);
1013 struct virgl_resource
*sres
= virgl_resource(blit
->src
.resource
);
1015 dres
->clean
= FALSE
;
1016 virgl_encode_blit(vctx
, dres
, sres
,
1020 static void virgl_set_hw_atomic_buffers(struct pipe_context
*ctx
,
1021 unsigned start_slot
,
1023 const struct pipe_shader_buffer
*buffers
)
1025 struct virgl_context
*vctx
= virgl_context(ctx
);
1027 for (unsigned i
= 0; i
< count
; i
++) {
1028 unsigned idx
= start_slot
+ i
;
1031 if (buffers
[i
].buffer
) {
1032 pipe_resource_reference(&vctx
->atomic_buffers
[idx
],
1037 pipe_resource_reference(&vctx
->atomic_buffers
[idx
], NULL
);
1039 virgl_encode_set_hw_atomic_buffers(vctx
, start_slot
, count
, buffers
);
1042 static void virgl_set_shader_buffers(struct pipe_context
*ctx
,
1043 enum pipe_shader_type shader
,
1044 unsigned start_slot
, unsigned count
,
1045 const struct pipe_shader_buffer
*buffers
)
1047 struct virgl_context
*vctx
= virgl_context(ctx
);
1048 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1050 for (unsigned i
= 0; i
< count
; i
++) {
1051 unsigned idx
= start_slot
+ i
;
1054 if (buffers
[i
].buffer
) {
1055 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], buffers
[i
].buffer
);
1059 pipe_resource_reference(&vctx
->ssbos
[shader
][idx
], NULL
);
1062 uint32_t max_shader_buffer
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1063 rs
->caps
.caps
.v2
.max_shader_buffer_frag_compute
:
1064 rs
->caps
.caps
.v2
.max_shader_buffer_other_stages
;
1065 if (!max_shader_buffer
)
1067 virgl_encode_set_shader_buffers(vctx
, shader
, start_slot
, count
, buffers
);
1070 static void virgl_create_fence_fd(struct pipe_context
*ctx
,
1071 struct pipe_fence_handle
**fence
,
1073 enum pipe_fd_type type
)
1075 assert(type
== PIPE_FD_TYPE_NATIVE_SYNC
);
1076 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1078 if (rs
->vws
->cs_create_fence
)
1079 *fence
= rs
->vws
->cs_create_fence(rs
->vws
, fd
);
1082 static void virgl_fence_server_sync(struct pipe_context
*ctx
,
1083 struct pipe_fence_handle
*fence
)
1085 struct virgl_context
*vctx
= virgl_context(ctx
);
1086 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1088 if (rs
->vws
->fence_server_sync
)
1089 rs
->vws
->fence_server_sync(rs
->vws
, vctx
->cbuf
, fence
);
1092 static void virgl_set_shader_images(struct pipe_context
*ctx
,
1093 enum pipe_shader_type shader
,
1094 unsigned start_slot
, unsigned count
,
1095 const struct pipe_image_view
*images
)
1097 struct virgl_context
*vctx
= virgl_context(ctx
);
1098 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1100 for (unsigned i
= 0; i
< count
; i
++) {
1101 unsigned idx
= start_slot
+ i
;
1104 if (images
[i
].resource
) {
1105 pipe_resource_reference(&vctx
->images
[shader
][idx
], images
[i
].resource
);
1109 pipe_resource_reference(&vctx
->images
[shader
][idx
], NULL
);
1112 uint32_t max_shader_images
= (shader
== PIPE_SHADER_FRAGMENT
|| shader
== PIPE_SHADER_COMPUTE
) ?
1113 rs
->caps
.caps
.v2
.max_shader_image_frag_compute
:
1114 rs
->caps
.caps
.v2
.max_shader_image_other_stages
;
1115 if (!max_shader_images
)
1117 virgl_encode_set_shader_images(vctx
, shader
, start_slot
, count
, images
);
1120 static void virgl_memory_barrier(struct pipe_context
*ctx
,
1123 struct virgl_context
*vctx
= virgl_context(ctx
);
1124 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1126 if (!(rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_MEMORY_BARRIER
))
1128 virgl_encode_memory_barrier(vctx
, flags
);
1131 static void *virgl_create_compute_state(struct pipe_context
*ctx
,
1132 const struct pipe_compute_state
*state
)
1134 struct virgl_context
*vctx
= virgl_context(ctx
);
1136 const struct tgsi_token
*new_tokens
= state
->prog
;
1137 struct pipe_stream_output_info so_info
= {};
1140 handle
= virgl_object_assign_handle();
1141 ret
= virgl_encode_shader_state(vctx
, handle
, PIPE_SHADER_COMPUTE
,
1143 state
->req_local_mem
,
1149 return (void *)(unsigned long)handle
;
1152 static void virgl_bind_compute_state(struct pipe_context
*ctx
, void *state
)
1154 uint32_t handle
= (unsigned long)state
;
1155 struct virgl_context
*vctx
= virgl_context(ctx
);
1157 virgl_encode_bind_shader(vctx
, handle
, PIPE_SHADER_COMPUTE
);
1160 static void virgl_delete_compute_state(struct pipe_context
*ctx
, void *state
)
1162 uint32_t handle
= (unsigned long)state
;
1163 struct virgl_context
*vctx
= virgl_context(ctx
);
1165 virgl_encode_delete_object(vctx
, handle
, VIRGL_OBJECT_SHADER
);
1168 static void virgl_launch_grid(struct pipe_context
*ctx
,
1169 const struct pipe_grid_info
*info
)
1171 struct virgl_context
*vctx
= virgl_context(ctx
);
1172 virgl_encode_launch_grid(vctx
, info
);
1176 virgl_context_destroy( struct pipe_context
*ctx
)
1178 struct virgl_context
*vctx
= virgl_context(ctx
);
1179 struct virgl_screen
*rs
= virgl_screen(ctx
->screen
);
1181 vctx
->framebuffer
.zsbuf
= NULL
;
1182 vctx
->framebuffer
.nr_cbufs
= 0;
1183 virgl_encoder_destroy_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1184 virgl_flush_eq(vctx
, vctx
, NULL
);
1186 rs
->vws
->cmd_buf_destroy(vctx
->cbuf
);
1188 u_upload_destroy(vctx
->uploader
);
1189 util_primconvert_destroy(vctx
->primconvert
);
1191 slab_destroy_child(&vctx
->texture_transfer_pool
);
1195 static void virgl_get_sample_position(struct pipe_context
*ctx
,
1196 unsigned sample_count
,
1200 struct virgl_context
*vctx
= virgl_context(ctx
);
1201 struct virgl_screen
*vs
= virgl_screen(vctx
->base
.screen
);
1203 if (sample_count
> vs
->caps
.caps
.v1
.max_samples
) {
1204 debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1205 sample_count
, vs
->caps
.caps
.v1
.max_samples
);
1209 /* The following is basically copied from dri/i965gen6_get_sample_position
1210 * The only addition is that we hold the msaa positions for all sample
1211 * counts in a flat array. */
1213 if (sample_count
== 1) {
1214 out_value
[0] = out_value
[1] = 0.5f
;
1216 } else if (sample_count
== 2) {
1217 bits
= vs
->caps
.caps
.v2
.sample_locations
[0] >> (8 * index
);
1218 } else if (sample_count
<= 4) {
1219 bits
= vs
->caps
.caps
.v2
.sample_locations
[1] >> (8 * index
);
1220 } else if (sample_count
<= 8) {
1221 bits
= vs
->caps
.caps
.v2
.sample_locations
[2 + (index
>> 2)] >> (8 * (index
& 3));
1222 } else if (sample_count
<= 16) {
1223 bits
= vs
->caps
.caps
.v2
.sample_locations
[4 + (index
>> 2)] >> (8 * (index
& 3));
1225 out_value
[0] = ((bits
>> 4) & 0xf) / 16.0f
;
1226 out_value
[1] = (bits
& 0xf) / 16.0f
;
1228 if (virgl_debug
& VIRGL_DEBUG_VERBOSE
)
1229 debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1230 index
, sample_count
, out_value
[0], out_value
[1]);
1233 struct pipe_context
*virgl_context_create(struct pipe_screen
*pscreen
,
1237 struct virgl_context
*vctx
;
1238 struct virgl_screen
*rs
= virgl_screen(pscreen
);
1239 vctx
= CALLOC_STRUCT(virgl_context
);
1240 const char *host_debug_flagstring
;
1242 vctx
->cbuf
= rs
->vws
->cmd_buf_create(rs
->vws
);
1248 vctx
->base
.destroy
= virgl_context_destroy
;
1249 vctx
->base
.create_surface
= virgl_create_surface
;
1250 vctx
->base
.surface_destroy
= virgl_surface_destroy
;
1251 vctx
->base
.set_framebuffer_state
= virgl_set_framebuffer_state
;
1252 vctx
->base
.create_blend_state
= virgl_create_blend_state
;
1253 vctx
->base
.bind_blend_state
= virgl_bind_blend_state
;
1254 vctx
->base
.delete_blend_state
= virgl_delete_blend_state
;
1255 vctx
->base
.create_depth_stencil_alpha_state
= virgl_create_depth_stencil_alpha_state
;
1256 vctx
->base
.bind_depth_stencil_alpha_state
= virgl_bind_depth_stencil_alpha_state
;
1257 vctx
->base
.delete_depth_stencil_alpha_state
= virgl_delete_depth_stencil_alpha_state
;
1258 vctx
->base
.create_rasterizer_state
= virgl_create_rasterizer_state
;
1259 vctx
->base
.bind_rasterizer_state
= virgl_bind_rasterizer_state
;
1260 vctx
->base
.delete_rasterizer_state
= virgl_delete_rasterizer_state
;
1262 vctx
->base
.set_viewport_states
= virgl_set_viewport_states
;
1263 vctx
->base
.create_vertex_elements_state
= virgl_create_vertex_elements_state
;
1264 vctx
->base
.bind_vertex_elements_state
= virgl_bind_vertex_elements_state
;
1265 vctx
->base
.delete_vertex_elements_state
= virgl_delete_vertex_elements_state
;
1266 vctx
->base
.set_vertex_buffers
= virgl_set_vertex_buffers
;
1267 vctx
->base
.set_constant_buffer
= virgl_set_constant_buffer
;
1269 vctx
->base
.set_tess_state
= virgl_set_tess_state
;
1270 vctx
->base
.create_vs_state
= virgl_create_vs_state
;
1271 vctx
->base
.create_tcs_state
= virgl_create_tcs_state
;
1272 vctx
->base
.create_tes_state
= virgl_create_tes_state
;
1273 vctx
->base
.create_gs_state
= virgl_create_gs_state
;
1274 vctx
->base
.create_fs_state
= virgl_create_fs_state
;
1276 vctx
->base
.bind_vs_state
= virgl_bind_vs_state
;
1277 vctx
->base
.bind_tcs_state
= virgl_bind_tcs_state
;
1278 vctx
->base
.bind_tes_state
= virgl_bind_tes_state
;
1279 vctx
->base
.bind_gs_state
= virgl_bind_gs_state
;
1280 vctx
->base
.bind_fs_state
= virgl_bind_fs_state
;
1282 vctx
->base
.delete_vs_state
= virgl_delete_vs_state
;
1283 vctx
->base
.delete_tcs_state
= virgl_delete_tcs_state
;
1284 vctx
->base
.delete_tes_state
= virgl_delete_tes_state
;
1285 vctx
->base
.delete_gs_state
= virgl_delete_gs_state
;
1286 vctx
->base
.delete_fs_state
= virgl_delete_fs_state
;
1288 vctx
->base
.create_compute_state
= virgl_create_compute_state
;
1289 vctx
->base
.bind_compute_state
= virgl_bind_compute_state
;
1290 vctx
->base
.delete_compute_state
= virgl_delete_compute_state
;
1291 vctx
->base
.launch_grid
= virgl_launch_grid
;
1293 vctx
->base
.clear
= virgl_clear
;
1294 vctx
->base
.draw_vbo
= virgl_draw_vbo
;
1295 vctx
->base
.flush
= virgl_flush_from_st
;
1296 vctx
->base
.screen
= pscreen
;
1297 vctx
->base
.create_sampler_view
= virgl_create_sampler_view
;
1298 vctx
->base
.sampler_view_destroy
= virgl_destroy_sampler_view
;
1299 vctx
->base
.set_sampler_views
= virgl_set_sampler_views
;
1300 vctx
->base
.texture_barrier
= virgl_texture_barrier
;
1302 vctx
->base
.create_sampler_state
= virgl_create_sampler_state
;
1303 vctx
->base
.delete_sampler_state
= virgl_delete_sampler_state
;
1304 vctx
->base
.bind_sampler_states
= virgl_bind_sampler_states
;
1306 vctx
->base
.set_polygon_stipple
= virgl_set_polygon_stipple
;
1307 vctx
->base
.set_scissor_states
= virgl_set_scissor_states
;
1308 vctx
->base
.set_sample_mask
= virgl_set_sample_mask
;
1309 vctx
->base
.set_min_samples
= virgl_set_min_samples
;
1310 vctx
->base
.set_stencil_ref
= virgl_set_stencil_ref
;
1311 vctx
->base
.set_clip_state
= virgl_set_clip_state
;
1313 vctx
->base
.set_blend_color
= virgl_set_blend_color
;
1315 vctx
->base
.get_sample_position
= virgl_get_sample_position
;
1317 vctx
->base
.resource_copy_region
= virgl_resource_copy_region
;
1318 vctx
->base
.flush_resource
= virgl_flush_resource
;
1319 vctx
->base
.blit
= virgl_blit
;
1320 vctx
->base
.create_fence_fd
= virgl_create_fence_fd
;
1321 vctx
->base
.fence_server_sync
= virgl_fence_server_sync
;
1323 vctx
->base
.set_shader_buffers
= virgl_set_shader_buffers
;
1324 vctx
->base
.set_hw_atomic_buffers
= virgl_set_hw_atomic_buffers
;
1325 vctx
->base
.set_shader_images
= virgl_set_shader_images
;
1326 vctx
->base
.memory_barrier
= virgl_memory_barrier
;
1328 virgl_init_context_resource_functions(&vctx
->base
);
1329 virgl_init_query_functions(vctx
);
1330 virgl_init_so_functions(vctx
);
1332 list_inithead(&vctx
->to_flush_bufs
);
1333 slab_create_child(&vctx
->texture_transfer_pool
, &rs
->texture_transfer_pool
);
1335 vctx
->primconvert
= util_primconvert_create(&vctx
->base
, rs
->caps
.caps
.v1
.prim_mask
);
1336 vctx
->uploader
= u_upload_create(&vctx
->base
, 1024 * 1024,
1337 PIPE_BIND_INDEX_BUFFER
, PIPE_USAGE_STREAM
, 0);
1338 if (!vctx
->uploader
)
1340 vctx
->base
.stream_uploader
= vctx
->uploader
;
1341 vctx
->base
.const_uploader
= vctx
->uploader
;
1343 vctx
->hw_sub_ctx_id
= rs
->sub_ctx_id
++;
1344 virgl_encoder_create_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1346 virgl_encoder_set_sub_ctx(vctx
, vctx
->hw_sub_ctx_id
);
1348 if (rs
->caps
.caps
.v2
.capability_bits
& VIRGL_CAP_GUEST_MAY_INIT_LOG
) {
1349 host_debug_flagstring
= getenv("VIRGL_HOST_DEBUG");
1350 if (host_debug_flagstring
)
1351 virgl_encode_host_debug_flagstring(vctx
, host_debug_flagstring
);