src/gallium/drivers/virgl/virgl_context.c

   1 /*
   2  * Copyright 2014, 2015 Red Hat.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "pipe/p_shader_tokens.h"
  25
  26 #include "pipe/p_context.h"
  27 #include "pipe/p_defines.h"
  28 #include "pipe/p_screen.h"
  29 #include "pipe/p_state.h"
  30 #include "util/u_inlines.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_format.h"
  33 #include "util/u_prim.h"
  34 #include "util/u_transfer.h"
  35 #include "util/u_helpers.h"
  36 #include "util/slab.h"
  37 #include "util/u_upload_mgr.h"
  38 #include "util/u_blitter.h"
  39 #include "tgsi/tgsi_text.h"
  40 #include "indices/u_primconvert.h"
  41
  42 #include "pipebuffer/pb_buffer.h"
  43
  44 #include "virgl_encode.h"
  45 #include "virgl_context.h"
  46 #include "virgl_protocol.h"
  47 #include "virgl_resource.h"
  48 #include "virgl_screen.h"
  49
  50 static uint32_t next_handle;
  51 uint32_t virgl_object_assign_handle(void)
  52 {
  53    return ++next_handle;
  54 }
  55
  56 static void virgl_buffer_flush(struct virgl_context *vctx,
  57                               struct virgl_buffer *vbuf)
  58 {
  59    struct virgl_screen *rs = virgl_screen(vctx->base.screen);
  60    struct pipe_box box;
  61
  62    assert(vbuf->on_list);
  63
  64    box.height = 1;
  65    box.depth = 1;
  66    box.y = 0;
  67    box.z = 0;
  68
  69    box.x = vbuf->valid_buffer_range.start;
  70    box.width = MIN2(vbuf->valid_buffer_range.end - vbuf->valid_buffer_range.start, vbuf->base.u.b.width0);
  71
  72    vctx->num_transfers++;
  73    rs->vws->transfer_put(rs->vws, vbuf->base.hw_res,
  74                          &box, 0, 0, box.x, 0);
  75
  76    util_range_set_empty(&vbuf->valid_buffer_range);
  77 }
  78
  79 static void virgl_attach_res_framebuffer(struct virgl_context *vctx)
  80 {
  81    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
  82    struct pipe_surface *surf;
  83    struct virgl_resource *res;
  84    unsigned i;
  85
  86    surf = vctx->framebuffer.zsbuf;
  87    if (surf) {
  88       res = virgl_resource(surf->texture);
  89       if (res)
  90          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
  91    }
  92    for (i = 0; i < vctx->framebuffer.nr_cbufs; i++) {
  93       surf = vctx->framebuffer.cbufs[i];
  94       if (surf) {
  95          res = virgl_resource(surf->texture);
  96          if (res)
  97             vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
  98       }
  99    }
 100 }
 101
 102 static void virgl_attach_res_sampler_views(struct virgl_context *vctx,
 103                                            enum pipe_shader_type shader_type)
 104 {
 105    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 106    struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
 107    struct virgl_resource *res;
 108    uint32_t remaining_mask = tinfo->enabled_mask;
 109    unsigned i;
 110    while (remaining_mask) {
 111       i = u_bit_scan(&remaining_mask);
 112       assert(tinfo->views[i]);
 113
 114       res = virgl_resource(tinfo->views[i]->base.texture);
 115       if (res)
 116          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 117    }
 118 }
 119
 120 static void virgl_attach_res_vertex_buffers(struct virgl_context *vctx)
 121 {
 122    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 123    struct virgl_resource *res;
 124    unsigned i;
 125
 126    for (i = 0; i < vctx->num_vertex_buffers; i++) {
 127       res = virgl_resource(vctx->vertex_buffer[i].buffer.resource);
 128       if (res)
 129          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 130    }
 131 }
 132
 133 static void virgl_attach_res_index_buffer(struct virgl_context *vctx,
 134                                           struct virgl_indexbuf *ib)
 135 {
 136    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 137    struct virgl_resource *res;
 138
 139    res = virgl_resource(ib->buffer);
 140    if (res)
 141       vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 142 }
 143
 144 static void virgl_attach_res_so_targets(struct virgl_context *vctx)
 145 {
 146    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 147    struct virgl_resource *res;
 148    unsigned i;
 149
 150    for (i = 0; i < vctx->num_so_targets; i++) {
 151       res = virgl_resource(vctx->so_targets[i].base.buffer);
 152       if (res)
 153          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 154    }
 155 }
 156
 157 static void virgl_attach_res_uniform_buffers(struct virgl_context *vctx,
 158                                              enum pipe_shader_type shader_type)
 159 {
 160    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 161    struct virgl_resource *res;
 162    unsigned i;
 163    for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; i++) {
 164       res = virgl_resource(vctx->ubos[shader_type][i]);
 165       if (res) {
 166          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 167       }
 168    }
 169 }
 170
 171 static void virgl_attach_res_shader_buffers(struct virgl_context *vctx,
 172                                             enum pipe_shader_type shader_type)
 173 {
 174    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 175    struct virgl_resource *res;
 176    unsigned i;
 177    for (i = 0; i < PIPE_MAX_SHADER_BUFFERS; i++) {
 178       res = virgl_resource(vctx->ssbos[shader_type][i]);
 179       if (res) {
 180          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 181       }
 182    }
 183 }
 184
 185 static void virgl_attach_res_shader_images(struct virgl_context *vctx,
 186                                            enum pipe_shader_type shader_type)
 187 {
 188    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 189    struct virgl_resource *res;
 190    unsigned i;
 191    for (i = 0; i < PIPE_MAX_SHADER_IMAGES; i++) {
 192       res = virgl_resource(vctx->images[shader_type][i]);
 193       if (res) {
 194          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 195       }
 196    }
 197 }
 198
 199 static void virgl_attach_res_atomic_buffers(struct virgl_context *vctx)
 200 {
 201    struct virgl_winsys *vws = virgl_screen(vctx->base.screen)->vws;
 202    struct virgl_resource *res;
 203    unsigned i;
 204    for (i = 0; i < PIPE_MAX_HW_ATOMIC_BUFFERS; i++) {
 205       res = virgl_resource(vctx->atomic_buffers[i]);
 206       if (res) {
 207          vws->emit_res(vws, vctx->cbuf, res->hw_res, FALSE);
 208       }
 209    }
 210 }
 211
 212 /*
 213  * after flushing, the hw context still has a bunch of
 214  * resources bound, so we need to rebind those here.
 215  */
 216 static void virgl_reemit_res(struct virgl_context *vctx)
 217 {
 218    enum pipe_shader_type shader_type;
 219
 220    /* reattach any flushed resources */
 221    /* framebuffer, sampler views, vertex/index/uniform/stream buffers */
 222    virgl_attach_res_framebuffer(vctx);
 223
 224    for (shader_type = 0; shader_type < PIPE_SHADER_TYPES; shader_type++) {
 225       virgl_attach_res_sampler_views(vctx, shader_type);
 226       virgl_attach_res_uniform_buffers(vctx, shader_type);
 227       virgl_attach_res_shader_buffers(vctx, shader_type);
 228       virgl_attach_res_shader_images(vctx, shader_type);
 229    }
 230    virgl_attach_res_atomic_buffers(vctx);
 231    virgl_attach_res_vertex_buffers(vctx);
 232    virgl_attach_res_so_targets(vctx);
 233 }
 234
 235 static struct pipe_surface *virgl_create_surface(struct pipe_context *ctx,
 236                                                 struct pipe_resource *resource,
 237                                                 const struct pipe_surface *templ)
 238 {
 239    struct virgl_context *vctx = virgl_context(ctx);
 240    struct virgl_surface *surf;
 241    struct virgl_resource *res = virgl_resource(resource);
 242    uint32_t handle;
 243
 244    surf = CALLOC_STRUCT(virgl_surface);
 245    if (!surf)
 246       return NULL;
 247
 248    res->clean = FALSE;
 249    handle = virgl_object_assign_handle();
 250    pipe_reference_init(&surf->base.reference, 1);
 251    pipe_resource_reference(&surf->base.texture, resource);
 252    surf->base.context = ctx;
 253    surf->base.format = templ->format;
 254    if (resource->target != PIPE_BUFFER) {
 255       surf->base.width = u_minify(resource->width0, templ->u.tex.level);
 256       surf->base.height = u_minify(resource->height0, templ->u.tex.level);
 257       surf->base.u.tex.level = templ->u.tex.level;
 258       surf->base.u.tex.first_layer = templ->u.tex.first_layer;
 259       surf->base.u.tex.last_layer = templ->u.tex.last_layer;
 260    } else {
 261       surf->base.width = templ->u.buf.last_element - templ->u.buf.first_element + 1;
 262       surf->base.height = resource->height0;
 263       surf->base.u.buf.first_element = templ->u.buf.first_element;
 264       surf->base.u.buf.last_element = templ->u.buf.last_element;
 265    }
 266    virgl_encoder_create_surface(vctx, handle, res, &surf->base);
 267    surf->handle = handle;
 268    return &surf->base;
 269 }
 270
 271 static void virgl_surface_destroy(struct pipe_context *ctx,
 272                                  struct pipe_surface *psurf)
 273 {
 274    struct virgl_context *vctx = virgl_context(ctx);
 275    struct virgl_surface *surf = virgl_surface(psurf);
 276
 277    pipe_resource_reference(&surf->base.texture, NULL);
 278    virgl_encode_delete_object(vctx, surf->handle, VIRGL_OBJECT_SURFACE);
 279    FREE(surf);
 280 }
 281
 282 static void *virgl_create_blend_state(struct pipe_context *ctx,
 283                                               const struct pipe_blend_state *blend_state)
 284 {
 285    struct virgl_context *vctx = virgl_context(ctx);
 286    uint32_t handle;
 287    handle = virgl_object_assign_handle();
 288
 289    virgl_encode_blend_state(vctx, handle, blend_state);
 290    return (void *)(unsigned long)handle;
 291
 292 }
 293
 294 static void virgl_bind_blend_state(struct pipe_context *ctx,
 295                                            void *blend_state)
 296 {
 297    struct virgl_context *vctx = virgl_context(ctx);
 298    uint32_t handle = (unsigned long)blend_state;
 299    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_BLEND);
 300 }
 301
 302 static void virgl_delete_blend_state(struct pipe_context *ctx,
 303                                      void *blend_state)
 304 {
 305    struct virgl_context *vctx = virgl_context(ctx);
 306    uint32_t handle = (unsigned long)blend_state;
 307    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_BLEND);
 308 }
 309
 310 static void *virgl_create_depth_stencil_alpha_state(struct pipe_context *ctx,
 311                                                    const struct pipe_depth_stencil_alpha_state *blend_state)
 312 {
 313    struct virgl_context *vctx = virgl_context(ctx);
 314    uint32_t handle;
 315    handle = virgl_object_assign_handle();
 316
 317    virgl_encode_dsa_state(vctx, handle, blend_state);
 318    return (void *)(unsigned long)handle;
 319 }
 320
 321 static void virgl_bind_depth_stencil_alpha_state(struct pipe_context *ctx,
 322                                                 void *blend_state)
 323 {
 324    struct virgl_context *vctx = virgl_context(ctx);
 325    uint32_t handle = (unsigned long)blend_state;
 326    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_DSA);
 327 }
 328
 329 static void virgl_delete_depth_stencil_alpha_state(struct pipe_context *ctx,
 330                                                   void *dsa_state)
 331 {
 332    struct virgl_context *vctx = virgl_context(ctx);
 333    uint32_t handle = (unsigned long)dsa_state;
 334    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_DSA);
 335 }
 336
 337 static void *virgl_create_rasterizer_state(struct pipe_context *ctx,
 338                                                    const struct pipe_rasterizer_state *rs_state)
 339 {
 340    struct virgl_context *vctx = virgl_context(ctx);
 341    uint32_t handle;
 342    handle = virgl_object_assign_handle();
 343
 344    virgl_encode_rasterizer_state(vctx, handle, rs_state);
 345    return (void *)(unsigned long)handle;
 346 }
 347
 348 static void virgl_bind_rasterizer_state(struct pipe_context *ctx,
 349                                                 void *rs_state)
 350 {
 351    struct virgl_context *vctx = virgl_context(ctx);
 352    uint32_t handle = (unsigned long)rs_state;
 353
 354    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
 355 }
 356
 357 static void virgl_delete_rasterizer_state(struct pipe_context *ctx,
 358                                          void *rs_state)
 359 {
 360    struct virgl_context *vctx = virgl_context(ctx);
 361    uint32_t handle = (unsigned long)rs_state;
 362    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_RASTERIZER);
 363 }
 364
 365 static void virgl_set_framebuffer_state(struct pipe_context *ctx,
 366                                                 const struct pipe_framebuffer_state *state)
 367 {
 368    struct virgl_context *vctx = virgl_context(ctx);
 369
 370    vctx->framebuffer = *state;
 371    virgl_encoder_set_framebuffer_state(vctx, state);
 372    virgl_attach_res_framebuffer(vctx);
 373 }
 374
 375 static void virgl_set_viewport_states(struct pipe_context *ctx,
 376                                      unsigned start_slot,
 377                                      unsigned num_viewports,
 378                                      const struct pipe_viewport_state *state)
 379 {
 380    struct virgl_context *vctx = virgl_context(ctx);
 381    virgl_encoder_set_viewport_states(vctx, start_slot, num_viewports, state);
 382 }
 383
 384 static void *virgl_create_vertex_elements_state(struct pipe_context *ctx,
 385                                                         unsigned num_elements,
 386                                                         const struct pipe_vertex_element *elements)
 387 {
 388    struct virgl_context *vctx = virgl_context(ctx);
 389    uint32_t handle = virgl_object_assign_handle();
 390    virgl_encoder_create_vertex_elements(vctx, handle,
 391                                        num_elements, elements);
 392    return (void*)(unsigned long)handle;
 393
 394 }
 395
 396 static void virgl_delete_vertex_elements_state(struct pipe_context *ctx,
 397                                               void *ve)
 398 {
 399    struct virgl_context *vctx = virgl_context(ctx);
 400    uint32_t handle = (unsigned long)ve;
 401
 402    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
 403 }
 404
 405 static void virgl_bind_vertex_elements_state(struct pipe_context *ctx,
 406                                                      void *ve)
 407 {
 408    struct virgl_context *vctx = virgl_context(ctx);
 409    uint32_t handle = (unsigned long)ve;
 410    virgl_encode_bind_object(vctx, handle, VIRGL_OBJECT_VERTEX_ELEMENTS);
 411 }
 412
 413 static void virgl_set_vertex_buffers(struct pipe_context *ctx,
 414                                     unsigned start_slot,
 415                                     unsigned num_buffers,
 416                                     const struct pipe_vertex_buffer *buffers)
 417 {
 418    struct virgl_context *vctx = virgl_context(ctx);
 419
 420    util_set_vertex_buffers_count(vctx->vertex_buffer,
 421                                  &vctx->num_vertex_buffers,
 422                                  buffers, start_slot, num_buffers);
 423
 424    vctx->vertex_array_dirty = TRUE;
 425 }
 426
 427 static void virgl_hw_set_vertex_buffers(struct pipe_context *ctx)
 428 {
 429    struct virgl_context *vctx = virgl_context(ctx);
 430
 431    if (vctx->vertex_array_dirty) {
 432       virgl_encoder_set_vertex_buffers(vctx, vctx->num_vertex_buffers, vctx->vertex_buffer);
 433       virgl_attach_res_vertex_buffers(vctx);
 434    }
 435 }
 436
 437 static void virgl_set_stencil_ref(struct pipe_context *ctx,
 438                                  const struct pipe_stencil_ref *ref)
 439 {
 440    struct virgl_context *vctx = virgl_context(ctx);
 441    virgl_encoder_set_stencil_ref(vctx, ref);
 442 }
 443
 444 static void virgl_set_blend_color(struct pipe_context *ctx,
 445                                  const struct pipe_blend_color *color)
 446 {
 447    struct virgl_context *vctx = virgl_context(ctx);
 448    virgl_encoder_set_blend_color(vctx, color);
 449 }
 450
 451 static void virgl_hw_set_index_buffer(struct pipe_context *ctx,
 452                                      struct virgl_indexbuf *ib)
 453 {
 454    struct virgl_context *vctx = virgl_context(ctx);
 455    virgl_encoder_set_index_buffer(vctx, ib);
 456    virgl_attach_res_index_buffer(vctx, ib);
 457 }
 458
 459 static void virgl_set_constant_buffer(struct pipe_context *ctx,
 460                                      enum pipe_shader_type shader, uint index,
 461                                      const struct pipe_constant_buffer *buf)
 462 {
 463    struct virgl_context *vctx = virgl_context(ctx);
 464
 465    if (buf) {
 466       if (!buf->user_buffer){
 467          struct virgl_resource *res = virgl_resource(buf->buffer);
 468          virgl_encoder_set_uniform_buffer(vctx, shader, index, buf->buffer_offset,
 469                                           buf->buffer_size, res);
 470          pipe_resource_reference(&vctx->ubos[shader][index], buf->buffer);
 471          return;
 472       }
 473       pipe_resource_reference(&vctx->ubos[shader][index], NULL);
 474       virgl_encoder_write_constant_buffer(vctx, shader, index, buf->buffer_size / 4, buf->user_buffer);
 475    } else {
 476       virgl_encoder_write_constant_buffer(vctx, shader, index, 0, NULL);
 477       pipe_resource_reference(&vctx->ubos[shader][index], NULL);
 478    }
 479 }
 480
 481 void virgl_transfer_inline_write(struct pipe_context *ctx,
 482                                 struct pipe_resource *res,
 483                                 unsigned level,
 484                                 unsigned usage,
 485                                 const struct pipe_box *box,
 486                                 const void *data,
 487                                 unsigned stride,
 488                                 unsigned layer_stride)
 489 {
 490    struct virgl_context *vctx = virgl_context(ctx);
 491    struct virgl_screen *vs = virgl_screen(ctx->screen);
 492    struct virgl_resource *grres = virgl_resource(res);
 493    struct virgl_buffer *vbuf = virgl_buffer(res);
 494
 495    grres->clean = FALSE;
 496
 497    if (virgl_res_needs_flush_wait(vctx, &vbuf->base, usage)) {
 498       ctx->flush(ctx, NULL, 0);
 499
 500       vs->vws->resource_wait(vs->vws, vbuf->base.hw_res);
 501    }
 502
 503    virgl_encoder_inline_write(vctx, grres, level, usage,
 504                               box, data, stride, layer_stride);
 505 }
 506
 507 static void *virgl_shader_encoder(struct pipe_context *ctx,
 508                                   const struct pipe_shader_state *shader,
 509                                   unsigned type)
 510 {
 511    struct virgl_context *vctx = virgl_context(ctx);
 512    uint32_t handle;
 513    struct tgsi_token *new_tokens;
 514    int ret;
 515
 516    new_tokens = virgl_tgsi_transform(vctx, shader->tokens);
 517    if (!new_tokens)
 518       return NULL;
 519
 520    handle = virgl_object_assign_handle();
 521    /* encode VS state */
 522    ret = virgl_encode_shader_state(vctx, handle, type,
 523                                    &shader->stream_output, 0,
 524                                    new_tokens);
 525    if (ret) {
 526       return NULL;
 527    }
 528
 529    FREE(new_tokens);
 530    return (void *)(unsigned long)handle;
 531
 532 }
 533 static void *virgl_create_vs_state(struct pipe_context *ctx,
 534                                    const struct pipe_shader_state *shader)
 535 {
 536    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_VERTEX);
 537 }
 538
 539 static void *virgl_create_tcs_state(struct pipe_context *ctx,
 540                                    const struct pipe_shader_state *shader)
 541 {
 542    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_CTRL);
 543 }
 544
 545 static void *virgl_create_tes_state(struct pipe_context *ctx,
 546                                    const struct pipe_shader_state *shader)
 547 {
 548    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_TESS_EVAL);
 549 }
 550
 551 static void *virgl_create_gs_state(struct pipe_context *ctx,
 552                                    const struct pipe_shader_state *shader)
 553 {
 554    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_GEOMETRY);
 555 }
 556
 557 static void *virgl_create_fs_state(struct pipe_context *ctx,
 558                                    const struct pipe_shader_state *shader)
 559 {
 560    return virgl_shader_encoder(ctx, shader, PIPE_SHADER_FRAGMENT);
 561 }
 562
 563 static void
 564 virgl_delete_fs_state(struct pipe_context *ctx,
 565                      void *fs)
 566 {
 567    uint32_t handle = (unsigned long)fs;
 568    struct virgl_context *vctx = virgl_context(ctx);
 569
 570    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 571 }
 572
 573 static void
 574 virgl_delete_gs_state(struct pipe_context *ctx,
 575                      void *gs)
 576 {
 577    uint32_t handle = (unsigned long)gs;
 578    struct virgl_context *vctx = virgl_context(ctx);
 579
 580    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 581 }
 582
 583 static void
 584 virgl_delete_vs_state(struct pipe_context *ctx,
 585                      void *vs)
 586 {
 587    uint32_t handle = (unsigned long)vs;
 588    struct virgl_context *vctx = virgl_context(ctx);
 589
 590    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 591 }
 592
 593 static void
 594 virgl_delete_tcs_state(struct pipe_context *ctx,
 595                        void *tcs)
 596 {
 597    uint32_t handle = (unsigned long)tcs;
 598    struct virgl_context *vctx = virgl_context(ctx);
 599
 600    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 601 }
 602
 603 static void
 604 virgl_delete_tes_state(struct pipe_context *ctx,
 605                       void *tes)
 606 {
 607    uint32_t handle = (unsigned long)tes;
 608    struct virgl_context *vctx = virgl_context(ctx);
 609
 610    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
 611 }
 612
 613 static void virgl_bind_vs_state(struct pipe_context *ctx,
 614                                         void *vss)
 615 {
 616    uint32_t handle = (unsigned long)vss;
 617    struct virgl_context *vctx = virgl_context(ctx);
 618
 619    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_VERTEX);
 620 }
 621
 622 static void virgl_bind_tcs_state(struct pipe_context *ctx,
 623                                void *vss)
 624 {
 625    uint32_t handle = (unsigned long)vss;
 626    struct virgl_context *vctx = virgl_context(ctx);
 627
 628    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_CTRL);
 629 }
 630
 631 static void virgl_bind_tes_state(struct pipe_context *ctx,
 632                                void *vss)
 633 {
 634    uint32_t handle = (unsigned long)vss;
 635    struct virgl_context *vctx = virgl_context(ctx);
 636
 637    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_TESS_EVAL);
 638 }
 639
 640 static void virgl_bind_gs_state(struct pipe_context *ctx,
 641                                void *vss)
 642 {
 643    uint32_t handle = (unsigned long)vss;
 644    struct virgl_context *vctx = virgl_context(ctx);
 645
 646    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_GEOMETRY);
 647 }
 648
 649
 650 static void virgl_bind_fs_state(struct pipe_context *ctx,
 651                                         void *vss)
 652 {
 653    uint32_t handle = (unsigned long)vss;
 654    struct virgl_context *vctx = virgl_context(ctx);
 655
 656    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_FRAGMENT);
 657 }
 658
 659 static void virgl_clear(struct pipe_context *ctx,
 660                                 unsigned buffers,
 661                                 const union pipe_color_union *color,
 662                                 double depth, unsigned stencil)
 663 {
 664    struct virgl_context *vctx = virgl_context(ctx);
 665
 666    virgl_encode_clear(vctx, buffers, color, depth, stencil);
 667 }
 668
 669 static void virgl_draw_vbo(struct pipe_context *ctx,
 670                                    const struct pipe_draw_info *dinfo)
 671 {
 672    struct virgl_context *vctx = virgl_context(ctx);
 673    struct virgl_screen *rs = virgl_screen(ctx->screen);
 674    struct virgl_indexbuf ib = {};
 675    struct pipe_draw_info info = *dinfo;
 676
 677    if (!dinfo->count_from_stream_output && !dinfo->indirect &&
 678        !dinfo->primitive_restart &&
 679        !u_trim_pipe_prim(dinfo->mode, (unsigned*)&dinfo->count))
 680       return;
 681
 682    if (!(rs->caps.caps.v1.prim_mask & (1 << dinfo->mode))) {
 683       util_primconvert_draw_vbo(vctx->primconvert, dinfo);
 684       return;
 685    }
 686    if (info.index_size) {
 687            pipe_resource_reference(&ib.buffer, info.has_user_indices ? NULL : info.index.resource);
 688            ib.user_buffer = info.has_user_indices ? info.index.user : NULL;
 689            ib.index_size = dinfo->index_size;
 690            ib.offset = info.start * ib.index_size;
 691
 692            if (ib.user_buffer) {
 693                    u_upload_data(vctx->uploader, 0, info.count * ib.index_size, 256,
 694                                  ib.user_buffer, &ib.offset, &ib.buffer);
 695                    ib.user_buffer = NULL;
 696            }
 697    }
 698
 699    u_upload_unmap(vctx->uploader);
 700
 701    vctx->num_draws++;
 702    virgl_hw_set_vertex_buffers(ctx);
 703    if (info.index_size)
 704       virgl_hw_set_index_buffer(ctx, &ib);
 705
 706    virgl_encoder_draw_vbo(vctx, &info);
 707
 708    pipe_resource_reference(&ib.buffer, NULL);
 709
 710 }
 711
 712 static void virgl_flush_eq(struct virgl_context *ctx, void *closure)
 713 {
 714    struct virgl_screen *rs = virgl_screen(ctx->base.screen);
 715
 716    /* send the buffer to the remote side for decoding */
 717    ctx->num_transfers = ctx->num_draws = 0;
 718    rs->vws->submit_cmd(rs->vws, ctx->cbuf);
 719
 720    virgl_encoder_set_sub_ctx(ctx, ctx->hw_sub_ctx_id);
 721
 722    /* add back current framebuffer resources to reference list? */
 723    virgl_reemit_res(ctx);
 724 }
 725
 726 static void virgl_flush_from_st(struct pipe_context *ctx,
 727                                struct pipe_fence_handle **fence,
 728                                enum pipe_flush_flags flags)
 729 {
 730    struct virgl_context *vctx = virgl_context(ctx);
 731    struct virgl_screen *rs = virgl_screen(ctx->screen);
 732    struct virgl_buffer *buf, *tmp;
 733
 734    if (fence)
 735       *fence = rs->vws->cs_create_fence(rs->vws);
 736
 737    LIST_FOR_EACH_ENTRY_SAFE(buf, tmp, &vctx->to_flush_bufs, flush_list) {
 738       struct pipe_resource *res = &buf->base.u.b;
 739       virgl_buffer_flush(vctx, buf);
 740       list_del(&buf->flush_list);
 741       buf->on_list = FALSE;
 742       pipe_resource_reference(&res, NULL);
 743
 744    }
 745    virgl_flush_eq(vctx, vctx);
 746 }
 747
 748 static struct pipe_sampler_view *virgl_create_sampler_view(struct pipe_context *ctx,
 749                                       struct pipe_resource *texture,
 750                                       const struct pipe_sampler_view *state)
 751 {
 752    struct virgl_context *vctx = virgl_context(ctx);
 753    struct virgl_sampler_view *grview;
 754    uint32_t handle;
 755    struct virgl_resource *res;
 756
 757    if (!state)
 758       return NULL;
 759
 760    grview = CALLOC_STRUCT(virgl_sampler_view);
 761    if (!grview)
 762       return NULL;
 763
 764    res = virgl_resource(texture);
 765    handle = virgl_object_assign_handle();
 766    virgl_encode_sampler_view(vctx, handle, res, state);
 767
 768    grview->base = *state;
 769    grview->base.reference.count = 1;
 770
 771    grview->base.texture = NULL;
 772    grview->base.context = ctx;
 773    pipe_resource_reference(&grview->base.texture, texture);
 774    grview->handle = handle;
 775    return &grview->base;
 776 }
 777
 778 static void virgl_set_sampler_views(struct pipe_context *ctx,
 779                                    enum pipe_shader_type shader_type,
 780                                    unsigned start_slot,
 781                                    unsigned num_views,
 782                                    struct pipe_sampler_view **views)
 783 {
 784    struct virgl_context *vctx = virgl_context(ctx);
 785    int i;
 786    uint32_t disable_mask = ~((1ull << num_views) - 1);
 787    struct virgl_textures_info *tinfo = &vctx->samplers[shader_type];
 788    uint32_t new_mask = 0;
 789    uint32_t remaining_mask;
 790
 791    remaining_mask = tinfo->enabled_mask & disable_mask;
 792
 793    while (remaining_mask) {
 794       i = u_bit_scan(&remaining_mask);
 795       assert(tinfo->views[i]);
 796
 797       pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
 798    }
 799
 800    for (i = 0; i < num_views; i++) {
 801       struct virgl_sampler_view *grview = virgl_sampler_view(views[i]);
 802
 803       if (views[i] == (struct pipe_sampler_view *)tinfo->views[i])
 804          continue;
 805
 806       if (grview) {
 807          new_mask |= 1 << i;
 808          pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], views[i]);
 809       } else {
 810          pipe_sampler_view_reference((struct pipe_sampler_view **)&tinfo->views[i], NULL);
 811          disable_mask |= 1 << i;
 812       }
 813    }
 814
 815    tinfo->enabled_mask &= ~disable_mask;
 816    tinfo->enabled_mask |= new_mask;
 817    virgl_encode_set_sampler_views(vctx, shader_type, start_slot, num_views, tinfo->views);
 818    virgl_attach_res_sampler_views(vctx, shader_type);
 819 }
 820
 821 static void
 822 virgl_texture_barrier(struct pipe_context *ctx, unsigned flags)
 823 {
 824    struct virgl_context *vctx = virgl_context(ctx);
 825    struct virgl_screen *rs = virgl_screen(ctx->screen);
 826
 827    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_TEXTURE_BARRIER))
 828       return;
 829    virgl_encode_texture_barrier(vctx, flags);
 830 }
 831
 832 static void virgl_destroy_sampler_view(struct pipe_context *ctx,
 833                                  struct pipe_sampler_view *view)
 834 {
 835    struct virgl_context *vctx = virgl_context(ctx);
 836    struct virgl_sampler_view *grview = virgl_sampler_view(view);
 837
 838    virgl_encode_delete_object(vctx, grview->handle, VIRGL_OBJECT_SAMPLER_VIEW);
 839    pipe_resource_reference(&view->texture, NULL);
 840    FREE(view);
 841 }
 842
 843 static void *virgl_create_sampler_state(struct pipe_context *ctx,
 844                                         const struct pipe_sampler_state *state)
 845 {
 846    struct virgl_context *vctx = virgl_context(ctx);
 847    uint32_t handle;
 848
 849    handle = virgl_object_assign_handle();
 850
 851    virgl_encode_sampler_state(vctx, handle, state);
 852    return (void *)(unsigned long)handle;
 853 }
 854
 855 static void virgl_delete_sampler_state(struct pipe_context *ctx,
 856                                       void *ss)
 857 {
 858    struct virgl_context *vctx = virgl_context(ctx);
 859    uint32_t handle = (unsigned long)ss;
 860
 861    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SAMPLER_STATE);
 862 }
 863
 864 static void virgl_bind_sampler_states(struct pipe_context *ctx,
 865                                      enum pipe_shader_type shader,
 866                                      unsigned start_slot,
 867                                      unsigned num_samplers,
 868                                      void **samplers)
 869 {
 870    struct virgl_context *vctx = virgl_context(ctx);
 871    uint32_t handles[32];
 872    int i;
 873    for (i = 0; i < num_samplers; i++) {
 874       handles[i] = (unsigned long)(samplers[i]);
 875    }
 876    virgl_encode_bind_sampler_states(vctx, shader, start_slot, num_samplers, handles);
 877 }
 878
 879 static void virgl_set_polygon_stipple(struct pipe_context *ctx,
 880                                      const struct pipe_poly_stipple *ps)
 881 {
 882    struct virgl_context *vctx = virgl_context(ctx);
 883    virgl_encoder_set_polygon_stipple(vctx, ps);
 884 }
 885
 886 static void virgl_set_scissor_states(struct pipe_context *ctx,
 887                                     unsigned start_slot,
 888                                     unsigned num_scissor,
 889                                    const struct pipe_scissor_state *ss)
 890 {
 891    struct virgl_context *vctx = virgl_context(ctx);
 892    virgl_encoder_set_scissor_state(vctx, start_slot, num_scissor, ss);
 893 }
 894
 895 static void virgl_set_sample_mask(struct pipe_context *ctx,
 896                                  unsigned sample_mask)
 897 {
 898    struct virgl_context *vctx = virgl_context(ctx);
 899    virgl_encoder_set_sample_mask(vctx, sample_mask);
 900 }
 901
 902 static void virgl_set_min_samples(struct pipe_context *ctx,
 903                                  unsigned min_samples)
 904 {
 905    struct virgl_context *vctx = virgl_context(ctx);
 906    struct virgl_screen *rs = virgl_screen(ctx->screen);
 907
 908    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_SET_MIN_SAMPLES))
 909       return;
 910    virgl_encoder_set_min_samples(vctx, min_samples);
 911 }
 912
 913 static void virgl_set_clip_state(struct pipe_context *ctx,
 914                                 const struct pipe_clip_state *clip)
 915 {
 916    struct virgl_context *vctx = virgl_context(ctx);
 917    virgl_encoder_set_clip_state(vctx, clip);
 918 }
 919
 920 static void virgl_set_tess_state(struct pipe_context *ctx,
 921                                  const float default_outer_level[4],
 922                                  const float default_inner_level[2])
 923 {
 924    struct virgl_context *vctx = virgl_context(ctx);
 925    struct virgl_screen *rs = virgl_screen(ctx->screen);
 926
 927    if (!rs->caps.caps.v1.bset.has_tessellation_shaders)
 928       return;
 929    virgl_encode_set_tess_state(vctx, default_outer_level, default_inner_level);
 930 }
 931
 932 static void virgl_resource_copy_region(struct pipe_context *ctx,
 933                                       struct pipe_resource *dst,
 934                                       unsigned dst_level,
 935                                       unsigned dstx, unsigned dsty, unsigned dstz,
 936                                       struct pipe_resource *src,
 937                                       unsigned src_level,
 938                                       const struct pipe_box *src_box)
 939 {
 940    struct virgl_context *vctx = virgl_context(ctx);
 941    struct virgl_resource *dres = virgl_resource(dst);
 942    struct virgl_resource *sres = virgl_resource(src);
 943
 944    dres->clean = FALSE;
 945    virgl_encode_resource_copy_region(vctx, dres,
 946                                     dst_level, dstx, dsty, dstz,
 947                                     sres, src_level,
 948                                     src_box);
 949 }
 950
 951 static void
 952 virgl_flush_resource(struct pipe_context *pipe,
 953                     struct pipe_resource *resource)
 954 {
 955 }
 956
 957 static void virgl_blit(struct pipe_context *ctx,
 958                       const struct pipe_blit_info *blit)
 959 {
 960    struct virgl_context *vctx = virgl_context(ctx);
 961    struct virgl_resource *dres = virgl_resource(blit->dst.resource);
 962    struct virgl_resource *sres = virgl_resource(blit->src.resource);
 963
 964    dres->clean = FALSE;
 965    virgl_encode_blit(vctx, dres, sres,
 966                     blit);
 967 }
 968
 969 static void virgl_set_hw_atomic_buffers(struct pipe_context *ctx,
 970                                         unsigned start_slot,
 971                                         unsigned count,
 972                                         const struct pipe_shader_buffer *buffers)
 973 {
 974    struct virgl_context *vctx = virgl_context(ctx);
 975
 976    for (unsigned i = 0; i < count; i++) {
 977       unsigned idx = start_slot + i;
 978
 979       if (buffers) {
 980          if (buffers[i].buffer) {
 981             pipe_resource_reference(&vctx->atomic_buffers[idx],
 982                                     buffers[i].buffer);
 983             continue;
 984          }
 985       }
 986       pipe_resource_reference(&vctx->atomic_buffers[idx], NULL);
 987    }
 988    virgl_encode_set_hw_atomic_buffers(vctx, start_slot, count, buffers);
 989 }
 990
 991 static void virgl_set_shader_buffers(struct pipe_context *ctx,
 992                                      enum pipe_shader_type shader,
 993                                      unsigned start_slot, unsigned count,
 994                                      const struct pipe_shader_buffer *buffers)
 995 {
 996    struct virgl_context *vctx = virgl_context(ctx);
 997    struct virgl_screen *rs = virgl_screen(ctx->screen);
 998
 999    for (unsigned i = 0; i < count; i++) {
1000       unsigned idx = start_slot + i;
1001
1002       if (buffers) {
1003          if (buffers[i].buffer) {
1004             pipe_resource_reference(&vctx->ssbos[shader][idx], buffers[i].buffer);
1005             continue;
1006          }
1007       }
1008       pipe_resource_reference(&vctx->ssbos[shader][idx], NULL);
1009    }
1010
1011    uint32_t max_shader_buffer = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1012       rs->caps.caps.v2.max_shader_buffer_frag_compute :
1013       rs->caps.caps.v2.max_shader_buffer_other_stages;
1014    if (!max_shader_buffer)
1015       return;
1016    virgl_encode_set_shader_buffers(vctx, shader, start_slot, count, buffers);
1017 }
1018
1019 static void virgl_set_shader_images(struct pipe_context *ctx,
1020                                     enum pipe_shader_type shader,
1021                                     unsigned start_slot, unsigned count,
1022                                     const struct pipe_image_view *images)
1023 {
1024    struct virgl_context *vctx = virgl_context(ctx);
1025    struct virgl_screen *rs = virgl_screen(ctx->screen);
1026
1027    for (unsigned i = 0; i < count; i++) {
1028       unsigned idx = start_slot + i;
1029
1030       if (images) {
1031          if (images[i].resource) {
1032             pipe_resource_reference(&vctx->images[shader][idx], images[i].resource);
1033             continue;
1034          }
1035       }
1036       pipe_resource_reference(&vctx->images[shader][idx], NULL);
1037    }
1038
1039    uint32_t max_shader_images = (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE) ?
1040      rs->caps.caps.v2.max_shader_image_frag_compute :
1041      rs->caps.caps.v2.max_shader_image_other_stages;
1042    if (!max_shader_images)
1043       return;
1044    virgl_encode_set_shader_images(vctx, shader, start_slot, count, images);
1045 }
1046
1047 static void virgl_memory_barrier(struct pipe_context *ctx,
1048                                  unsigned flags)
1049 {
1050    struct virgl_context *vctx = virgl_context(ctx);
1051    struct virgl_screen *rs = virgl_screen(ctx->screen);
1052
1053    if (!(rs->caps.caps.v2.capability_bits & VIRGL_CAP_MEMORY_BARRIER))
1054       return;
1055    virgl_encode_memory_barrier(vctx, flags);
1056 }
1057
1058 static void *virgl_create_compute_state(struct pipe_context *ctx,
1059                                         const struct pipe_compute_state *state)
1060 {
1061    struct virgl_context *vctx = virgl_context(ctx);
1062    uint32_t handle;
1063    const struct tgsi_token *new_tokens = state->prog;
1064    struct pipe_stream_output_info so_info = {};
1065    int ret;
1066
1067    handle = virgl_object_assign_handle();
1068    ret = virgl_encode_shader_state(vctx, handle, PIPE_SHADER_COMPUTE,
1069                                    &so_info,
1070                                    state->req_local_mem,
1071                                    new_tokens);
1072    if (ret) {
1073       return NULL;
1074    }
1075
1076    return (void *)(unsigned long)handle;
1077 }
1078
1079 static void virgl_bind_compute_state(struct pipe_context *ctx, void *state)
1080 {
1081    uint32_t handle = (unsigned long)state;
1082    struct virgl_context *vctx = virgl_context(ctx);
1083
1084    virgl_encode_bind_shader(vctx, handle, PIPE_SHADER_COMPUTE);
1085 }
1086
1087 static void virgl_delete_compute_state(struct pipe_context *ctx, void *state)
1088 {
1089    uint32_t handle = (unsigned long)state;
1090    struct virgl_context *vctx = virgl_context(ctx);
1091
1092    virgl_encode_delete_object(vctx, handle, VIRGL_OBJECT_SHADER);
1093 }
1094
1095 static void virgl_launch_grid(struct pipe_context *ctx,
1096                               const struct pipe_grid_info *info)
1097 {
1098    struct virgl_context *vctx = virgl_context(ctx);
1099    virgl_encode_launch_grid(vctx, info);
1100 }
1101
1102 static void
1103 virgl_context_destroy( struct pipe_context *ctx )
1104 {
1105    struct virgl_context *vctx = virgl_context(ctx);
1106    struct virgl_screen *rs = virgl_screen(ctx->screen);
1107
1108    vctx->framebuffer.zsbuf = NULL;
1109    vctx->framebuffer.nr_cbufs = 0;
1110    virgl_encoder_destroy_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1111    virgl_flush_eq(vctx, vctx);
1112
1113    rs->vws->cmd_buf_destroy(vctx->cbuf);
1114    if (vctx->uploader)
1115       u_upload_destroy(vctx->uploader);
1116    util_primconvert_destroy(vctx->primconvert);
1117
1118    slab_destroy_child(&vctx->texture_transfer_pool);
1119    FREE(vctx);
1120 }
1121
1122 static void virgl_get_sample_position(struct pipe_context *ctx,
1123                                       unsigned sample_count,
1124                                       unsigned index,
1125                                       float *out_value)
1126 {
1127    struct virgl_context *vctx = virgl_context(ctx);
1128    struct virgl_screen *vs = virgl_screen(vctx->base.screen);
1129
1130    if (sample_count > vs->caps.caps.v1.max_samples) {
1131       debug_printf("VIRGL: requested %d MSAA samples, but only %d supported\n",
1132                    sample_count, vs->caps.caps.v1.max_samples);
1133       return;
1134    }
1135
1136    /* The following is basically copied from dri/i965gen6_get_sample_position
1137     * The only addition is that we hold the msaa positions for all sample
1138     * counts in a flat array. */
1139    uint32_t bits = 0;
1140    if (sample_count == 1) {
1141       out_value[0] = out_value[1] = 0.5f;
1142       return;
1143    } else if (sample_count == 2) {
1144       bits = vs->caps.caps.v2.sample_locations[0] >> (8 * index);
1145    } else if (sample_count <= 4) {
1146       bits = vs->caps.caps.v2.sample_locations[1] >> (8 * index);
1147    } else if (sample_count <= 8) {
1148       bits = vs->caps.caps.v2.sample_locations[2 + (index >> 2)] >> (8 * (index & 3));
1149    } else if (sample_count <= 16) {
1150       bits = vs->caps.caps.v2.sample_locations[4 + (index >> 2)] >> (8 * (index & 3));
1151    }
1152    out_value[0] = ((bits >> 4) & 0xf) / 16.0f;
1153    out_value[1] = (bits & 0xf) / 16.0f;
1154
1155    if (virgl_debug & VIRGL_DEBUG_VERBOSE)
1156       debug_printf("VIRGL: sample postion [%2d/%2d] = (%f, %f)\n",
1157                    index, sample_count, out_value[0], out_value[1]);
1158 }
1159
1160 struct pipe_context *virgl_context_create(struct pipe_screen *pscreen,
1161                                           void *priv,
1162                                           unsigned flags)
1163 {
1164    struct virgl_context *vctx;
1165    struct virgl_screen *rs = virgl_screen(pscreen);
1166    vctx = CALLOC_STRUCT(virgl_context);
1167
1168    vctx->cbuf = rs->vws->cmd_buf_create(rs->vws);
1169    if (!vctx->cbuf) {
1170       FREE(vctx);
1171       return NULL;
1172    }
1173
1174    vctx->base.destroy = virgl_context_destroy;
1175    vctx->base.create_surface = virgl_create_surface;
1176    vctx->base.surface_destroy = virgl_surface_destroy;
1177    vctx->base.set_framebuffer_state = virgl_set_framebuffer_state;
1178    vctx->base.create_blend_state = virgl_create_blend_state;
1179    vctx->base.bind_blend_state = virgl_bind_blend_state;
1180    vctx->base.delete_blend_state = virgl_delete_blend_state;
1181    vctx->base.create_depth_stencil_alpha_state = virgl_create_depth_stencil_alpha_state;
1182    vctx->base.bind_depth_stencil_alpha_state = virgl_bind_depth_stencil_alpha_state;
1183    vctx->base.delete_depth_stencil_alpha_state = virgl_delete_depth_stencil_alpha_state;
1184    vctx->base.create_rasterizer_state = virgl_create_rasterizer_state;
1185    vctx->base.bind_rasterizer_state = virgl_bind_rasterizer_state;
1186    vctx->base.delete_rasterizer_state = virgl_delete_rasterizer_state;
1187
1188    vctx->base.set_viewport_states = virgl_set_viewport_states;
1189    vctx->base.create_vertex_elements_state = virgl_create_vertex_elements_state;
1190    vctx->base.bind_vertex_elements_state = virgl_bind_vertex_elements_state;
1191    vctx->base.delete_vertex_elements_state = virgl_delete_vertex_elements_state;
1192    vctx->base.set_vertex_buffers = virgl_set_vertex_buffers;
1193    vctx->base.set_constant_buffer = virgl_set_constant_buffer;
1194
1195    vctx->base.set_tess_state = virgl_set_tess_state;
1196    vctx->base.create_vs_state = virgl_create_vs_state;
1197    vctx->base.create_tcs_state = virgl_create_tcs_state;
1198    vctx->base.create_tes_state = virgl_create_tes_state;
1199    vctx->base.create_gs_state = virgl_create_gs_state;
1200    vctx->base.create_fs_state = virgl_create_fs_state;
1201
1202    vctx->base.bind_vs_state = virgl_bind_vs_state;
1203    vctx->base.bind_tcs_state = virgl_bind_tcs_state;
1204    vctx->base.bind_tes_state = virgl_bind_tes_state;
1205    vctx->base.bind_gs_state = virgl_bind_gs_state;
1206    vctx->base.bind_fs_state = virgl_bind_fs_state;
1207
1208    vctx->base.delete_vs_state = virgl_delete_vs_state;
1209    vctx->base.delete_tcs_state = virgl_delete_tcs_state;
1210    vctx->base.delete_tes_state = virgl_delete_tes_state;
1211    vctx->base.delete_gs_state = virgl_delete_gs_state;
1212    vctx->base.delete_fs_state = virgl_delete_fs_state;
1213
1214    vctx->base.create_compute_state = virgl_create_compute_state;
1215    vctx->base.bind_compute_state = virgl_bind_compute_state;
1216    vctx->base.delete_compute_state = virgl_delete_compute_state;
1217    vctx->base.launch_grid = virgl_launch_grid;
1218
1219    vctx->base.clear = virgl_clear;
1220    vctx->base.draw_vbo = virgl_draw_vbo;
1221    vctx->base.flush = virgl_flush_from_st;
1222    vctx->base.screen = pscreen;
1223    vctx->base.create_sampler_view = virgl_create_sampler_view;
1224    vctx->base.sampler_view_destroy = virgl_destroy_sampler_view;
1225    vctx->base.set_sampler_views = virgl_set_sampler_views;
1226    vctx->base.texture_barrier = virgl_texture_barrier;
1227
1228    vctx->base.create_sampler_state = virgl_create_sampler_state;
1229    vctx->base.delete_sampler_state = virgl_delete_sampler_state;
1230    vctx->base.bind_sampler_states = virgl_bind_sampler_states;
1231
1232    vctx->base.set_polygon_stipple = virgl_set_polygon_stipple;
1233    vctx->base.set_scissor_states = virgl_set_scissor_states;
1234    vctx->base.set_sample_mask = virgl_set_sample_mask;
1235    vctx->base.set_min_samples = virgl_set_min_samples;
1236    vctx->base.set_stencil_ref = virgl_set_stencil_ref;
1237    vctx->base.set_clip_state = virgl_set_clip_state;
1238
1239    vctx->base.set_blend_color = virgl_set_blend_color;
1240
1241    vctx->base.get_sample_position = virgl_get_sample_position;
1242
1243    vctx->base.resource_copy_region = virgl_resource_copy_region;
1244    vctx->base.flush_resource = virgl_flush_resource;
1245    vctx->base.blit =  virgl_blit;
1246
1247    vctx->base.set_shader_buffers = virgl_set_shader_buffers;
1248    vctx->base.set_hw_atomic_buffers = virgl_set_hw_atomic_buffers;
1249    vctx->base.set_shader_images = virgl_set_shader_images;
1250    vctx->base.memory_barrier = virgl_memory_barrier;
1251
1252    virgl_init_context_resource_functions(&vctx->base);
1253    virgl_init_query_functions(vctx);
1254    virgl_init_so_functions(vctx);
1255
1256    list_inithead(&vctx->to_flush_bufs);
1257    slab_create_child(&vctx->texture_transfer_pool, &rs->texture_transfer_pool);
1258
1259    vctx->primconvert = util_primconvert_create(&vctx->base, rs->caps.caps.v1.prim_mask);
1260    vctx->uploader = u_upload_create(&vctx->base, 1024 * 1024,
1261                                      PIPE_BIND_INDEX_BUFFER, PIPE_USAGE_STREAM, 0);
1262    if (!vctx->uploader)
1263            goto fail;
1264    vctx->base.stream_uploader = vctx->uploader;
1265    vctx->base.const_uploader = vctx->uploader;
1266
1267    vctx->hw_sub_ctx_id = rs->sub_ctx_id++;
1268    virgl_encoder_create_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1269
1270    virgl_encoder_set_sub_ctx(vctx, vctx->hw_sub_ctx_id);
1271    return &vctx->base;
1272 fail:
1273    return NULL;
1274 }